perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events
PATCH 1/1 perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events
perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events
Extent the POWER7 PMU driver with definitions for generic front-end and back-end stall events.
arch/powerpc/kernel/power7-pmu.c +2 -0
@@ -297,6 +297,8 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])static int power7_generic_events[] = { [PERF_COUNT_HW_CPU_CYCLES ] =0x1e , + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND ] =0x100f8 ,/* GCT_NOSLOT_CYC */ + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND ] =0x4000a ,/* CMPLU_STALL */ [PERF_COUNT_HW_INSTRUCTIONS ] =2 , [PERF_COUNT_HW_CACHE_REFERENCES ] =0xc880 ,/* LD_REF_L1_LSU*/ [PERF_COUNT_HW_CACHE_MISSES ] =0x400f0 ,/* LD_MISS_L1 */
Signature · 1 line
Anshuman Khandual
Quoted 4 lines
perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events
Extent the POWER7 PMU driver with definitions for generic front-end and back-end stall events.
Anshuman,
Can you explain what these P7 events actually are and how they relate to Ingo's original comment on this in 8f62242246351b5a4bc0c1f00c0c7003edea128a
Both events limit performance: most front end stalls tend to be caused by branch misprediction or instruction fetch cachemisses, backend stalls can be caused by various resource shortages or inefficient instruction scheduling.
arch/powerpc/kernel/power7-pmu.c static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) · line 300
Quoted 12 lines
Signed-off-by Anshuman Khandual <[email protected]>arch/powerpc/kernel/power7-pmu.c +1
-0@@ -297,6 +297,8 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])static int power7_generic_events[] = { [PERF_COUNT_HW_CPU_CYCLES ] =0x1e , + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND ] =0x100f8 ,/* GCT_NOSLOT_CYC */
eg. Is this Global Completion Table (GCT) empty?
arch/powerpc/kernel/power7-pmu.c static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) · line 301
Quoted 1 line
arch/powerpc/kernel/power7-pmu.c +1
-0+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */
eg. Is this instruction completion stall?
Mikey
Quoted 13 lines
arch/powerpc/kernel/power7-pmu.c +0
-0[PERF_COUNT_HW_INSTRUCTIONS] = 2, [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/ [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */Signature · 8 lines
-- Anshuman Khandual _______________________________________________ Linuxppc-dev mailing list [email protected] https://lists.ozlabs.org/listinfo/linuxppc-dev
Quoted 7 lines · Michael Neuling
Quoted 4 lines
perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events
Extent the POWER7 PMU driver with definitions for generic front-end and back-end stall events.
Anshuman,
Quoted 9 lines
Can you explain what these P7 events actually are and how they relate to Ingo's original comment on this in
8f62242246351b5a4bc0c1f00c0c7003edea128aBoth events limit performance: most front end stalls tend to be caused by branch misprediction or instruction fetch cachemisses, backend stalls can be caused by various resource shortages or inefficient instruction scheduling.
As explained in Ingo's original comment, the exact definitions of the stall events are very much processor specific as different things mean different in their respective instruction pipeline. These two Power7 raw events are the closest approximation to the concept detailed in Ingo's comment.
Quoted 9 lines
Quoted 9 lines
Signed-off-by Anshuman Khandual <[email protected]>arch/powerpc/kernel/power7-pmu.c +0
-0@@ -297,6 +297,8 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
Quoted 5 lines
arch/powerpc/kernel/power7-pmu.c static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) · line 300
Quoted 3 lines
arch/powerpc/kernel/power7-pmu.c +1
-0static int power7_generic_events[] = { [PERF_COUNT_HW_CPU_CYCLES ] =0x1e , + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND ] =0x100f8 ,/* GCT_NOSLOT_CYC */ eg. Is this Global Completion Table (GCT) empty?
Yes, it means cycles when the Global Completion Table has no slots from this thread
Quoted 4 lines
arch/powerpc/kernel/power7-pmu.c static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) · line 301
Quoted 2 lines
arch/powerpc/kernel/power7-pmu.c +1
-0+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */eg. Is this instruction completion stall?
Yes, it means no groups completed and GCT not empty
Quoted 22 lines
Mikey
Quoted 13 lines
arch/powerpc/kernel/power7-pmu.c +0
-0[PERF_COUNT_HW_INSTRUCTIONS] = 2, [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/ [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */Signature · 8 lines
-- Anshuman Khandual _______________________________________________ Linuxppc-dev mailing list [email protected] https://lists.ozlabs.org/listinfo/linuxppc-dev--
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Signature · 2 lines
Anshuman Khandual LTC India
Quoted 23 lines · In message <[email protected]> you wrote:
Quoted 7 lines · Michael Neuling
Quoted 4 lines
perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events
Extent the POWER7 PMU driver with definitions for generic front-end and back-end stall events.
Anshuman,
Quoted 9 lines
Can you explain what these P7 events actually are and how they relate to Ingo's original comment on this in
8f62242246351b5a4bc0c1f00c0c7003edea128aBoth events limit performance: most front end stalls tend to be caused by branch misprediction or instruction fetch cachemisses, backend stalls can be caused by various resource shortages or inefficient instruction scheduling.
As explained in Ingo's original comment, the exact definitions of the stall events are very much processor specific as different things mean different in their respective instruction pipeline. These two Power7 raw events are the closest approximation to the concept detailed in Ingo's comment.
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Quoted 1 line
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arch/powerpc/kernel/power7
Quoted 3 lines
Signed-off-by Anshuman Khandual <[email protected]>arch/powerpc/kernel/power7 renamed from arch/powerpc/kernel/power7-pmu.c +0
-0
-pmu.c
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arch/powerpc/kernel/power7-pmu.c static void power7_disable_pmc(unsigned int pmc, unsig
Quoted 4 lines
index 593740f..e5d2844 100644
arch/powerpc/kernel/power7-pmu.c +0
-0@@ -297,6 +297,8 @@ static void power7_disable_pmc(unsigned int pmc, unsig
ned long mmcr[])
Quoted 9 lines
Quoted 6 lines
arch/powerpc/kernel/power7-pmu.c static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) · line 300
Quoted 4 lines
arch/powerpc/kernel/power7-pmu.c +1
-0static int power7_generic_events[] = { [PERF_COUNT_HW_CPU_CYCLES ] =0x1e , + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND ] =0x100f8 ,/* GCT_NOSLOT_CYC */ eg. Is this Global Completion Table (GCT) empty?
Yes, it means cycles when the Global Completion Table has no slots from this thread
Quoted 2 lines
Quoted 2 lines
arch/powerpc/kernel/power7-pmu.c +1
-0+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL
*/
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Quoted 2 lines
eg. Is this instruction completion stall?
Yes, it means no groups completed and GCT not empty
I agree, I think they match what Ingo is trying to achieve.
Can you add these descriptions to the patch and resubmit please?
If you can find similar events for power4/5/5+/6 that would be great too submit too.
FWIW, the patch compiles and runs for me.
Mikey
Quoted 8 lines · Michael Neuling
I agree, I think they match what Ingo is trying to achieve.
Can you add these descriptions to the patch and resubmit please?
If you can find similar events for power4/5/5+/6 that would be great too submit too.
FWIW, the patch compiles and runs for me.
I already put it in my next branch, but feel free to send a followup patch adding some comments if you think that's worthwhile.
Cheers,
Ben.