arm: Tegra: fix undefined instruction hang immediately after reset

PATCH New Tom Warren 6 participants 12 messages Dec 6, 2011 – Dec 21, 2011 1 message not in the archive Arm (32-bit)

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Tom Warren

author

2011-12-06 23:00 UTC #0 lore raw

PATCH 1/1 arm: Tegra: fix undefined instruction hang immediately after reset

commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. Result was an undefined instruction hang just after reset.

Signed-off-by Tom Warren <[email protected]>

Cc Albert Aribaud <[email protected]>

Cc Tom Rini <[email protected]>

---
 arch/arm/cpu/armv7/start.S |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

arch/arm/cpu/armv7/start.S +2 -0

index d23dc9d..ceed11e 100644
@@ -144,6 +144,7 @@ reset:
 	orr	r0, r0, #0xd3
 	msr	cpsr,r0
 
+#if !defined(CONFIG_TEGRA2)
 /*
  * Setup vector:
  * (OMAP4 spl TEXT_BASE is not 32 byte aligned.

@@ -159,6 +160,7 @@ reset:
 	ldr	r0, =_start
 	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
 #endif
+#endif	/* !Tegra2 */
 
 	/* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT

Signature · 1 line

1.7.7.1

Mike Frysinger

2011-12-08 00:14 UTC #1 lore raw

PATCH 1/1 arm: Tegra: fix undefined instruction hang immediately after reset

Quoted 12 lines · On Tuesday 06 December 2011 18:00:19 Tom Warren wrote:

commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. Result was an undefined instruction hang just after reset.
arch/arm/cpu/armv7/start.S +1 -0
 
+#if !defined(CONFIG_TEGRA2)
 /*
  * Setup vector:
  * (OMAP4 spl TEXT_BASE is not 32 byte aligned.

arch/arm/cpu/armv7/start.S reset: · line 163

Quoted 4 lines

arch/arm/cpu/armv7/start.S +1 -0

@@ -159,6 +160,7 @@ reset:
 	ldr	r0, =_start
 	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
 #endif
+#endif	/* !Tegra2 */

forgive my ignorance, but would it be better to invert the logic ? have ARM cores that do have a CP15 define CONFIG_ARM_CP15 (or whatever) and then put all this logic behind that rather than grow a list of SoC's that lack it ? -mike
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Aneesh V

2011-12-08 05:51 UTC #2 lore raw

PATCH 1/1 arm: Tegra: fix undefined instruction hang immediately after reset

Mike,

Quoted 8 lines · Mike Frysinger

Quoted 7 lines · On Tuesday 06 December 2011 18:00:19 Tom Warren wrote:
commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. Result was an undefined instruction hang just after reset.
arch/arm/cpu/armv7/start.S +0 -0

Quoted 14 lines

arch/arm/cpu/armv7/start.S reset: · line 163
Quoted 9 lines
arch/arm/cpu/armv7/start.S +2 -0
+#if !defined(CONFIG_TEGRA2)
  /*
   * Setup vector:
   * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
@@ -159,6 +160,7 @@ reset:
  	ldr	r0, =_start
  	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
  #endif
+#endif	/* !Tegra2 */
forgive my ignorance, but would it be better to invert the logic ? have ARM cores that do have a CP15 define CONFIG_ARM_CP15 (or whatever) and then put all this logic behind that rather than grow a list of SoC's that lack it ? -mike

As far as I understand CP15 is typically available(if not mandatory) on all armv7 processors. Here, IIUC, NVidia has a peculiar architecture that necessitates an armv4 processor supported by armv7 code. IMHO, this is the exceptional case.

br,
Aneesh

Mike Frysinger

2011-12-08 06:25 UTC #3 lore raw

PATCH 1/1 arm: Tegra: fix undefined instruction hang immediately after reset

Quoted 29 lines · On Thursday 08 December 2011 00:51:01 Aneesh V wrote:

Quoted 19 lines · Mike Frysinger
Quoted 18 lines · On Tuesday 06 December 2011 18:00:19 Tom Warren wrote:
commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. Result was an undefined instruction hang just after reset.
arch/arm/cpu/armv7/start.S +1 -0
 
+#if !defined(CONFIG_TEGRA2)
 
  /*
 
   * Setup vector:
   * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
@@ -159,6 +160,7 @@ reset:
  	ldr	r0, =_start
  	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
 
Quoted 8 lines
arch/arm/cpu/armv7/start.S reset: · line 163
Quoted 3 lines
arch/arm/cpu/armv7/start.S +1 -0
  #endif
 
+#endif	/* !Tegra2 */
forgive my ignorance, but would it be better to invert the logic ? have ARM cores that do have a CP15 define CONFIG_ARM_CP15 (or whatever) and then put all this logic behind that rather than grow a list of SoC's that lack it ?

Quoted 4 lines

As far as I understand CP15 is typically available(if not mandatory) on all armv7 processors. Here, IIUC, NVidia has a peculiar architecture that necessitates an armv4 processor supported by armv7 code. IMHO, this is the exceptional case.

np then ... thanks
-mike
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Tom Warren

2011-12-08 15:37 UTC #4 lore raw

PATCH 1/1 arm: Tegra: fix undefined instruction hang immediately after reset

In reply to Aneesh V

Aneesh & Mike,

Quoted 32 lines

-----Original Message-----
From: Aneesh V [mailto:aneesh at ti.com]
Sent: Wednesday, December 07, 2011 10:51 PM
To: Mike Frysinger
Cc: u-boot at lists.denx.de; trini at ti.com; Tom Warren; Tom Warren
Subject: Re: [U-Boot] [PATCH] arm: Tegra: fix undefined instruction hang immediately after reset
Mike,
Quoted 8 lines · Mike Frysinger
Quoted 7 lines · On Tuesday 06 December 2011 18:00:19 Tom Warren wrote:
commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. Result was an undefined instruction hang just after reset.
arch/arm/cpu/armv7/start.S +0 -0
Quoted 13 lines
arch/arm/cpu/armv7/start.S reset: · line 163
Quoted 9 lines
arch/arm/cpu/armv7/start.S +2 -0
+#if !defined(CONFIG_TEGRA2)
  /*
   * Setup vector:
   * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
@@ -159,6 +160,7 @@ reset:
  	ldr	r0, =_start
  	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
  #endif
+#endif	/* !Tegra2 */
forgive my ignorance, but would it be better to invert the logic ? have ARM cores that do have a CP15 define CONFIG_ARM_CP15 (or whatever) and then put all this logic behind that rather than grow a list

Quoted 7 lines

of SoC's that lack it ?
Quoted 1 line
-mike
As far as I understand CP15 is typically available(if not mandatory) on all armv7 processors. Here, IIUC, NVidia has a peculiar architecture that necessitates an armv4 processor supported by armv7 code. IMHO, this is the exceptional case.

Tegra has (at least) 2 ARM processors - the AVP, which is ARM7TDMI-based and hence has no CP15, and the CPU complex, which as 2 or more A9 CPUs. Since the AVP is the boot processor, it runs the initial U-Boot code (start.S) and will eventually setup and kick off the CPU(s) to run the bulk of U-Boot.

Perhaps we should be in our own arch/arm/cpu/arm7tdmi subdir, but that's a major change from the current structure. Is it possible for this code ("Setup vector") to only be defined for OMAP processor builds? The code it replaces was ifdef'd for OMAP3, and had no affect on Tegra builds.

Unless some other SoC decides to use an ARM7TDMI-S boot proc, though, the CONFIG_TEGRA2 fencing should be the only one necessary.

Tom

Quoted 3 lines

br,
Aneesh

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Aneesh V

2011-12-09 06:18 UTC #5 lore raw

PATCH 1/1 arm: Tegra: fix undefined instruction hang immediately after reset

Tom,

Quoted 37 lines · Tom Warren

Aneesh& Mike,
Quoted 35 lines
-----Original Message-----
From: Aneesh V [mailto:aneesh at ti.com]
Sent: Wednesday, December 07, 2011 10:51 PM
To: Mike Frysinger
Cc: u-boot at lists.denx.de; trini at ti.com; Tom Warren; Tom Warren
Subject: Re: [U-Boot] [PATCH] arm: Tegra: fix undefined instruction hang immediately after reset
Mike,
Quoted 8 lines · Mike Frysinger
Quoted 7 lines · On Tuesday 06 December 2011 18:00:19 Tom Warren wrote:
commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. Result was an undefined instruction hang just after reset.
arch/arm/cpu/armv7/start.S +0 -0
Quoted 13 lines
arch/arm/cpu/armv7/start.S reset: · line 163
Quoted 9 lines
arch/arm/cpu/armv7/start.S +2 -0
+#if !defined(CONFIG_TEGRA2)
   /*
    * Setup vector:
    * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
@@ -159,6 +160,7 @@ reset:
   	ldr	r0, =_start
   	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
   #endif
+#endif	/* !Tegra2 */
forgive my ignorance, but would it be better to invert the logic ? have ARM cores that do have a CP15 define CONFIG_ARM_CP15 (or whatever) and then put all this logic behind that rather than grow a list
of SoC's that lack it ?
Quoted 1 line
-mike

Quoted 8 lines

Quoted 4 lines
As far as I understand CP15 is typically available(if not mandatory) on all armv7 processors. Here, IIUC, NVidia has a peculiar architecture that necessitates an armv4 processor supported by armv7 code. IMHO, this is the exceptional case.
Tegra has (at least) 2 ARM processors - the AVP, which is ARM7TDMI-based and hence has no CP15, and the CPU complex, which as 2 or more A9 CPUs. Since the AVP is the boot processor, it runs the initial U-Boot code (start.S) and will eventually setup and kick off the CPU(s) to run the bulk of U-Boot.
Perhaps we should be in our own arch/arm/cpu/arm7tdmi subdir, but that's a major change from the current structure. Is it possible for this code ("Setup vector") to only be defined for OMAP processor builds? The code it replaces was ifdef'd for OMAP3, and had no affect on Tegra builds.

I think setting up vector is useful for all platforms and I think this is the right place to do it. Just that we didn't have it till now ecept for OMAP3 and OMAP3 was doing it in a round-about way.

Quoted 2 lines

Unless some other SoC decides to use an ARM7TDMI-S boot proc, though, the CONFIG_TEGRA2 fencing should be the only one necessary.

I agree. I don't think there will be many more exceptions like this. We can live with that #ifdef. Not sure what Albert thinks though.

Quoted 11 lines

Tom
Quoted 3 lines
br,
Aneesh
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A message that is not in the archive (sent off-list or not yet received): [email protected]

Tom Warren

author

2011-12-20 23:27 UTC #7 lore raw

PATCH 1/1 arm: Tegra: fix undefined instruction hang immediately after reset

This is needed for v2011.12-rc2. I'm using my Google email because I seem to be getting blocked by base64 MIME crap w/Outlook.

Tom

Quoted 102 lines · Tom Warren

[Resending due to Outlook Base64 MIME issues. Sorry if you get spammed w/multiple copies]
Wolfgang/Albert,
This needs to be added to v2011.12-rc1 or Tegra2 builds/boards will be DOA.
Thanks,
Tom
Quoted 91 lines
-----Original Message-----
From: Aneesh V [mailto:aneesh at ti.com]
Sent: Thursday, December 08, 2011 11:18 PM
To: Tom Warren
Cc: Mike Frysinger; u-boot at lists.denx.de; trini at ti.com; Tom Warren; Albert Aribaud
Subject: Re: [U-Boot] [PATCH] arm: Tegra: fix undefined instruction hang immediately after reset
Tom,
Quoted 38 lines · Tom Warren
Aneesh& ?Mike,
Quoted 36 lines
-----Original Message-----
From: Aneesh V [mailto:aneesh at ti.com]
Sent: Wednesday, December 07, 2011 10:51 PM
To: Mike Frysinger
Cc: u-boot at lists.denx.de; trini at ti.com; Tom Warren; Tom Warren
Subject: Re: [U-Boot] [PATCH] arm: Tegra: fix undefined instruction hang immediately after reset
Mike,
Quoted 8 lines · Mike Frysinger
Quoted 7 lines · On Tuesday 06 December 2011 18:00:19 Tom Warren wrote:
commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. Result was an undefined instruction hang just after reset.
arch/arm/cpu/armv7/start.S +0 -0
Quoted 14 lines
Quoted 9 lines
+#if !defined(CONFIG_TEGRA2)
? ?/*
? ? * Setup vector:
? ? * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
arch/arm/cpu/armv7/start.S +0 -0
@@ -159,6 +160,7 @@ reset:
? ? ? ? ?ldr ? ? r0, =_start
? ? ? ? ?mcr ? ? p15, 0, r0, c12, c0, 0 ?@Set VBAR ? ?#endif
+#endif ?/* !Tegra2 */
forgive my ignorance, but would it be better to invert the logic ? have ARM cores that do have a CP15 define CONFIG_ARM_CP15 (or whatever) and then put all this logic behind that rather than grow a list
of SoC's that lack it ?
Quoted 1 line
-mike
Quoted 7 lines
Quoted 5 lines
As far as I understand CP15 is typically available(if not mandatory) on all
armv7 processors. Here, IIUC, NVidia has a peculiar architecture that necessitates an armv4 processor supported by armv7 code. IMHO, this is the exceptional case.
Tegra has (at least) 2 ARM processors - the AVP, which is ARM7TDMI-based
and hence has no CP15, and the CPU complex, which as 2 or more A9 CPUs. Since the AVP is the boot processor, it runs the initial U-Boot code (start.S) and will eventually setup and kick off the CPU(s) to run the bulk of U-Boot.
Quoted 2 lines
Perhaps we should be in our own arch/arm/cpu/arm7tdmi subdir, but that's a
major change from the current structure. Is it possible for this code ("Setup vector") to only be defined for OMAP processor builds? The code it replaces was ifdef'd for OMAP3, and had no affect on Tegra builds.
I think setting up vector is useful for all platforms and I think this is the right place to do it. Just that we didn't have it till now ecept for OMAP3 and OMAP3 was doing it in a round-about way.
Quoted 2 lines
Unless some other SoC decides to use an ARM7TDMI-S boot proc, though, the
CONFIG_TEGRA2 fencing should be the only one necessary.
I agree. I don't think there will be many more exceptions like this. We can live with that #ifdef. Not sure what Albert thinks though.
Quoted 13 lines
Tom
Quoted 3 lines
br,
Aneesh
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------------- This email message is for the sole use of the intended recipient(s) and may contain confidential information. ?Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message.
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Simon Glass

2011-12-21 04:07 UTC #8 lore raw

PATCH 1/1 arm: Tegra: fix undefined instruction hang immediately after reset

Hi,

Quoted 4 lines · Tom Warren

This is needed for v2011.12-rc2. I'm using my Google email because I seem to be getting blocked by base64 MIME crap w/Outlook.
Tom

Yes please! Tegra is broken in mainline without this patch.

Regards,
Simon

Quoted 108 lines · Tom Warren

Quoted 102 lines
[Resending due to Outlook Base64 MIME issues. Sorry if you get spammed w/multiple copies]
Wolfgang/Albert,
This needs to be added to v2011.12-rc1 or Tegra2 builds/boards will be DOA.
Thanks,
Tom
Quoted 91 lines
-----Original Message-----
From: Aneesh V [mailto:aneesh at ti.com]
Sent: Thursday, December 08, 2011 11:18 PM
To: Tom Warren
Cc: Mike Frysinger; u-boot at lists.denx.de; trini at ti.com; Tom Warren; Albert Aribaud
Subject: Re: [U-Boot] [PATCH] arm: Tegra: fix undefined instruction hang immediately after reset
Tom,
Quoted 38 lines · Tom Warren
Aneesh& ?Mike,
Quoted 36 lines
-----Original Message-----
From: Aneesh V [mailto:aneesh at ti.com]
Sent: Wednesday, December 07, 2011 10:51 PM
To: Mike Frysinger
Cc: u-boot at lists.denx.de; trini at ti.com; Tom Warren; Tom Warren
Subject: Re: [U-Boot] [PATCH] arm: Tegra: fix undefined instruction hang immediately after reset
Mike,
Quoted 8 lines · Mike Frysinger
Quoted 7 lines · On Tuesday 06 December 2011 18:00:19 Tom Warren wrote:
commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. Result was an undefined instruction hang just after reset.
arch/arm/cpu/armv7/start.S +0 -0
Quoted 14 lines
Quoted 9 lines
+#if !defined(CONFIG_TEGRA2)
? ?/*
? ? * Setup vector:
? ? * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
arch/arm/cpu/armv7/start.S +0 -0
@@ -159,6 +160,7 @@ reset:
? ? ? ? ?ldr ? ? r0, =_start
? ? ? ? ?mcr ? ? p15, 0, r0, c12, c0, 0 ?@Set VBAR ? ?#endif
+#endif ?/* !Tegra2 */
forgive my ignorance, but would it be better to invert the logic ? have ARM cores that do have a CP15 define CONFIG_ARM_CP15 (or whatever) and then put all this logic behind that rather than grow a list
of SoC's that lack it ?
Quoted 1 line
-mike
Quoted 7 lines
Quoted 5 lines
As far as I understand CP15 is typically available(if not mandatory) on all
armv7 processors. Here, IIUC, NVidia has a peculiar architecture that necessitates an armv4 processor supported by armv7 code. IMHO, this is the exceptional case.
Tegra has (at least) 2 ARM processors - the AVP, which is ARM7TDMI-based
and hence has no CP15, and the CPU complex, which as 2 or more A9 CPUs. Since the AVP is the boot processor, it runs the initial U-Boot code (start.S) and will eventually setup and kick off the CPU(s) to run the bulk of U-Boot.
Quoted 2 lines
Perhaps we should be in our own arch/arm/cpu/arm7tdmi subdir, but that's a
major change from the current structure. Is it possible for this code ("Setup vector") to only be defined for OMAP processor builds? The code it replaces was ifdef'd for OMAP3, and had no affect on Tegra builds.
I think setting up vector is useful for all platforms and I think this is the right place to do it. Just that we didn't have it till now ecept for OMAP3 and OMAP3 was doing it in a round-about way.
Quoted 2 lines
Unless some other SoC decides to use an ARM7TDMI-S boot proc, though, the
CONFIG_TEGRA2 fencing should be the only one necessary.
I agree. I don't think there will be many more exceptions like this. We can live with that #ifdef. Not sure what Albert thinks though.
Quoted 13 lines
Tom
Quoted 3 lines
br,
Aneesh
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------------- This email message is for the sole use of the intended recipient(s) and may contain confidential information. ?Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message.
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Wolfgang Denk

2011-12-21 06:58 UTC #9 lore raw

PATCH 1/1 arm: Tegra: fix undefined instruction hang immediately after reset

In reply to Tom Warren

Dear Tom Warren,

Quoted 2 lines · In message <CA+m5__LR57F=KtOTMSE9SwB-zqmQJNknksg3rOR+9_aPfhZnAA@mail.gmail.com>…

This is needed for v2011.12-rc2. I'm using my Google email because I seem to be getting blocked by base64 MIME crap w/Outlook.

This has received a number of comments, but not a single ACK so far.

Do all agree that his shall go in?

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
For those who like this sort of thing, this is the sort of thing they
like.                                               - Abraham Lincoln

Aneesh V

2011-12-21 08:02 UTC #10 lore raw

PATCH 1/1 arm: Tegra: fix undefined instruction hang immediately after reset

In reply to Tom Warren

Hi Tom,

Quoted 24 lines · Tom Warren

commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. Result was an undefined instruction hang just after reset.
Signed-off-by Tom Warren<[email protected]>
Cc Albert Aribaud<[email protected]>
Cc Tom Rini<[email protected]>
---
  arch/arm/cpu/armv7/start.S |    2 ++
  1 files changed, 2 insertions(+), 0 deletions(-)
arch/arm/cpu/armv7/start.S +1 -0
index d23dc9d..ceed11e 100644
@@ -144,6 +144,7 @@ reset:
  	orr	r0, r0, #0xd3
  	msr	cpsr,r0
 
+#if !defined(CONFIG_TEGRA2)
  /*
   * Setup vector:
   * (OMAP4 spl TEXT_BASE is not 32 byte aligned.

arch/arm/cpu/armv7/start.S reset: · line 166

Quoted 7 lines

arch/arm/cpu/armv7/start.S +1 -0

@@ -159,6 +160,7 @@ reset:
  	ldr	r0, =_start
  	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
  #endif
+#endif	/* !Tegra2 */
 
  	/* the mask ROM code should have PLL and others stable */
  #ifndef CONFIG_SKIP_LOWLEVEL_INIT

FWIW,

Acked-by Aneesh V <[email protected]>

Tom Warren

author

2011-12-21 16:10 UTC #11 lore raw

PATCH 1/1 arm: Tegra: fix undefined instruction hang immediately after reset

Thanks, Aneesh.

Quoted 41 lines · Aneesh V

Hi Tom,
Quoted 30 lines · Tom Warren
commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. Result was an undefined instruction hang just after reset.
Signed-off-by Tom Warren<[email protected]>
Cc Albert Aribaud<[email protected]>
Cc Tom Rini<[email protected]>
---
?arch/arm/cpu/armv7/start.S | ? ?2 ++
?1 files changed, 2 insertions(+), 0 deletions(-)
arch/arm/cpu/armv7/start.S +0 -0
index d23dc9d..ceed11e 100644
@@ -144,6 +144,7 @@ reset:
? ? ? ?orr ? ? r0, r0, #0xd3
? ? ? ?msr ? ? cpsr,r0
+#if !defined(CONFIG_TEGRA2)
?/*
? * Setup vector:
? * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
arch/arm/cpu/armv7/start.S +0 -0
@@ -159,6 +160,7 @@ reset:
? ? ? ?ldr ? ? r0, =_start
? ? ? ?mcr ? ? p15, 0, r0, c12, c0, 0 ?@Set VBAR
?#endif
+#endif /* !Tegra2 */
Quoted 2 lines
? ? ? ?/* the mask ROM code should have PLL and others stable */ ?#ifndef CONFIG_SKIP_LOWLEVEL_INIT
FWIW,
Acked-by Aneesh V <[email protected]>

Wolfgang Denk

Applied

2011-12-21 19:37 UTC #12 lore raw

PATCH 1/1 arm: Tegra: fix undefined instruction hang immediately after reset

In reply to Tom Warren

Dear Tom Warren,

Quoted 10 lines · In message <[email protected]> you wrote:

commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. Result was an undefined instruction hang just after reset.
Signed-off-by Tom Warren <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/start.S |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

Applied, thanks.

Albert: hope this is OK with you.

Best regards,

Wolfgang Denk

Signature · 6 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
They're usually so busy thinking about what  happens  next  that  the
only  time they ever find out what is happening now is when they come
to look back on it.                 - Terry Pratchett, _Wyrd Sisters_