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drm/i915: set interlaced bits for TRANSCONF

PATCH Applied Paulo Zanoni 3 participants 5 messages Feb 3, 2012 – Feb 10, 2012

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DRM drivers Intel i915
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Paulo Zanoni

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#0 lore raw

PATCH 1/2 drm/i915: set interlaced bits for TRANSCONF

From: Paulo Zanoni <[email protected]>

I'm not sure why they are needed (I didn't notice any difference in my tests), but these bits are in our documentation and they are also set by the Windows driver.

Signed-off-by Paulo Zanoni <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h      |    2 ++
 drivers/gpu/drm/i915/intel_display.c |   12 ++++++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

Apply on top of danvet's interlaced branch. This seems to be the last
difference between Windows and Linux that is related to interlaced
modes.

drivers/gpu/drm/i915/i915_reg.h +2 -0
index bcd5cce..98494d6 100644
@@ -3294,7 +3294,9 @@
 #define  TRANS_FSYNC_DELAY_HB4  (3<<27)
 #define  TRANS_DP_AUDIO_ONLY    (1<<26)
 #define  TRANS_DP_VIDEO_AUDIO   (0<<26)
+#define  TRANS_INTERLACE_MASK   (7<<21)
 #define  TRANS_PROGRESSIVE      (0<<21)
+#define  TRANS_INTERLACED       (3<<21)
 #define  TRANS_8BPC             (0<<5)
 #define  TRANS_10BPC            (1<<5)
 #define  TRANS_6BPC             (2<<5)
drivers/gpu/drm/i915/intel_display.c +10 -2
index e842961..9d43866 100644
@@ -1262,7 +1262,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
 				    enum pipe pipe)
 {
 	int reg;
-	u32 val;
+	u32 val, pipeconf_val;
 
 	/* PCH only available on ILK+ */
 	BUG_ON(dev_priv->info->gen < 5);

@@ -1276,6 +1276,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
 
 	reg = TRANSCONF(pipe);
 	val = I915_READ(reg);
+	pipeconf_val = I915_READ(PIPECONF(pipe));
 
 	if (HAS_PCH_IBX(dev_priv->dev)) {
 		/*

@@ -1283,8 +1284,15 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
 		 * that in pipeconf reg.
 		 */
 		val &= ~PIPE_BPC_MASK;
-		val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
+		val |= pipeconf_val & PIPE_BPC_MASK;
 	}
+
+	val &= ~TRANS_INTERLACE_MASK;
+	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
+		val |= TRANS_INTERLACED;
+	else
+		val |= TRANS_PROGRESSIVE;
+
 	I915_WRITE(reg, val | TRANS_ENABLE);
 	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
 		DRM_ERROR("failed to enable transcoder %d\n", pipe);
Signature · 1 line
1.7.8.3
Reviewed-by on v1 1/2
#1 lore raw
Quoted 8 lines · On Fri, 3 Feb 2012 17:47:15 -0200 Paulo Zanoni <[email protected]> wrote:

From: Paulo Zanoni <[email protected]>

I'm not sure why they are needed (I didn't notice any difference in my tests), but these bits are in our documentation and they are also set by the Windows driver.

Signed-off-by Paulo Zanoni <[email protected]>

---

Do we pretend to support interlaced on SDVO? If so, there's a bit for that too, but only on IBX, not PPT or CPT.

Other than that,

Reviewed-by Jesse Barnes <[email protected]>
Signature · 1 line
Jesse Barnes, Intel Open Source Technology Center

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#2 lore raw
Quoted 9 lines · Jesse Barnes
Quoted 6 lines · On Fri, 3 Feb 2012 17:47:15 -0200 Paulo Zanoni <[email protected]> wrote:

From: Paulo Zanoni <[email protected]>

I'm not sure why they are needed (I didn't notice any difference in my tests), but these bits are in our documentation and they are also set by the Windows driver.

Quoted 5 lines
Quoted 2 lines
Signed-off-by Paulo Zanoni <[email protected]>

---

Do we pretend to support interlaced on SDVO? If so, there's a bit for that too, but only on IBX, not PPT or CPT.

Indeed, we do pretend. Paulo, can you whip together the follow up patch to fix that magical sdvo interlaced bit on ilk?
-Daniel

Signature · 3 lines
Daniel Vetter
Mail: [email protected]
Mobile: +41 (0)79 365 57 48
Applied
#3 lore raw
In reply to Jesse Barnes
Quoted 9 lines · Jesse Barnes
Quoted 6 lines · On Fri, 3 Feb 2012 17:47:15 -0200 Paulo Zanoni <[email protected]> wrote:

From: Paulo Zanoni <[email protected]>

I'm not sure why they are needed (I didn't notice any difference in my tests), but these bits are in our documentation and they are also set by the Windows driver.

Quoted 8 lines
Quoted 2 lines
Signed-off-by Paulo Zanoni <[email protected]>

---

Do we pretend to support interlaced on SDVO? If so, there's a bit for that too, but only on IBX, not PPT or CPT.

Other than that,

Reviewed-by Jesse Barnes <[email protected]>

Queued for -next, thanks for the patch and review. -Daniel

Signature · 3 lines
Daniel Vetter
Mail: [email protected]
Mobile: +41 (0)79 365 57 48
#4 lore raw
In reply to Paulo Zanoni
Quoted 8 lines · On Fri, 3 Feb 2012 17:47:15 -0200 Paulo Zanoni <[email protected]> wrote:

From: Paulo Zanoni <[email protected]>

I'm not sure why they are needed (I didn't notice any difference in my tests), but these bits are in our documentation and they are also set by the Windows driver.

Signed-off-by Paulo Zanoni <[email protected]>

---

This makes me think we should really just split the PCH related stuff into separate functions and headers with their own register and bit definitions. Duplicate code is better than fragility and having to scour through multiple docs when shared code is modified.

But obviously that's a much bigger cleanup that can come after this patch.

Ideally, anytime we had a register block with any different offsets or bits than a previous generation, we'd fork it into its own reg definition header and add function hooks for it.

Signature · 1 line
Jesse Barnes, Intel Open Source Technology Center

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