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dmaengine: Add context parameter to prep_dma_sg and prep_interleaved_dma

PATCH New Ravi Kumar V 1 participant 2 messages Mar 22, 2012 1 message not in the archive

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Arm (32-bit) Arm sub-architectures Arm Qualcomm mailing list Char and misc drivers +3 more subsystems
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A message that is not in the archive (sent off-list or not yet received): [email protected]

Ravi Kumar V

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PATCH 1/2 dmaengine: Add context parameter to prep_dma_sg and prep_interleaved_dma

Add new context parameter to DMA SG and Interleaveid mode for passing per transfer specific private data, using this it enables the dma devices which needs to pass the parameters which changes per each transfer

Change-Id Ia9ee19f2c253e68b8e5ff254a57478dcc51014ca
Signed-off-by Ravi Kumar V <[email protected]>
---
 drivers/dma/fsldma.c                    |    2 +-
 drivers/dma/sirf-dma.c                  |    2 +-
 drivers/dma/ste_dma40.c                 |    2 +-
 drivers/misc/carma/carma-fpga-program.c |    2 +-
 drivers/misc/carma/carma-fpga.c         |    7 ++---
 include/linux/dmaengine.h               |   45 +++++++++++++++++++++++++++++-
 6 files changed, 50 insertions(+), 10 deletions(-)
drivers/dma/fsldma.c +1 -1
index b98070c..f9f77db 100644
@@ -645,7 +645,7 @@ fail:
 static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
 	struct scatterlist *dst_sg, unsigned int dst_nents,
 	struct scatterlist *src_sg, unsigned int src_nents,
-	unsigned long flags)
+	unsigned long flags, void *context)
 {
 	struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
 	struct fsldma_chan *chan = to_fsl_chan(dchan);
drivers/dma/sirf-dma.c +1 -1
index 2333810..ff4d344 100644
@@ -428,7 +428,7 @@ sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 
 static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved(
 	struct dma_chan *chan, struct dma_interleaved_template *xt,
-	unsigned long flags)
+	unsigned long flags, void *context)
 {
 	struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
 	struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
drivers/dma/ste_dma40.c +1 -1
index cc5ecbc..2f58ba9 100644
@@ -2287,7 +2287,7 @@ static struct dma_async_tx_descriptor *
 d40_prep_memcpy_sg(struct dma_chan *chan,
 		   struct scatterlist *dst_sg, unsigned int dst_nents,
 		   struct scatterlist *src_sg, unsigned int src_nents,
-		   unsigned long dma_flags)
+		   unsigned long dma_flags, void *context)
 {
 	if (dst_nents != src_nents)
 		return NULL;
drivers/misc/carma/carma-fpga-program.c +1 -1
index a2d25e4..3739a12 100644
@@ -530,7 +530,7 @@ static noinline int fpga_program_dma(struct fpga_dev *priv)
 	}
 
 	/* setup and submit the DMA transaction */
-	tx = chan->device->device_prep_dma_sg(chan,
+	tx = chan->device->dmaengine_prep_dma_sg(chan,
 					      table.sgl, num_pages,
 					      vb->sglist, vb->sglen, 0);
 	if (!tx) {
drivers/misc/carma/carma-fpga.c +3 -4
index 14e974b2..be0baf6 100644
@@ -638,10 +638,9 @@ static int data_submit_dma(struct fpga_device *priv, struct data_buf *buf)
 	 */
 
 	/* setup the scatterlist to scatterlist transfer */
-	tx = chan->device->device_prep_dma_sg(chan,
-					      dst_sg, dst_nents,
-					      src_sg, src_nents,
-					      0);
+	tx = dmaengine_prep_dma_sg(chan, dst_sg, dst_nents,
+					 src_sg, src_nents,
+					 0);
 	if (!tx) {
 		dev_err(priv->dev, "unable to prep scatterlist DMA\n");
 		return -ENOMEM;
include/linux/dmaengine.h +43 -2

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#2 lore raw

PATCH 2/2 DMAEngine: Add DMAEngine driver based on old MSM ADM DMA APIs

In reply to a message not in the archive

Add DMAEngine based driver using the old MSM ADM DMA APIs internally. The benefit of this approach is that not all the drivers have to get converted to DMAEngine APIs simultaneosly while both the drivers can stay enabled in the kernel. The client drivers using the old MSM APIs directly can now convert to DMAEngine one by one.

Change-Id I3647ed7b8c73b3078dfa8877a3560db3cb0a2373
Signed-off-by Ravi Kumar V <[email protected]>
---
 arch/arm/mach-msm/include/mach/dma.h |   35 ++
 drivers/dma/Kconfig                  |   12 +
 drivers/dma/Makefile                 |    1 +
 drivers/dma/msm_adm_dma.c            |  728 ++++++++++++++++++++++++++++++++++
 4 files changed, 776 insertions(+), 0 deletions(-)
 create mode 100644 drivers/dma/msm_adm_dma.c
arch/arm/mach-msm/include/mach/dma.h +35 -0
index 05583f5..95b7b15 100644
@@ -18,6 +18,36 @@
 #include <linux/list.h>
 #include <mach/msm_iomap.h>
 
+#define sg_dma_offset(sg)               ((sg)->offset)
+#define box_dma_row_address(box)        ((box)->dma_row_address)
+#define box_dma_row_len(box)            ((box)->dma_row_len)
+#define box_dma_row_num(box)            ((box)->dma_row_num)
+#define box_dma_row_offset(box)         ((box)->dma_row_offset)
+
+#define MSM_DMA_CMD_MASK		0x9FFF8
+#define MSM_DMA_CMD_SHIFT		0
+#define MSM_BOX_SRC_RLEN_MASK		0xFFFF
+#define MSM_BOX_SRC_RLEN_SHIFT		16
+#define MSM_BOX_SRC_RNUM_MASK		0xFFFF
+#define MSM_BOX_SRC_RNUM_SHIFT		16
+#define MSM_BOX_SRC_ROFFSET_MASK	0xFFFF
+#define MSM_BOX_SRC_ROFFSET_SHIFT	16
+#define MSM_BOX_DST_RLEN_MASK		0xFFFF
+#define MSM_BOX_DST_RNUM_MASK		0xFFFF
+#define MSM_BOX_DST_ROFFSET_MASK	0xFFFF
+#define MSM_BOX_MODE_CMD		0x3
+
+enum adm_flush_type {
+	ADM_FORCED_FLUSH,
+	ADM_GRACEFUL_FLUSH,
+};
+
+enum adm_dma_type {
+	ADM_SINGLE_MODE,
+	ADM_SG_MODE,
+	ADM_BOX_MODE,
+};
+
 struct msm_dmov_errdata {
 	uint32_t flush[6];
 };

@@ -32,6 +62,11 @@ struct msm_dmov_cmd {
 	void *data;
 };
 
+struct msm_adm_cmd_config {
+	uint32_t num_cmd;
+	uint32_t *cmd_cntrl;
+};
+
 #ifndef CONFIG_ARCH_MSM8X60
 void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
 void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
drivers/dma/Kconfig +12 -0
index f1a2749..1f99362 100644
@@ -252,6 +252,18 @@ config EP93XX_DMA
 	help
 	  Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
 
+config MSM_ADM_DMA
+	tristate "Qualcomm MSM ADM DMA support"
+	depends on ARCH_MSM
+	select DMA_ENGINE
+	help
+	  Support the Qualcomm DMA engine. This engine is integrated into
+	  Qualcomm chips.
+
+	  Say Y here if you have such a chipset.
+
+	  If unsure, say N.
+
 config DMA_ENGINE
 	bool
drivers/dma/Makefile +1 -0
index 009a222..f55fb57 100644
@@ -19,6 +19,7 @@ obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
 obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
 obj-$(CONFIG_IMX_SDMA) += imx-sdma.o
 obj-$(CONFIG_IMX_DMA) += imx-dma.o
+obj-$(CONFIG_MSM_ADM_DMA) += msm_adm_dma.o
 obj-$(CONFIG_MXS_DMA) += mxs-dma.o
 obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
drivers/dma/msm_adm_dma.c new file +728 -0

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