net: ll_temac: Add LL TEMAC driver to u-boot

Xilinx LocalLink Tri-Mode Ether MAC driver can be
used by Xilinx Microblaze or Xilinx ppc405/440 in
SDMA and FIFO mode. DCR or XPS bus can be used.

The driver uses and requires MII and PHYLIB.

CP: 4 warnings: 'Use of volatile is usually wrong' I won't fix this, because it depends on the network driver subsystem.

---
v10: Reduce the driver initialization code. Remove the standardized
initialization routine and all components involved. Generate unique device/bus names automaticaly on demand.

v9: Remove private Rx/Tx transfer buffer for SDMA and FIFO.
Use the PktBuf infrastruct from upper network layer. Review all the recv/send functions for SDMA and FIFO mode and insert more detailed comments.
Test with tftp put/get on ML605 and SP3ADSP1800.

v8: Remove deprecated interface: miiphy_register()
Implement MDIO bus/phy access code as independent part of driver. Make the direct PHY access code accessible for upper layer like the MDIO command.
Define proper device names for TEMAC and MII interfaces. Support of TEMAC0 and TEMAC1 at same time is prepared and should work.

v7: Call udelay() in polling loops to avoid unintended watchdog reset
Define well known timeout values in usec
Handle timeouts as error situations
Reduce duplicated code in SDMA operations
Add a real and plausible PHY detect mask
Remove ETH_HALTING code exclusion
Code cleanup as recommended
Fix typos

v6: Code cleanup with ./tools/checkpatch.pl

v5: Remove more endless loops
Remove useless parenthesis in pointer operations Move phyaddr predefinition on top
Remove supernumerary newlines
Remove parenthesis around numbers (globally)

v4: Separate fifo and sdma code from driver core
Split sdma code into separate DCR and XPS bus access code Add extensive register struct definitions and enumerations Add new callbacks into fifo an sdma code
Prepare CDMAC buffer handling to be unique for every instance Separate Xilinx specific indirect DCR access, so we can move to arch Remove useless 'emac' parameter from indirect access helper functions Correct MDIO clock setup.
Remove endless loops
Common code beautifying

v3: Use helper functions for fifo mode
Use helper functions for indirect accesses
Code cleanup
Add comments for MAGIC values
Simplify code in fifo mode

v2: Remove helper function for access to temac
Remove SDMA/FIFO/DCR macros and configure it in board Setup mac by write_hwaddr

---
 drivers/net/Makefile               |    2 +
 drivers/net/xilinx_ll_temac.c      |  399 ++++++++++++++++++++++++++++++++++++
 drivers/net/xilinx_ll_temac.h      |  310 ++++++++++++++++++++++++++++
 drivers/net/xilinx_ll_temac_fifo.c |  143 +++++++++++++
 drivers/net/xilinx_ll_temac_fifo.h |  122 +++++++++++
 drivers/net/xilinx_ll_temac_mdio.c |  180 ++++++++++++++++
 drivers/net/xilinx_ll_temac_mdio.h |   53 +++++
 drivers/net/xilinx_ll_temac_sdma.c |  370 +++++++++++++++++++++++++++++++++
 drivers/net/xilinx_ll_temac_sdma.h |  281 +++++++++++++++++++++++++
 include/netdev.h                   |   12 +
 10 files changed, 1872 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/xilinx_ll_temac.c
 create mode 100644 drivers/net/xilinx_ll_temac.h
 create mode 100644 drivers/net/xilinx_ll_temac_fifo.c
 create mode 100644 drivers/net/xilinx_ll_temac_fifo.h
 create mode 100644 drivers/net/xilinx_ll_temac_mdio.c
 create mode 100644 drivers/net/xilinx_ll_temac_mdio.h
 create mode 100644 drivers/net/xilinx_ll_temac_sdma.c
 create mode 100644 drivers/net/xilinx_ll_temac_sdma.h

index f4f7ea3..430f90c 100644
@@ -77,6 +77,8 @@ COBJS-$(CONFIG_ULI526X) += uli526x.o
 COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
 COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
 COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
+COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
+		xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
 
 COBJS	:= $(sort $(COBJS-y))
 SRCS	:= $(COBJS:.o=.c)

index b0c21d5..4724717 100644
@@ -102,6 +102,18 @@ int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
 							unsigned long dma_addr);
 int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
 							int txpp, int rxpp);
+int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
+						unsigned long ctrl_addr);
+
+/*
+ * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
+ * exported by a public hader file, we need a global definition@this point.
+ */
+#if defined(CONFIG_XILINX_LL_TEMAC)
+#define XILINX_LL_TEMAC_M_FIFO		0	/* use FIFO Ctrl */
+#define XILINX_LL_TEMAC_M_SDMA_PLB	(1 << 0)/* use SDMA Ctrl via PLB */
+#define XILINX_LL_TEMAC_M_SDMA_DCR	(1 << 1)/* use SDMA Ctrl via DCR */
+#endif
 
 /* Boards with PCI network controllers can call this from their board_eth_init()
  * function to initialize whatever's on board.

1.7.0.4

U-Boot's multipple network supports enables to use several ethernet drivers but microblaze-generic platform config file select only one driver.

---
 include/configs/microblaze-generic.h |   11 ++++++-----
 1 files changed, 6 insertions(+), 5 deletions(-)

index 9f66fbf..efca136 100644
@@ -65,11 +65,12 @@
 
 /* ethernet */
 #undef CONFIG_SYS_ENET
-#ifdef XILINX_EMACLITE_BASEADDR
-# define CONFIG_XILINX_EMACLITE		1
+#if defined(XILINX_EMACLITE_BASEADDR)
+# define CONFIG_XILINX_EMACLITE	1
 # define CONFIG_SYS_ENET
-#elif XILINX_LLTEMAC_BASEADDR
-# define CONFIG_XILINX_LL_TEMAC		1
+#endif
+#if defined(XILINX_LLTEMAC_BASEADDR)
+# define CONFIG_XILINX_LL_TEMAC	1
 # define CONFIG_SYS_ENET
 #endif
 #if defined(XILINX_AXIEMAC_BASEADDR)

@@ -339,7 +340,7 @@
 #define CONFIG_FIT		1
 #define CONFIG_OF_LIBFDT	1
 
-#if defined(CONFIG_XILINX_AXIEMAC)
+#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
 # define CONFIG_MII		1
 # define CONFIG_CMD_MII		1
 # define CONFIG_PHY_GIGE	1

1.7.0.4

Note: this patch depends on commit "microblaze: Enable phylib and mii support" (http://patchwork.ozlabs.org/patch/142957/)

br-
Stephan

Am Samstag, den 25.02.2012, 11:48 +0100 schrieb Stephan Linz:

Viele Gr??e,
Stephan Linz
______________________________________________________________________________
MB-Ref: http://www.li-pro.de/xilinx_mb:mbref:start
OpenDCC: http://www.li-pro.net/opendcc.phtml
PC/M: http://www.li-pro.net/pcm.phtml
Sourceforge: http://sourceforge.net/users/slz
Gitorious: https://gitorious.org/~slz

Hi Stephan,

Applied.

Thanks,
-Joe

Expand the specific configuration for the microblaze-generic board in xparameters.h with a faked setup to enable the LL_TEMAC driver.

Note: From now the microblaze-generic board is no longer a valid board configuration for a real piece of hardware. Rather than, we use the file config.mk and xparameters.h as a faked board configuration to force the compilation of all potential driver code for Microblaze systems.

---
 board/xilinx/microblaze-generic/config.mk     |    6 ++++--
 board/xilinx/microblaze-generic/xparameters.h |   12 ++++++++++--
 2 files changed, 14 insertions(+), 4 deletions(-)

index f8d7e26..9fd1015 100644
@@ -21,8 +21,10 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-# CAUTION: This file is automatically generated by libgen.
-# Version: Xilinx EDK 6.3 EDK_Gmm.12.3
+# CAUTION: This file is a faked configuration !!!
+#          There is no real target for the microblaze-generic
+#          configuration. You have to replace this file with
+#          the generated file from your Xilinx design flow.
 #
 
 CONFIG_SYS_TEXT_BASE = 0x29000000

index fae03bf..50a82d9 100644
@@ -21,8 +21,10 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  *
- * CAUTION: This file is automatically generated by libgen.
- * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
+ * CAUTION: This file is a faked configuration !!!
+ *          There is no real target for the microblaze-generic
+ *          configuration. You have to replace this file with
+ *          the generated file from your Xilinx design flow.
  */
 
 #define XILINX_BOARD_NAME	microblaze-generic

@@ -69,3 +71,9 @@
 
 /* Ethernet controller is Ethernet_MAC */
 #define XILINX_EMACLITE_BASEADDR       0x40C00000
+
+/* LL_TEMAC Ethernet controller */
+#define XILINX_LLTEMAC_BASEADDR			0x44000000
+#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR	0x42000180
+#define XILINX_LLTEMAC_BASEADDR1		0x44200000
+#define XILINX_LLTEMAC_FIFO_BASEADDR1		0x42100000

1.7.0.4

Hi Stephan,

Applied.

Thanks,
-Joe

Initialize ll_temac driver.

---
 .../xilinx/microblaze-generic/microblaze-generic.c |   36 ++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)

index c4c13a6..a1e2bfe 100644
@@ -90,5 +90,41 @@ int board_eth_init(bd_t *bis)
 	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
 			txpp, rxpp);
 #endif
+
+#ifdef CONFIG_XILINX_LL_TEMAC
+# ifdef XILINX_LLTEMAC_BASEADDR
+#  ifdef XILINX_LLTEMAC_FIFO_BASEADDR
+	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
+			XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR);
+#  elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
+#   if XILINX_LLTEMAC_SDMA_USE_DCR == 1
+	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
+			XILINX_LL_TEMAC_M_SDMA_DCR,
+			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
+#   else
+	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
+			XILINX_LL_TEMAC_M_SDMA_PLB,
+			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
+#   endif
+#  endif
+# endif
+# ifdef XILINX_LLTEMAC_BASEADDR1
+#  ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
+	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
+			XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1);
+#  elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
+#   if XILINX_LLTEMAC_SDMA_USE_DCR == 1
+	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
+			XILINX_LL_TEMAC_M_SDMA_DCR,
+			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
+#   else
+	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
+			XILINX_LL_TEMAC_M_SDMA_PLB,
+			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
+#   endif
+#  endif
+# endif
+#endif
+
 	return ret;
 }

1.7.0.4

Hi Stephan,

Applied.

Thanks,
-Joe

Dear Stephan,

Please do not use my Reported-by: line. It is new patch not any bug which needs to be fixed. Patches are based on my origin version that's why it is fine to be just in copyright.

Joe, Wolfgang: I don't agree with this driver because it is doing the same things as my origin version but on 800 lines instead of 1860lines. The next thing is that plb bus on Xilinx fpgas is getting obsolete.

I am not going to add it to my microblaze custodian tree.
If you like this patch please add it to u-boot-net tree or directly to mainline. In that case you have my ACK for microblaze patches 2-4/4 and please apply them too.

I have applied one patch to my custodian master branch which is required by this patchset (also fix another problem with axi emac). I have also asked Wolfgang for merging this when possible.

Thanks,
Michal

Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

Hi Michal,

Are you meaning that you already have a driver in u-boot that works on this hardware or do you mean the original version somewhere else, like Linux?

As for plb being near obsolescence, are you recommending a change to the driver to drop support for that bus option? Or do you mean for that reason the driver itself should be omitted?

I was actually going to recommend that it go through the microblaze branch if it is primarily for microblaze targets. If you don't want it, then I think Stephan needs to work to convince you by making revisions.

Thanks,
-Joe

Hi Joe,

There is really long history about this u-boot driver. The origin version for ppc was sent to mailing list April 26, 2008 by Yoshio Kashiwagi. I have tried to add it to mainline several times
and my latest attempts end with result that I didn't want to follow u-boot coding style because
of ppc/microblaze differences (not using offset with structure because of ppc/microblaze differences - dcr/plb access). That driver has 800 lines.
Based on this strict rule I decided not to continue to push this driver to mainline
because it is just a lot of work to change it and especially test it. My origin driver is used by many our customers on microblaze and ppc and none reported any problem with it.

After this Stephan decided to change it to be acceptable to mainline submission.

should be obsolete in a year or so and if you add it to mainline it will be there but in 2013 there will be minimal number of users for it.

None can convince me that 1860 code lines which fulfill all u-boot rules is better than origin well tested 800 code lines (and commercially used) which break one u-boot rule.
I agree with rules but none can expect that I will assist and help to add it to mainline. I don't want to have responsibility for that.

BTW: Target is also ppc because there is DCR support.

Thanks,
Michal

Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

Hello Joe and Michal,

Am Mittwoch, den 28.03.2012, 09:53 +0200 schrieb Michal Simek:

No, there is no u-boot custodian tree with an already merged driver.

Yes, I've reworked the driver since November 2011 and now, in contrast to the "800 lines" driver submitted by Michal, the new driver has more features than the differnet memory access methods for ppc/microblaze:

- eliminates all private data exchange buffer
- supports the NetBuf handling for FIFO and DMA mode
- supports the new MII bus framework
- supports potentially more than just the two memory access methods
- includes a complete register description (structs and defines)
- split into differnet parts for better overview and readability

No! It may be that PLB will no longer be interesting for new designs. But there are many existing FPGA solutions which will use the latest software releases on it.

Moreover, this also aplied to the PowerPC at FPGA world (DCR part).

I like it ;) but unfortunately I have no custodian tree :(

Why not? The currently submitted driver has changes undergone a long review process by different submitters and maintainers of U-Boot. This driver is ready for future use (ex. the new MII bus and PHY device abstraction, fully qualified register description for further extensions if needed).

If the DCR support is a problem, I can split the patches and separate the DCR support. Currently the DCR related code is about 80 LOCs and already enclosed by CONFIG_XILINX_440 and CONFIG_XILINX_405.

br,
Stephan

Hi Stephan,

Applied.

Thanks,
-Joe