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perf, intel: Expose SMI_COUNT as a fixed counter

RFC PATCH In review Peter Zijlstra 1 participant 2 messages Sep 12, 2012 – Sep 14, 2012

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Peter Zijlstra

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RFC PATCH 1/1 perf, intel: Expose SMI_COUNT as a fixed counter

Subject: perf, intel: Expose SMI_COUNT as a fixed counter
From: Peter Zijlstra <[email protected]>
Date: Wed Sep 12 13:10:53 CEST 2012

The Intel SMI_COUNT sadly isn't a proper PMU event but a free-running MSR, expose it by creating another fake fixed PMC and another pseudo event.

Signed-off-by Peter Zijlstra <[email protected]>

---

Only added to wsm because that's what my testbox is ;-)

 arch/x86/include/asm/perf_event.h      |   18 ++++++++
 arch/x86/kernel/cpu/perf_event.c       |   68 +++++++++++++++++++++++++--------
 arch/x86/kernel/cpu/perf_event.h       |    9 ++++
 arch/x86/kernel/cpu/perf_event_intel.c |   42 ++++++++++++++------
 4 files changed, 109 insertions(+), 28 deletions(-)
arch/x86/include/asm/perf_event.h +17 -1
@@ -131,13 +131,29 @@ struct x86_pmu_capability {
 #define INTEL_PMC_MSK_FIXED_REF_CYCLES	(1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
 
 /*
+ * Create a range of 'special' (fake) fixed purpose counters
+ */
+#define INTEL_PMC_IDX_FIXED_SPECIAL	(INTEL_PMC_IDX_FIXED + 16)
+#define INTEL_PMC_MSK_FIXED_SPECIAL	(1ULL << INTEL_PMC_IDX_FIXED_SPECIAL)
+
+/*
  * We model BTS tracing as another fixed-mode PMC.
  *
  * We choose a value in the middle of the fixed event range, since lower
  * values are used by actual fixed events and higher values are used
  * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
  */
-#define INTEL_PMC_IDX_FIXED_BTS				(INTEL_PMC_IDX_FIXED + 16)
+#define INTEL_PMC_IDX_FIXED_BTS		(INTEL_PMC_IDX_FIXED_SPECIAL + 0)
+#define INTEL_PMC_MSK_FIXED_BTS		(1ULL << INTEL_PMC_IDX_FIXED_BTS)
+
+/*
+ * We model the SMI_COUNT as another fixed-mode PMC.
+ *
+ * This MSR (34h) is a free running counter of SMIs
+ */
+#define MSR_ARCH_SMI_COUNT		0x34
+#define INTEL_PMC_IDX_FIXED_SMI_COUNT	(INTEL_PMC_IDX_FIXED_SPECIAL + 1)
+#define INTEL_PMC_MSK_FIXED_SMI_COUNT	(1ULL << INTEL_PMC_IDX_FIXED_SMI_COUNT)
 
 /*
  * IBS cpuid feature detection
arch/x86/kernel/cpu/perf_event.c +53 -15

112 lines not on this page · raw message

arch/x86/kernel/cpu/perf_event.h +9 -0
@@ -536,6 +536,15 @@ static inline void set_linear_ip(struct 
 	regs->ip = ip;
 }
 
+static inline u64 x86_rdsmi(struct hw_perf_event *hwc)
+{
+	u64 count;
+
+	rdmsrl(MSR_ARCH_SMI_COUNT, count);
+
+	return count;
+}
+
 #ifdef CONFIG_CPU_SUP_AMD
 
 int amd_pmu_init(void);
arch/x86/kernel/cpu/perf_event_intel.c +30 -12

71 lines not on this page · raw message

author maintainer
#1 lore raw
Quoted 7 lines · Peter Zijlstra

Subject: perf, intel: Expose SMI_COUNT as a fixed counter
From: Peter Zijlstra <[email protected]>
Date: Wed Sep 12 13:10:53 CEST 2012

The Intel SMI_COUNT sadly isn't a proper PMU event but a free-running MSR, expose it by creating another fake fixed PMC and another pseudo event.

OK, so it looks like this MSR has the same content on all CPUs.. is this inherent to SMIs or is that just my box being funny?