mtd/st_smi: Clear error flags while initiating a fresh write

index 7507e5d..fad4420 100644
@@ -392,6 +392,8 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
 		return -1;
 	}
 
+	writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);
+
 	if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
 		return -EBUSY;
 

index fad4420..e2d1cf9 100644
@@ -75,6 +75,7 @@ static struct flash_device flash_devices[] = {
 	FLASH_ID("st m45pe20"    , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
 	FLASH_ID("st m45pe40"    , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
 	FLASH_ID("st m45pe80"    , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
+	FLASH_ID("mcr n25q128"   , 0xd8, 0x0018BA20, 0x100, 0x10000, 0x1000000),
 	FLASH_ID("sp s25fl004"   , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
 	FLASH_ID("sp s25fl008"   , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
 	FLASH_ID("sp s25fl016"   , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),

index e2d1cf9..1b9ff0e 100644
@@ -374,7 +374,7 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
 	u8 *src_addr8 = (u8 *)src_addr;
 	u8 *dst_addr8 = (u8 *)dst_addr;
 	int banknum;
-	int i;
+	int i, issue_we;
 
 	switch (bank_addr) {
 	case SMIBANK0_BASE:

@@ -394,19 +394,16 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
 	}
 
 	writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);
-
-	if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
-		return -EBUSY;
+	issue_we = 1;
 
 	/* Set SMI in Hardware Mode */
 	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
 
-	if (smi_write_enable(banknum))
-		return -EIO;
-
 	/* Perform the write command */
 	for (i = 0; i < length; i += 4) {
-		if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) {
+		if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
+			issue_we = 0;
+
 			if (smi_wait_till_ready(banknum,
 						CONFIG_SYS_FLASH_WRITE_TOUT))
 				return -EBUSY;

index 1b9ff0e..5298723 100644
@@ -368,13 +368,11 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector)
  *
  * Write to SMI flash
  */
-static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
+static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
 		     unsigned int length, ulong bank_addr)
 {
-	u8 *src_addr8 = (u8 *)src_addr;
-	u8 *dst_addr8 = (u8 *)dst_addr;
 	int banknum;
-	int i, issue_we;
+	int issue_we;
 
 	switch (bank_addr) {
 	case SMIBANK0_BASE:

@@ -400,7 +398,10 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
 	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
 
 	/* Perform the write command */
-	for (i = 0; i < length; i += 4) {
+	while (length) {
+		int k;
+		unsigned int wlen = min(SFLASH_PAGE_SIZE, length);
+
 		if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
 			issue_we = 0;
 

@@ -412,19 +413,14 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
 				return -EIO;
 		}
 
-		if (length < 4) {
-			int k;
+		writel(readl(&smicntl->smi_cr1) | WB_MODE, &smicntl->smi_cr1);
 
-			/*
-			 * Handle special case, where length < 4 (redundant env)
-			 */
-			for (k = 0; k < length; k++)
-				*dst_addr8++ = *src_addr8++;
-		} else {
-			/* Normal 32bit write */
+		for (k = 0; k < wlen; k++)
 			*dst_addr++ = *src_addr++;
-		}
 
+		writel(readl(&smicntl->smi_cr1) & ~WB_MODE, &smicntl->smi_cr1);
+
+		length -= wlen;
 		if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2)))
 			return -EIO;
 	}

@@ -448,8 +444,8 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
  */
 int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
 {
-	return smi_write((unsigned int *)src, (unsigned int *)dest_addr,
-			 length, info->start[0]);
+	return smi_write(src, (unsigned char *)dest_addr, length,
+			info->start[0]);
 }
 
 /*

index 5298723..ac10a3d 100644
@@ -96,6 +96,25 @@ static struct flash_device flash_devices[] = {
 };
 
 /*
+ * get_flash_device - Return flash_device pointer for a particular device id
+ * @id:	 Device id
+ *
+ * Return flash_device pointer for a particular device id
+ */
+static struct flash_device *get_flash_device(u32 id)
+{
+	struct flash_device *flash_dev_p = &flash_devices[0];
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(flash_devices); i++, flash_dev_p++) {
+		if (flash_dev_p->device_id == id)
+			return flash_dev_p;
+	}
+
+	return NULL;
+}
+
+/*
  * smi_wait_xfer_finish - Wait until TFF is set in status register
  * @timeout:	 timeout in milliseconds
  *

@@ -361,20 +380,27 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector)
 
 /*
  * smi_write - Write to SMI flash
+ * @info:	 flash info structure
  * @src_addr:	 source buffer
  * @dst_addr:	 destination buffer
  * @length:	 length to write in bytes
- * @bank:	 bank base address
  *
  * Write to SMI flash
  */
-static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
-		     unsigned int length, ulong bank_addr)
+static int smi_write(flash_info_t *info, unsigned char *src_addr,
+		unsigned char *dst_addr, unsigned int length)
 {
+	struct flash_device *flash_device_p = get_flash_device(info->flash_id);
+	u32 page_size;
 	int banknum;
 	int issue_we;
 
-	switch (bank_addr) {
+	if (!flash_device_p)
+		return -EIO;
+
+	page_size = flash_device_p->pagesize;
+
+	switch (info->start[0]) {
 	case SMIBANK0_BASE:
 		banknum = BANK0;
 		break;

@@ -400,9 +426,9 @@ static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
 	/* Perform the write command */
 	while (length) {
 		int k;
-		unsigned int wlen = min(SFLASH_PAGE_SIZE, length);
+		unsigned int wlen = min(page_size, length);
 
-		if (issue_we || (((ulong)(dst_addr) % SFLASH_PAGE_SIZE) == 0)) {
+		if (issue_we || (((ulong)(dst_addr) % page_size) == 0)) {
 			issue_we = 0;
 
 			if (smi_wait_till_ready(banknum,

@@ -444,8 +470,7 @@ static int smi_write(unsigned char *src_addr, unsigned char *dst_addr,
  */
 int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
 {
-	return smi_write(src, (unsigned char *)dest_addr, length,
-			info->start[0]);
+	return smi_write(info, src, (unsigned char *)dest_addr, length);
 }
 
 /*

index 04f81ea..5837493 100644
@@ -108,7 +108,6 @@ struct flash_dev {
 	ushort sector_count;
 };
 
-#define SFLASH_PAGE_SIZE	0x100	/* flash page size */
 #define XFER_FINISH_TOUT	15	/* xfer finish timeout(in ms) */
 #define WMODE_TOUT		15	/* write enable timeout(in ms) */
 

index e4a1201..24de9b7 100644
@@ -393,17 +393,34 @@ static int usb_hub_configure(struct usb_device *dev)
 		"" : "no ");
 	usb_hub_power_on(hub);
 
+	mdelay(1500);
+
 	for (i = 0; i < dev->maxchild; i++) {
 		ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
 		unsigned short portstatus, portchange;
+		int ret;
+		ulong start = get_timer(0);
+
+		do {
+			ret = usb_get_port_status(dev, i + 1, portsts);
+			if (ret < 0) {
+				USB_HUB_PRINTF("get_port_status failed\n");
+				break;
+			}
+
+			portstatus = le16_to_cpu(portsts->wPortStatus);
+			portchange = le16_to_cpu(portsts->wPortChange);
+
+			if ((portchange & USB_PORT_STAT_C_CONNECTION) &&
+				(portstatus & USB_PORT_STAT_CONNECTION))
+				break;
 
-		if (usb_get_port_status(dev, i + 1, portsts) < 0) {
-			USB_HUB_PRINTF("get_port_status failed\n");
+			mdelay(100);
+		} while (get_timer(start) < CONFIG_SYS_HZ * 10);
+
+		if (ret < 0)
 			continue;
-		}
 
-		portstatus = le16_to_cpu(portsts->wPortStatus);
-		portchange = le16_to_cpu(portsts->wPortChange);
 		USB_HUB_PRINTF("Port %d Status %X Change %X\n",
 				i + 1, portstatus, portchange);
 

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index bf21a08..46f6601 100644
@@ -113,7 +113,9 @@ static int mac_reset(struct eth_device *dev)
 	int timeout = CONFIG_MACRESET_TIMEOUT;
 
 	writel(DMAMAC_SRST, &dma_p->busmode);
-	writel(MII_PORTSELECT, &mac_p->conf);
+
+	if (priv->interface != PHY_INTERFACE_MODE_RGMII)
+		writel(MII_PORTSELECT, &mac_p->conf);
 
 	start = get_timer(0);
 	while (get_timer(start) < timeout) {

index eb670da..bd3bcbc 100644
@@ -35,6 +35,8 @@
 #include <usb/pxa27x_udc.h>
 #elif defined(CONFIG_DW_UDC)
 #include <usb/designware_udc.h>
+#elif defined(CONFIG_DW_OTG)
+#include <usb/designware_otg.h>
 #endif
 
 #include <version.h>

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index e47cb9a..148d1a6 100644
@@ -63,7 +63,7 @@
 /*
  * Buffers to hold input and output data
  */
-#define USBTTY_BUFFER_SIZE 256
+#define USBTTY_BUFFER_SIZE 2048
 static circbuf_t usbtty_input;
 static circbuf_t usbtty_output;
 

index 3edaf8b..7037efd 100644
@@ -475,7 +475,9 @@ typedef struct urb_link {
  * function driver to inform it that data has arrived.
  */
 
-#define URB_BUF_SIZE 128 /* in linux we'd malloc this, but in u-boot we prefer static data */
+/* in linux we'd malloc this, but in u-boot we prefer static data */
+#define URB_BUF_SIZE 512
+
 struct urb {
 
 	struct usb_endpoint_instance *endpoint;

index 0e1ced7..ac25b52 100644
@@ -165,6 +165,13 @@ static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
 	return MACB_BFEXT(DATA, frame);
 }
 
+static void __def_arch_get_mdio_control(const char *name)
+{
+	return;
+}
+int arch_get_mdio_control(const char *name)
+	__attribute__((weak, alias("__def_arch_get_mdio_control")));
+
 #if defined(CONFIG_CMD_MII)
 
 int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)

@@ -175,6 +182,7 @@ int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
 	if ( macb->phy_addr != phy_adr )
 		return -1;
 
+	arch_get_mdio_control(devname);
 	*value = macb_mdio_read(macb, reg);
 
 	return 0;

@@ -188,6 +196,7 @@ int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
 	if ( macb->phy_addr != phy_adr )
 		return -1;
 
+	arch_get_mdio_control(devname);
 	macb_mdio_write(macb, reg, value);
 
 	return 0;

@@ -379,6 +388,7 @@ static int macb_phy_init(struct macb_device *macb)
 	int media, speed, duplex;
 	int i;
 
+	arch_get_mdio_control(netdev->name);
 #ifdef CONFIG_MACB_SEARCH_PHY
 	/* Auto-detect phy_addr */
 	if (!macb_phy_find(macb)) {

index ac25b52..17bad33 100644
@@ -55,7 +55,7 @@
 
 #define CONFIG_SYS_MACB_RX_BUFFER_SIZE		4096
 #define CONFIG_SYS_MACB_RX_RING_SIZE		(CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
-#define CONFIG_SYS_MACB_TX_RING_SIZE		16
+#define CONFIG_SYS_MACB_TX_RING_SIZE		1
 #define CONFIG_SYS_MACB_TX_TIMEOUT		1000
 #define CONFIG_SYS_MACB_AUTONEG_TIMEOUT	5000000
 

@@ -226,7 +226,13 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
 	macb->tx_ring[tx_head].ctrl = ctrl;
 	macb->tx_ring[tx_head].addr = paddr;
 	barrier();
-	macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
+	/*
+	 * Due to issues on SPEAr320 RMII, disable TE first so that
+	 * controller can come out if it is hanged during transmission
+	 */
+	macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE));
+	macb_writel(macb, NCR, macb_readl(macb, NCR) |
+			MACB_BIT(TE) | MACB_BIT(TSTART));
 
 	/*
 	 * I guess this is necessary because the networking core may

@@ -444,6 +450,31 @@ static int macb_phy_init(struct macb_device *macb)
 	}
 }
 
+static void macb_reset_hw(struct macb_device *bp)
+{
+	/* Make sure we have the write buffer for ourselves */
+	barrier();
+	/*
+	 * Disable RX and TX (XXX: Should we halt the transmission
+	 * more gracefully?) and we should not close the mdio port
+	 */
+	macb_writel(bp, NCR, 0);
+
+	/* Clear the stats registers (XXX: Update stats first?) */
+	macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
+
+	/* keep the mdio port , otherwise other eth will not work */
+	macb_writel(bp, NCR, MACB_BIT(MPE));
+
+	/* Clear all status flags */
+	macb_writel(bp, TSR, ~0UL);
+	macb_writel(bp, RSR, ~0UL);
+
+	/* Disable all interrupts */
+	macb_writel(bp, IDR, ~0UL);
+	macb_readl(bp, ISR);
+}
+
 static int macb_init(struct eth_device *netdev, bd_t *bd)
 {
 	struct macb_device *macb = to_macb(netdev);

@@ -520,8 +551,7 @@ static void macb_halt(struct eth_device *netdev)
 		tsr = macb_readl(macb, TSR);
 	} while (tsr & MACB_BIT(TGO));
 
-	/* Disable TX and RX, and clear statistics */
-	macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
+	macb_reset_hw(macb);
 }
 
 static int macb_write_hwaddr(struct eth_device *dev)

new file mode 100644
index 0000000..541d702
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2012
+ * ST Micoelectronics Pvt. Ltd.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MISC_C3_
+#define _MISC_C3_
+
+#include <asm/arch/hardware.h>
+
+#define C3_HIF_OFF		0x400	/* master interface registers */
+
+#define C3_INT_MEM_BASE_ADDR		(CONFIG_SYS_C3_BASE + 0x400)
+#define C3_HIF_MBAR			(C3_INT_MEM_BASE_ADDR + 0x304)
+	#define C3_LOCAL_MEM_ADDR		0xF0000000
+#define C3_HIF_MCR			(C3_INT_MEM_BASE_ADDR + 0x308)
+	#define C3_HIF_MCR_ENB_INT_MEM		0x01
+#define C3_HIF_MAAR			(C3_INT_MEM_BASE_ADDR + 0x310)
+#define C3_HIF_MADR			(C3_INT_MEM_BASE_ADDR + 0x314)
+
+/* ID0 Registers definition */
+#define C3_ID0_SCR			(CONFIG_SYS_C3_BASE + 0x1000)
+	#define C3_ID0_SCR_RST			(1 << 16)
+#define C3_ID0_IP			(CONFIG_SYS_C3_BASE + 0x1000 + 0x10)
+	#define C3_ID0_DEF_RDY_VAL		0x80002AAA
+	#define C3_ID0_STATE_MASK		0xC0000000
+	#define C3_ID0_STATE_RUN		0xC0000000
+	#define C3_ID0_STATE_IDLE		0x80000000
+
+/* C3 Register Offsets */
+#define C3_MOVE_CHANNEL_ID		(CONFIG_SYS_C3_BASE + 0x2000 + 0x3FC)
+	#define C3_MOVE_CHANNEL_ID_VAL		0x00000102
+
+#define C3_INT_MEM_SIZE				0x4000
+#define C3_MOVE_AND				(1 << 21)
+
+/* Some Commands */
+#define C3_CMD_MOVE_INIT			0x06000000
+#define C3_CMD_MOVE_DATA			0x0A800000
+#define C3_CMD_STOP				0x00000000
+
+void *c3_memset(void *s, int c, size_t count);
+int c3_init(void);
+
+#endif

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new file mode 100644
index 0000000..8833853
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, [email protected].
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_ARM_CA9TIMER_H
+#define __ARCH_ARM_CA9TIMER_H
+
+struct ca9_timer_regs {
+	u32 load;
+	u32 count;
+	u32 control;
+};
+
+/* control related definitions */
+#define AUTO_RELOAD		(1 << 1)
+#define TIMER_ENABLE		(1 << 0)
+
+/* load related definitions */
+#define FREE_RUNNING		(0xFFFFFFFF)
+
+#endif

index 83fa5d7..ca3c430 100644
@@ -62,6 +62,11 @@
 #include <linux/lzo.h>
 #endif /* CONFIG_LZO */
 
+#if defined(CONFIG_CMD_NAND)
+#include <linux/err.h>
+#include <nand.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SYS_BOOTM_LEN

@@ -1221,6 +1226,99 @@ next_sector:		;
 next_bank:	;
 	}
 
+#if defined(CONFIG_CMD_NAND)
+	printf("\n");
+	nand_info_t *nand;
+	image_header_t image_header;
+	image_header_t *header = &image_header;
+	int nand_dev = nand_curr_device;
+	unsigned long img_size;
+	size_t hdr_size, read_len;
+	loff_t off;
+	unsigned int crc;
+	u_char *data;
+
+	/* the following commands operate on the current device */
+	if (nand_dev < 0 || nand_dev >= CONFIG_SYS_MAX_NAND_DEVICE) {
+		puts("\nNo NAND devices available\n");
+		return 0;
+	}
+
+	for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
+
+		nand = &nand_info[nand_dev];
+		if ((!nand->name) || (!nand->size))
+			continue;
+
+		data = malloc(nand->writesize);
+		if (!data) {
+			puts("No memory available to list NAND images\n");
+			return 0;
+		}
+
+		for (off = 0; off < nand->size; off += nand->erasesize) {
+			int ret;
+
+			if (nand_block_isbad(nand, off))
+				continue;
+
+			hdr_size = sizeof(image_header_t);
+			ret = nand_read(nand, off, &hdr_size, (u_char *)header);
+			if (ret < 0 && ret != -EUCLEAN)
+				continue;
+
+			if (!image_check_hcrc(header))
+				continue;
+
+			printf("Legacy Image@NAND device %d offset %08lX:\n",
+					nand_dev, (ulong)off);
+			image_print_contents(header);
+
+			puts("   Verifying Checksum ... ");
+			crc = 0;
+			img_size = ntohl(header->ih_size);
+			img_size += hdr_size;
+
+			while (img_size > 0) {
+				int blockoff = 0;
+
+				while (nand_block_isbad(nand, off)) {
+					off += nand->erasesize;
+					if (off >= nand->size)
+						goto out;
+				}
+
+				do {
+					read_len = min(img_size,
+							nand->writesize);
+					ret = nand_read(nand, off + blockoff,
+							&read_len, data);
+					if (ret < 0 && ret != -EUCLEAN)
+						break;
+
+					crc = crc32(crc, data + hdr_size,
+							read_len - hdr_size);
+					img_size -= read_len;
+					blockoff += read_len;
+					hdr_size = 0;
+				} while (img_size &&
+						(blockoff < nand->erasesize));
+
+				off += nand->erasesize;
+				if (off >= nand->size)
+					goto out;
+			}
+			off -= nand->erasesize;
+out:
+			if (crc != ntohl(header->ih_dcrc))
+				puts("   Bad Data CRC\n");
+			else
+				puts("OK\n");
+		}
+		free(data);
+	}
+
+#endif
 	return (0);
 }
 

index 92cad9a..fa161b8 100644
@@ -399,6 +399,11 @@ void board_init_f(ulong bootflag)
 	gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
 #endif
 
+#ifdef CONFIG_BOOT_PARAMS_P
+	/* Boot params passed to Linux */
+	gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_P;
+#endif
+
 	addr_sp -= sizeof (gd_t);
 	id = (gd_t *) addr_sp;
 	debug("Reserving %zu Bytes for Global Data at: %08lx\n",

@@ -468,6 +473,13 @@ void board_init_f(ulong bootflag)
 static char *failed = "*** failed ***\n";
 #endif
 
+static int __def_board_init(bd_t *bis)
+{
+	return -1;
+}
+
+int board_init(void) __attribute__((weak, alias("__def_board_init")));
+
 /*
  ************************************************************************
  *

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new file mode 100644
index 0000000..351e8cd
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+#endif
+}

new file mode 100644
index 0000000..7beb1c2
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_ARM_GENERIC_H__
+#define __ARCH_ARM_GENERIC_H__
+
+#if defined(CONFIG_SOC_SPEAR1310)
+extern void spear1310_usbh_stop(void);
+#elif defined(CONFIG_SOC_SPEAR1340)
+extern void spear1340_usbh_stop(void);
+#endif
+
+#endif

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new file mode 100644
index 0000000..b49ef67
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#if defined(CONFIG_SOC_SPEAR1340)
+#include <asm/arch/spear1340.h>
+#endif
+
+#endif /* _ASM_ARCH_HARDWARE_H */

new file mode 100644
index 0000000..5134938
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_MISC_H
+#define _ASM_ARCH_MISC_H
+
+#ifdef CONFIG_SOC_SPEAR1340
+#include <asm/arch/spear1340_misc.h>
+#endif
+
+#endif

new file mode 100644
index 0000000..5c01a7e
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_MMC_H
+#define _ASM_ARCH_MMC_H
+
+extern int spear_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+
+#endif

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index 71c4ea2..7a57379 100644
@@ -59,6 +59,8 @@ int ehci_hcd_stop(int index)
 	spear3xx_usbh_stop();
 #elif defined(CONFIG_ARCH_SPEAR6XX)
 	spear6xx_usbh_stop();
+#elif defined(CONFIG_SOC_SPEAR1340)
+	spear1340_usbh_stop();
 #else
 #error No spear platforms defined
 #endif

index e724310..984022c 100644
@@ -115,6 +115,10 @@ static inline unsigned int generic_hweight8(unsigned int w)
 # define __set_bit generic_set_bit
 #endif
 
+#ifndef PLATFORM__TEST_BIT
+# define __test_bit generic_test_bit
+#endif
+
 #ifndef PLATFORM__CLEAR_BIT
 # define __clear_bit generic_clear_bit
 #endif

@@ -144,6 +148,14 @@ static inline void generic_set_bit(int nr, volatile unsigned long *addr)
 	*p  |= mask;
 }
 
+static inline int generic_test_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	return !!(*p & mask);
+}
+
 static inline void generic_clear_bit(int nr, volatile unsigned long *addr)
 {
 	unsigned long mask = BIT_MASK(nr);

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index b49ef67..616b57d 100644
@@ -26,6 +26,8 @@
 
 #if defined(CONFIG_SOC_SPEAR1340)
 #include <asm/arch/spear1340.h>
+#elif defined(CONFIG_SOC_SPEAR1310)
+#include <asm/arch/spear1310.h>
 #endif
 
 #endif /* _ASM_ARCH_HARDWARE_H */

index 5134938..531862a 100644
@@ -26,6 +26,9 @@
 
 #ifdef CONFIG_SOC_SPEAR1340
 #include <asm/arch/spear1340_misc.h>
+
+#elif defined(CONFIG_SOC_SPEAR1310)
+#include <asm/arch/spear1310_misc.h>
 #endif
 
 #endif

index 9354f21..01531f1 100644
@@ -72,17 +72,22 @@ enum pinmux_ip {
 	PMX_SDMMC,
 	PMX_EMI,
 	PMX_SMI,
+	PMX_LEGGPIO0,
+	PMX_LEGGPIO1,
 };
 
 /* UART0 modem modes */
 #define PMX_UART_SIMPLE		1
 #define PMX_UART_MODEM		2
+#define PMX_UART_DISSD		3
+#define PMX_UART_DISI2C0	4
 
 /* SSP modes */
 #define PMX_SSP_CS0		1
 #define PMX_SSP_CS1		2
 #define PMX_SSP_CS2		3
 #define PMX_SSP_CS3		4
+#define PMX_SSP_CS1_CS2		5
 
 /* ETH modes */
 #define PMX_ETH_GMII		1

@@ -95,6 +100,11 @@ enum pinmux_ip {
 /* NAND modes */
 #define PMX_NAND_8BIT		1
 #define PMX_NAND_16BIT		2
+#define PMX_NAND_4CHIPS		3
+
+/* SMI modes */
+#define PMX_SMI_2CHIPS		1
+#define PMX_SMI_4CHIPS		2
 
 /* PLGPIO modes */
 #define PMX_GPIO		1

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index 7a57379..61d30f8 100644
@@ -59,6 +59,8 @@ int ehci_hcd_stop(int index)
 	spear3xx_usbh_stop();
 #elif defined(CONFIG_ARCH_SPEAR6XX)
 	spear6xx_usbh_stop();
+#elif defined(CONFIG_SOC_SPEAR1310)
+	spear1310_usbh_stop();
 #elif defined(CONFIG_SOC_SPEAR1340)
 	spear1340_usbh_stop();
 #else

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new file mode 100644
index 0000000..8cf3d1a
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_SPEAR1340_H
+#define __CONFIG_SPEAR1340_H
+
+#define CONFIG_SOC_SPEAR1340
+
+#include <configs/spear13xx.h>
+#endif /* __CONFIG_SPEAR1340_H */

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index b14e3fb..d996c34 100644
@@ -34,6 +34,8 @@ int checkboard(void)
 {
 #ifdef CONFIG_MACH_SPEAR1340EVB
 	printf("BOARD: SPEAr1340-EVB\n");
+#elif defined(CONFIG_MACH_SPEAR1310EVB)
+	printf("BOARD: SPEAr1310-EVB\n");
 #else
 #error BOARD not supported
 #endif

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new file mode 100644
index 0000000..ad348f7
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, STMicroelectronics, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_SPEAR1310_H
+#define __CONFIG_SPEAR1310_H
+
+#define CONFIG_SOC_SPEAR1310
+
+#if defined(CONFIG_DDR_ECC_ENABLE)
+	#define CONFIG_C3
+	#define CONFIG_SPL_MISC_SUPPORT
+#endif
+
+#include <configs/spear13xx.h>
+#endif /* __CONFIG_SPEAR1310_H */

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index d996c34..7da6333 100644
@@ -36,6 +36,8 @@ int checkboard(void)
 	printf("BOARD: SPEAr1340-EVB\n");
 #elif defined(CONFIG_MACH_SPEAR1310EVB)
 	printf("BOARD: SPEAr1310-EVB\n");
+#elif defined(CONFIG_MACH_SPEAR1340LCAD)
+	printf("BOARD: SPEAr1340-LCAD\n");
 #else
 #error BOARD not supported
 #endif

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index 351e8cd..13e5422 100644
@@ -30,3 +30,33 @@ void enable_caches(void)
 	dcache_enable();
 #endif
 }
+
+#ifdef CONFIG_POST
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	/*
+	 * Run the POST test on 64 MB memory starting from CONFIG_SYS_LOAD_ADDR
+	 * The assumption here is that the DDR present on board is >= 128MB.
+	 *
+	 * The test runs before relocation (after the code copy has taken
+	 * place), so it can not touch either before or after relocation areas
+	 * of U-boot
+	 *
+	 * DDR usage
+	 * <--------->|<---------------- / --------------->|<---------->
+	 *   U-boot		Area to be used for		U-boot
+	 *   before		POST test			after
+	 *   relocation						relocation
+	 */
+
+	*vstart = CONFIG_SYS_LOAD_ADDR;
+	*size = 64 << 20;
+
+	return 0;
+}
+
+void arch_memory_failure_handle(void)
+{
+	hang();
+}
+#endif

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index 7beb1c2..eb066d4 100644
@@ -30,4 +30,12 @@ extern void spear1310_usbh_stop(void);
 extern void spear1340_usbh_stop(void);
 #endif
 
+#if defined(CONFIG_SPL_BUILD)
+extern void cpu2_wake(void);
+extern void soc_init(void);
+extern void board_pre_ddrinit(void);
+extern void ddr_init(void);
+extern void board_post_ddrinit(void);
+#endif
+
 #endif

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index a4fca51..916175b 100644
@@ -26,6 +26,10 @@
 
 #define CONFIG_SPEAR_CORTEXBASE		0xEC800000
 #define CONFIG_ARMV7_LTIMER_BASE	(CONFIG_SPEAR_CORTEXBASE + 0x600)
+#define CONFIG_SYS_L2CACHE_BASE		0xED000000
+
+#define CONFIG_SYS_MPMC_BASE		0xEC000000
+#define CONFIG_SPEAR_MPMCREGS		208
 
 #define CONFIG_SYS_C3_BASE		0xE1800000
 #define CONFIG_SYS_USBD_BASE		0xE3800000

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index 05ae8fb..a5335a3 100644

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index 6c21cf4..b36c644 100644
@@ -81,6 +81,11 @@
 #define CONFIG_NAND_FSMC
 #define CONFIG_SYS_FSMC_NAND_8BIT
 
+/* SPL support */
+#define CONFIG_SPL
+#define CONFIG_DDR_MT41J256M8
+#define CONFIG_SPEAR_DDRFREQ533
+
 /* Environment Variable configs */
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 	/* Environment is in serial NOR flash */

new file mode 100644
index 0000000..351e8cd
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+#endif
+}

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index 24faaea..4bfa619 100644
@@ -30,4 +30,31 @@
 #define CONFIG_SYS_NAND_CLE			(1 << 16)
 #define CONFIG_SYS_NAND_ALE			(1 << 17)
 
+/* RAS misc registers and respective bitmasks */
+#define CONFIG_SYS_RAS_BASE			0x99000000
+#define SPEAR300_RAS_REG1			CONFIG_SYS_RAS_BASE
+	/* Bitmaks for REG1 are in spear3xx.h */
+#define SPEAR300_RAS_REG2			(CONFIG_SYS_RAS_BASE + 0x04)
+	#define SPEAR300_MODE_MSK		(0xF << 0)
+	#define SPEAR300_MODE_NAND		(0x0 << 0)
+	#define SPEAR300_MODE_NOR		(0x1 << 0)
+	#define SPEAR300_MODE_PHOTOFRAME	(0x2 << 0)
+	#define SPEAR300_MODE_LENDIPFONE	(0x3 << 0)
+	#define SPEAR300_MODE_HENDIPFONE	(0x4 << 0)
+	#define SPEAR300_MODE_LENDWIFIFONE	(0x5 << 0)
+	#define SPEAR300_MODE_HENDWIFIFONE	(0x6 << 0)
+	#define SPEAR300_MODE_ATAPABXWI2S	(0x7 << 0)
+	#define SPEAR300_MODE_ATAPABXI2S	(0x8 << 0)
+	#define SPEAR300_MODE_CAM1LCDW		(0xC << 0)
+	#define SPEAR300_MODE_CAMULCD		(0xD << 0)
+	#define SPEAR300_MODE_CAMULCDW		(0xE << 0)
+	#define SPEAR300_MODE_CAM1LCD		(0xF << 0)
+
+#define SPEAR3XX_FUNC_ENB_REG		SPEAR300_RAS_REG1
+
+/* externs related to pinmux */
+extern void spear300_pins_default(void);
+extern void spear300_select_mode(u32 mode);
+extern void spear300_enable_pins(u32 ip, u32 mode);
+
 #endif

index 0f6223e..9d20237 100644
@@ -37,4 +37,17 @@
 #define CONFIG_SYS_MACB3_BASE			0xB1800000
 #define CONFIG_SPEAR_RASBASE			0xB4000000
 
+/* SPEAr310 RAS misc space registers and bitmasks */
+#define SPEAR310_FUNCENB_REG		(CONFIG_SPEAR_RASBASE + 0x8)
+
+#define SPEAR310_SMII_REG		(CONFIG_SPEAR_RASBASE + 0xC)
+	#define SPEAR310_SMII_PHY_SHIFT		0x0
+	#define SPEAR310_SMII_PHY_MASK		0x3
+
+#define SPEAR3XX_FUNC_ENB_REG		SPEAR310_FUNCENB_REG
+
+/* externs related to pinmux */
+extern void spear310_pins_default(void);
+extern void spear310_enable_pins(u32 ip, u32 mode);
+
 #endif

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index e0a72f0..f0df4e6 100644
@@ -37,4 +37,26 @@
 #define CONFIG_SPEAR_SYSCNTLBASE		0xFCA00000
 #define CONFIG_SPEAR_MISCBASE			0xFCA80000
 
+/* spear3xx pinmux register and related bit masks */
+#define PMX_FIRDA_MASK			(1 << 14)
+#define PMX_I2C_MASK			(1 << 13)
+#define PMX_SSP_CS_MASK			(1 << 12)
+#define PMX_SSP_MASK			(1 << 11)
+#define PMX_MII_MASK			(1 << 10)
+#define PMX_GPIO_PIN0_MASK		(1 << 9)
+#define PMX_GPIO_PIN1_MASK		(1 << 8)
+#define PMX_GPIO_PIN2_MASK		(1 << 7)
+#define PMX_GPIO_PIN3_MASK		(1 << 6)
+#define PMX_GPIO_PIN4_MASK		(1 << 5)
+#define PMX_GPIO_PIN5_MASK		(1 << 4)
+#define PMX_UART0_MODEM_MASK		(1 << 3)
+#define PMX_UART0_MASK			(1 << 2)
+#define PMX_TIMER_2_3_MASK		(1 << 1)
+#define PMX_TIMER_0_1_MASK		(1 << 0)
+
+#define SPEAR3XX_MAX_PLGPIOS			101
+
+/* externs related to pinmux */
+extern void spear3xx_enable_pins(u32 ip, u32 mode);
+
 #endif

index 46a5922..2ea598a 100644
@@ -30,11 +30,30 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/generic.h>
 #include <asm/arch/misc.h>
+#include <asm/arch/pinmux.h>
 
 #if defined(CONFIG_CMD_NAND)
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 #endif
 
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+	spear300_select_mode(SPEAR300_MODE_NAND);
+
+	spear300_pins_default();
+	spear3xx_enable_pins(PMX_I2C0, 0);
+	spear3xx_enable_pins(PMX_SSP0, 0);
+	spear3xx_enable_pins(PMX_ETH0, 0);
+	spear3xx_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+
+	spear300_enable_pins(PMX_SDMMC, PMX_SDMMC_4BIT);
+	spear300_enable_pins(PMX_FSMCNAND, PMX_NAND_2CHIP);
+
+	return 0;
+}
+#endif
+
 #if defined(CONFIG_CMD_NAND)
 /*
  * board_nand_init - Board specific NAND initialization

index 4ed8f01..7f70008 100644
@@ -31,11 +31,27 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/generic.h>
 #include <asm/arch/misc.h>
+#include <asm/arch/pinmux.h>
 
 #if defined(CONFIG_CMD_NAND)
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 #endif
 
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+	spear310_pins_default();
+	spear3xx_enable_pins(PMX_I2C0, 0);
+	spear3xx_enable_pins(PMX_SSP0, 0);
+	spear3xx_enable_pins(PMX_ETH0, 0);
+	spear3xx_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+
+	spear310_enable_pins(PMX_ETH1, 0);
+
+	return 0;
+}
+#endif
+
 #if defined(CONFIG_CMD_NAND)
 /*
  * board_nand_init - Board specific NAND initialization

index a463998..84185a5 100644
@@ -31,9 +31,8 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/generic.h>
 #include <asm/arch/misc.h>
-
-#define PLGPIO_SEL_36	0xb3000028
-#define PLGPIO_IO_36	0xb3000038
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
 
 #if defined(CONFIG_CMD_NAND)
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];

@@ -41,15 +40,44 @@ static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 static void spear_phy_reset(void)
 {
-	writel(0x10, PLGPIO_IO_36);
-	writel(0x10, PLGPIO_SEL_36);
+	/* GPIO36 is used to enable oscillator */
+	spear320_configure_pin(36, PMX_GPIO);
+	spear320_plgpio_set(36, 1);
+
+	/* GPIO76 is used to reset phy */
+	spear320_configure_pin(76, PMX_GPIO);
+	spear320_plgpio_set(76, 0);
+	spear320_plgpio_set(76, 1);
 }
 
 int board_init(void)
 {
 	spear_phy_reset();
+
+	return 0;
+}
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+	spear320_select_mode(SPEAR320_EXTENDED_MODE);
+
+	spear320_pins_default();
+
+	spear320_enable_pins(PMX_I2C0, 0);
+	spear320_enable_pins(PMX_ETH0, 0);
+	spear320_enable_pins(PMX_SSP0, 0);
+	spear320_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+	spear320_enable_pins(PMX_ETH2, PMX_ETH_MII);
+	spear320_enable_pins(PMX_SDMMC, PMX_SDMMC_CD51);
+
+	/* GPIO61 is used for card power on */
+	spear320_configure_pin(61, PMX_GPIO);
+	spear320_plgpio_set(61, 0);
+
 	return 0;
 }
+#endif
 
 #if defined(CONFIG_CMD_NAND)
 /*

index 17828a3..add496b 100644
@@ -35,6 +35,13 @@
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 #endif
 
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+	return 0;
+}
+#endif
+
 #if defined(CONFIG_CMD_NAND)
 /*
  * board_nand_init - Board specific NAND initialization