target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs

PATCH Applied Will Auld 4 participants 6 messages Nov 27, 2012 – Feb 6, 2013 KVM

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Will Auld

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2012-11-27 05:32 UTC #0 lore raw

PATCH v5 1/1 target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs

CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported

Basic design is to emulate the MSR by allowing reads and writes to the hypervisor vcpu specific locations to store the value of the emulated MSRs. In this way the IA32_TSC_ADJUST value will be included in all reads to the TSC MSR whether through rdmsr or rdtsc.

As this is a new MSR that the guest may access and modify its value needs to be migrated along with the other MRSs. The changes here are specifically for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added for migrating its value.

Signed-off-by Will Auld <[email protected]>

---
Andreas,

Thanks, that helped. I used Stefan's auto-run method this time.

Will

 target-i386/cpu.h     |  2 ++
 target-i386/kvm.c     | 14 ++++++++++++++
 target-i386/machine.c | 21 +++++++++++++++++++++
 3 files changed, 37 insertions(+)

target-i386/cpu.h +2 -0

index aabf993..45b1bcb 100644
@@ -284,6 +284,7 @@
 #define MSR_IA32_APICBASE_BSP           (1<<8)
 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
+#define MSR_TSC_ADJUST                  0x0000003b
 #define MSR_IA32_TSCDEADLINE            0x6e0
 
 #define MSR_MTRRcap			0xfe

@@ -701,6 +702,7 @@ typedef struct CPUX86State {
     uint64_t async_pf_en_msr;
 
     uint64_t tsc;
+    uint64_t tsc_adjust;
     uint64_t tsc_deadline;
 
     uint64_t mcg_status;

target-i386/kvm.c +14 -0

index 696b14a..e4480c4 100644
@@ -61,6 +61,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
 
 static bool has_msr_star;
 static bool has_msr_hsave_pa;
+static bool has_msr_tsc_adjust;
 static bool has_msr_tsc_deadline;
 static bool has_msr_async_pf_en;
 static bool has_msr_misc_enable;

@@ -641,6 +642,10 @@ static int kvm_get_supported_msrs(KVMState *s)
                     has_msr_hsave_pa = true;
                     continue;
                 }
+                if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
+                    has_msr_tsc_adjust = true;
+                    continue;
+                }
                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
                     has_msr_tsc_deadline = true;
                     continue;

@@ -978,6 +983,9 @@ static int kvm_put_msrs(CPUX86State *env, int level)
     if (has_msr_hsave_pa) {
         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
     }
+    if (has_msr_tsc_adjust) {
+        kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
+    }
     if (has_msr_tsc_deadline) {
         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
     }

@@ -1234,6 +1242,9 @@ static int kvm_get_msrs(CPUX86State *env)
     if (has_msr_hsave_pa) {
         msrs[n++].index = MSR_VM_HSAVE_PA;
     }
+    if (has_msr_tsc_adjust) {
+        msrs[n++].index = MSR_TSC_ADJUST;
+    }
     if (has_msr_tsc_deadline) {
         msrs[n++].index = MSR_IA32_TSCDEADLINE;
     }

@@ -1308,6 +1319,9 @@ static int kvm_get_msrs(CPUX86State *env)
         case MSR_IA32_TSC:
             env->tsc = msrs[i].data;
             break;
+        case MSR_TSC_ADJUST:
+            env->tsc_adjust = msrs[i].data;
+            break;
         case MSR_IA32_TSCDEADLINE:
             env->tsc_deadline = msrs[i].data;
             break;

target-i386/machine.c +21 -0

index a8be058..4f45d5a 100644
@@ -310,6 +310,24 @@ static const VMStateDescription vmstate_fpop_ip_dp = {
     }
 };
 
+static bool tsc_adjust_needed(void *opaque)
+{
+    CPUX86State *env = opaque;
+
+    return env->tsc_adjust != 0;
+}
+
+static const VMStateDescription vmstate_msr_tsc_adjust = {
+    .name = "cpu/msr_tsc_adjust",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields      = (VMStateField[]) {
+        VMSTATE_UINT64(tsc_adjust, CPUX86State),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static bool tscdeadline_needed(void *opaque)
 {
     CPUX86State *env = opaque;

@@ -457,6 +475,9 @@ static const VMStateDescription vmstate_cpu = {
             .vmsd = &vmstate_fpop_ip_dp,
             .needed = fpop_ip_dp_needed,
         }, {
+            .vmsd = &vmstate_msr_tsc_adjust,
+            .needed = tsc_adjust_needed,
+        }, {
             .vmsd = &vmstate_msr_tscdeadline,
             .needed = tscdeadline_needed,
         }, {

Signature · 1 line

1.8.0.rc0

Andreas Färber

Reviewed-by on v5 1/1

2012-11-30 14:35 UTC #1 lore raw

Am 27.11.2012 06:32, schrieb Will Auld:

Quoted 7 lines

CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the hypervisor vcpu specific locations to store the value of the emulated MSRs. In this way the IA32_TSC_ADJUST value will be included in all reads to the TSC MSR whether through rdmsr or rdtsc.

Quoted 6 lines

As this is a new MSR that the guest may access and modify its value needs to be migrated along with the other MRSs. The changes here are specifically for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added for migrating its value.
Signed-off-by Will Auld <[email protected]>

Reviewed-by Andreas Färber <[email protected]>

from the CPU perspective.

Thanks,
Andreas

Signature · 2 lines

SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Marcelo Tosatti

Applied

2012-11-30 20:39 UTC #2 lore raw

In reply to Will Auld

Quoted 16 lines · Will Auld

CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the hypervisor vcpu specific locations to store the value of the emulated MSRs. In this way the IA32_TSC_ADJUST value will be included in all reads to the TSC MSR whether through rdmsr or rdtsc.
As this is a new MSR that the guest may access and modify its value needs to be migrated along with the other MRSs. The changes here are specifically for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added for migrating its value.
Signed-off-by Will Auld <[email protected]>
---
Andreas,

Quoted 8 lines

Thanks, that helped. I used Stefan's auto-run method this time.

Will

 target-i386/cpu.h     |  2 ++
 target-i386/kvm.c     | 14 ++++++++++++++
 target-i386/machine.c | 21 +++++++++++++++++++++
 3 files changed, 37 insertions(+)

Applied, thanks.

Auld, Will

2012-11-30 20:45 UTC #3 lore raw

Thanks Marcelo!

Quoted 39 lines

-----Original Message-----
From: Marcelo Tosatti [mailto:[email protected]]
Sent: Friday, November 30, 2012 12:40 PM
To: Auld, Will
Cc: qemu-devel; Gleb; Andreas Farber; [email protected]; Dugger, Donald D; Liu, Jinsong; Zhang, Xiantao; [email protected]
Subject: Re: [PATCH V5] target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs
Quoted 3 lines · Will Auld
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to
the
Quoted 1 line
hypervisor vcpu specific locations to store the value of the emulated
MSRs.
Quoted 1 line
In this way the IA32_TSC_ADJUST value will be included in all reads
to
Quoted 11 lines
the TSC MSR whether through rdmsr or rdtsc.
As this is a new MSR that the guest may access and modify its value needs to be migrated along with the other MRSs. The changes here are specifically for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added for migrating its value.
Signed-off-by Will Auld <[email protected]>
---
Andreas,
Quoted 8 lines
Thanks, that helped. I used Stefan's auto-run method this time.
Will
 target-i386/cpu.h     |  2 ++
 target-i386/kvm.c     | 14 ++++++++++++++
 target-i386/machine.c | 21 +++++++++++++++++++++
 3 files changed, 37 insertions(+)
Applied, thanks.

Auld, Will

2013-02-06 22:22 UTC #4 lore raw

In reply to Marcelo Tosatti

Marcelo, Hi,

I have been watching for this patch in the upstream but have not seen it yet. What version of QEMU should it be in?

Thanks,

Will

Quoted 39 lines

-----Original Message-----
From: Marcelo Tosatti [mailto:[email protected]]
Sent: Friday, November 30, 2012 12:40 PM
To: Auld, Will
Cc: qemu-devel; Gleb; Andreas Farber; [email protected]; Dugger, Donald D; Liu, Jinsong; Zhang, Xiantao; [email protected]
Subject: Re: [PATCH V5] target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs
Quoted 3 lines · Will Auld
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to
the
Quoted 1 line
hypervisor vcpu specific locations to store the value of the emulated
MSRs.
Quoted 1 line
In this way the IA32_TSC_ADJUST value will be included in all reads
to
Quoted 11 lines
the TSC MSR whether through rdmsr or rdtsc.
As this is a new MSR that the guest may access and modify its value needs to be migrated along with the other MRSs. The changes here are specifically for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added for migrating its value.
Signed-off-by Will Auld <[email protected]>
---
Andreas,
Quoted 8 lines
Thanks, that helped. I used Stefan's auto-run method this time.
Will
 target-i386/cpu.h     |  2 ++
 target-i386/kvm.c     | 14 ++++++++++++++
 target-i386/machine.c | 21 +++++++++++++++++++++
 3 files changed, 37 insertions(+)
Applied, thanks.

Marcelo Tosatti

2013-02-06 23:35 UTC #5 lore raw

Quoted 7 lines · Will

Marcelo, Hi,
I have been watching for this patch in the upstream but have not seen it yet. What version of QEMU should it be in?
Thanks,
Will

Will, its in the GIT tree:
https://github.com/qemu/qemu/commit/f28558d3d37ad3bc4e35e8ac93f7bf81a0d5622c

As for the next release:
http://www.mail-archive.com/[email protected]/msg153579.html