OMAP GPMC DT bindings
Subsystems (8)
v8 cover OMAP GPMC DT bindings
This is a series of patches to support GPMC peripherals on OMAP boards.
Tested on Linus' master +
omap-next (branch omap-for-v3.8/cleanup-headers-gpmc)
Generated from linux-next as of today, resolving one trivial include file rebase conflict.
The only supported peripheral for now is NAND, but other types would be easy to add.
Version 2 addresses details pointed out by Jon Hunter, Afzal Mohammed and Rob Herring:
- add "reg" and "ti,hwmod" properties to Documentation
- use generic of_mtd functions and the property names defined by them, namely "nand-bus-width" and "nand-ecc-mode"
- reduce the default register space size in the Documentation to 8K, as found in the hwmod code
- switch to a DT layout based on ranges and address translation. Although this property is not currently looked at as long as the handling code still uses the runtime calculation methods, we now have these values in the bindings, eventually allowing us to switch the implementation with less pain.
Version 3 includes fixes pointed out by Jon Hunter:
- better documentation of the 'ranges' property to describe the fact that it's representing the CS lines
- GPMC_CS_CONFIGx -> GPMC_CONFIGx in comments
- drop interrupt-parent from example bindings
- add of_node_put() at the end of the child iteration
Version 4 fixes compilation for !CONFIG_MTD_NAND and includes more details from Jon Hunter and Avinash, Philip:
- Add "num-cs" and "num-waitpins" properties, which will eventually be used to get rid of GPMC_CS_NUM
- Better description of generic nand DT properties
- Dropped patch 3/4 as an equivalent fix was already merged
- Added ti,nand-ecc-use-elm property
Version 5 with regards to Avinash, Philip and Peter Korsgaard:
- Re-add accidentially forgotten Documentation/devicetree/bindings/bus/ti-gpmc.txt
- Rename "software" ecc mode to "sw"
- Initialize gpmc_nand_data->is_elm_used to 'true' rather than 1
- Drop ti,nand-ecc-use-elm binding in favor of a new ecc mode named "bch8-am335xrbl-compatible"
- Add two more patches for section mismatch fixups
Version 6:
- Dropped "bch8-am335xrbl-compatible" mode again. As discussed with Avinash, the ELM issue will be solved subsequently in s separate series.
- re-added a patch to bail out of automatic GPMC instanciation in case of DT boot.
- re-added the "of_node" addition in mtd_nand_omap2.h in 2/5
Version 7: comments from Jon Hunter, all affecting the documentation:
- add num-wait pins properties as they are marked 'required'
- make reg sizes consistent
- AM335x only has 2 wait-pins
Version 8: comments from Grant, thanks to Jon for the summary of all the derivates:
- Added specific compatible strings for different derivates of OMAPs
- Renamed num-cs to gpmc,num-cs
- Renamed num-waitpins to gpmc,num-waitpins
Daniel Mack (5):
ARM: OMAP: gpmc: don't create devices from initcall on DT
mtd: omap-nand: pass device_node in platform data
ARM: OMAP: gpmc-nand: drop __init annotation
ARM: OMAP: gpmc: enable hwecc for AM33xx SoCs
ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
Documentation/devicetree/bindings/bus/ti-gpmc.txt | 84 ++++++++++ .../devicetree/bindings/mtd/gpmc-nand.txt | 76 +++++++++ arch/arm/mach-omap2/gpmc-nand.c | 15 +- arch/arm/mach-omap2/gpmc.c | 182 ++++++++++++++++++++- drivers/mtd/nand/omap2.c | 4 +- include/linux/platform_data/mtd-nand-omap2.h | 4 +- 6 files changed, 355 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/bus/ti-gpmc.txt create mode 100644 Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Signature · 1 line
1.7.11.7
PATCH v8 1/5 ARM: OMAP: gpmc: don't create devices from initcall on DT
On DT driven boards, the gpmc node will match the driver. Hence, there's no need to do that unconditionally from the initcall.
--- arch/arm/mach-omap2/gpmc.c | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm/mach-omap2/gpmc.c +7 -0
@@ -1214,6 +1214,13 @@ static int __init omap_gpmc_init(void)struct platform_device *pdev;char *oh_name ="gpmc" ; +/* +* if the board boots up with a populated DT, do not +* manually add the device from this initcall +*/ +if (of_have_populated_dt ()) +return -ENODEV ; + oh =omap_hwmod_lookup (oh_name);if (!oh) {pr_err ("Could not look up %s\n" , oh_name);
Signature · 1 line
1.7.11.7
PATCH v8 2/5 mtd: omap-nand: pass device_node in platform data
In reply to Daniel MackPass an optional device_node pointer in the platform data, which in turn will be put into a mtd_part_parser_data. This way, code that sets up the platform devices can pass along the node from DT so that the partitions can be parsed.
For non-DT boards, this change has no effect.
--- drivers/mtd/nand/omap2.c | 4 +++- include/linux/platform_data/mtd-nand-omap2.h | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-)
drivers/mtd/nand/omap2.c +3 -1
@@ -1332,6 +1332,7 @@ static int omap_nand_probe(struct platform_device *pdev)dma_cap_mask_t mask;unsigned sig;struct resource *res; +struct mtd_part_parser_data ppdata = {}; pdata = pdev->dev.platform_data;if (pdata ==NULL ) {
@@ -1557,7 +1558,8 @@ static int omap_nand_probe(struct platform_device *pdev) goto out_release_mem_region; } -mtd_device_parse_register (&info->mtd,NULL ,NULL , pdata->parts, + ppdata.of_node = pdata->of_node; +mtd_device_parse_register (&info->mtd,NULL , &ppdata, pdata->parts, pdata->nr_parts);platform_set_drvdata (pdev, &info->mtd);
include/linux/platform_data/mtd-nand-omap2.h +3 -1
@@ -60,6 +60,8 @@ struct omap_nand_platform_data {int devsize;enum omap_ecc ecc_opt;struct gpmc_nand_regs reg; -}; +/* for passing the partitions */ + struct device_node *of_node; +};#endif
Signature · 1 line
1.7.11.7
Tony Lindgren
maintainerPATCH v8 2/5 mtd: omap-nand: pass device_node in platform data
Artem,
Looks like this patch related to making GPMC work with DT was never sent to linux-mtd or to you so adding to cc.
Is this OK to apply along with the GPMC patches, or do you want to take this separately with the MTD patches?
Regards,
Tony
Quoted 52 lines · Daniel Mack
Pass an optional
device_nodepointer in the platform data, which in turn will be put into amtd_part_parser_data. This way, code that sets up the platform devices can pass along the node from DT so that the partitions can be parsed.For non-DT boards, this change has no effect.
Signed-off-by Daniel Mack <[email protected]>--- drivers/mtd/nand/omap2.c | 4 +++- include/linux/platform_data/mtd-nand-omap2.h | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-)drivers/mtd/nand/omap2.c +3
-1@@ -1332,6 +1332,7 @@ static int omap_nand_probe(struct platform_device *pdev)dma_cap_mask_t mask;unsigned sig;struct resource *res; +struct mtd_part_parser_data ppdata = {}; pdata = pdev->dev.platform_data;if (pdata ==NULL ) {@@ -1557,7 +1558,8 @@ static int omap_nand_probe(struct platform_device *pdev) goto out_release_mem_region; } -mtd_device_parse_register (&info->mtd,NULL ,NULL , pdata->parts, + ppdata.of_node = pdata->of_node; +mtd_device_parse_register (&info->mtd,NULL , &ppdata, pdata->parts, pdata->nr_parts);platform_set_drvdata (pdev, &info->mtd);include/linux/platform_data/mtd-nand-omap2.h +3
-1@@ -60,6 +60,8 @@ struct omap_nand_platform_data {int devsize;enum omap_ecc ecc_opt;struct gpmc_nand_regs reg; -}; +/* for passing the partitions */ + struct device_node *of_node; +};#endif Signature · 1 line
1.7.11.7
PATCH v8 2/5 mtd: omap-nand: pass device_node in platform data
Quoted 7 lines · Tony Lindgren
Artem,
Looks like this patch related to making GPMC work with DT was never sent to linux-mtd or to you so adding to cc.
Is this OK to apply along with the GPMC patches, or do you want to take this separately with the MTD patches?
Please, go ahead!
Signature · 9 lines
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Tony Lindgren
maintainerPATCH v8 2/5 mtd: omap-nand: pass device_node in platform data
Quoted 10 lines · Artem Bityutskiy
Quoted 7 lines · Tony Lindgren
Artem,
Looks like this patch related to making GPMC work with DT was never sent to linux-mtd or to you so adding to cc.
Is this OK to apply along with the GPMC patches, or do you want to take this separately with the MTD patches?
Please, go ahead!
OK thanks. Can I add your Acked-by too?
Tony
PATCH v8 2/5 mtd: omap-nand: pass device_node in platform data
Quoted 7 lines · Tony Lindgren
Quoted 6 lines · Artem Bityutskiy
Quoted 5 lines · Tony Lindgren
Artem,
Looks like this patch related to making GPMC work with DT was never sent to linux-mtd or to you so adding to cc.
Quoted 6 lines
Quoted 4 lines
Quoted 2 lines
Is this OK to apply along with the GPMC patches, or do you want to take this separately with the MTD patches?
Please, go ahead!
OK thanks. Can I add your Acked-by too?
Yes Tony, please, do:
Signature · 9 lines
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PATCH v8 3/5 ARM: OMAP: gpmc-nand: drop __init annotation
In reply to Daniel Mackgpmc_nand_init() will be called from another driver's probe() function, so the easiest way to prevent section mismatches is to drop the annotation here.
--- arch/arm/mach-omap2/gpmc-nand.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
arch/arm/mach-omap2/gpmc-nand.c +3 -3
@@ -89,7 +89,7 @@ static int omap2_nand_gpmc_retime(return 0 ; } -static bool __init gpmc_hwecc_bch_capable (enum omap_ecc ecc_opt) +static bool gpmc_hwecc_bch_capable (enum omap_ecc ecc_opt) {/* support only OMAP3 class */ if (!cpu_is_omap34xx ()) {
@@ -110,8 +110,8 @@ static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)return 1 ; } -int __init gpmc_nand_init (struct omap_nand_platform_data *gpmc_nand_data, -struct gpmc_timings *gpmc_t) +int gpmc_nand_init (struct omap_nand_platform_data *gpmc_nand_data, +struct gpmc_timings *gpmc_t) {int err =0 ;struct device *dev = &gpmc_nand_device.dev;
Signature · 1 line
1.7.11.7
PATCH v8 4/5 ARM: OMAP: gpmc: enable hwecc for AM33xx SoCs
In reply to Daniel MackThe am33xx is capable of handling bch error correction modes, so enable that feature in the driver.
--- arch/arm/mach-omap2/gpmc-nand.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
arch/arm/mach-omap2/gpmc-nand.c +5 -4
@@ -92,17 +92,18 @@ static int omap2_nand_gpmc_retime(static bool gpmc_hwecc_bch_capable (enum omap_ecc ecc_opt) {/* support only OMAP3 class */ -if (!cpu_is_omap34xx ()) { +if (!cpu_is_omap34xx () && !soc_is_am33xx ()) {pr_err ("BCH ecc is not supported on this CPU\n" );return 0 ; }/* -* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1. -* Other chips may be added if confirmed to work. +* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 +* and AM33xx derivates. Other chips may be added if confirmed to work. */ if ((ecc_opt ==OMAP_ECC_BCH4_CODE_HW ) && - (!cpu_is_omap3630 () || (GET_OMAP_REVISION () ==0 ))) { + (!cpu_is_omap3630 () || (GET_OMAP_REVISION () ==0 )) && + (!soc_is_am33xx ())) {pr_err ("BCH 4-bit mode is not supported on this CPU\n" );return 0 ; }
Signature · 1 line
1.7.11.7
PATCH v8 5/5 ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
In reply to Daniel MackThis patch adds basic DT bindings for OMAP GPMC.
The actual peripherals are instantiated from child nodes within the GPMC node, and the only type of device that is currently supported is NAND.
Code was added to parse the generic GPMC timing parameters and some documentation with examples on how to use them.
Successfully tested on an AM33xx board.
--- Documentation/devicetree/bindings/bus/ti-gpmc.txt | 84 ++++++++++ .../devicetree/bindings/mtd/gpmc-nand.txt | 76 +++++++++ arch/arm/mach-omap2/gpmc.c | 173 +++++++++++++++++++++ 3 files changed, 333 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/ti-gpmc.txt create mode 100644 Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Documentation/devicetree/bindings/bus/ti-gpmc.txt new file +84 -0
@@ -0,0 +1,84 @@ +Device tree bindings for OMAP general purpose memory controllers (GPMC) + +The actual devices are instantiated from the child nodes of a GPMC node. + +Required properties: + + - compatible: Should be set to one of the following: + + ti,omap2420-gpmc (omap2420) + ti,omap2430-gpmc (omap2430) + ti,omap3430-gpmc (omap3430 & omap3630) + ti,omap4430-gpmc (omap4430 & omap4460 & omap543x) + ti,am3352-gpmc (am335x devices) + + - reg: A resource specifier for the register space + (see the example below) + - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is + completed. + - #address-cells: Must be set to 2 to allow memory address translation + - #size-cells: Must be set to 1 to allow CS address passing + - gpmc,num-cs: The maximum number of chip-select lines that controller + can support. + - gpmc,num-waitpins: The maximum number of wait pins that controller can + support. + - ranges: Must be set up to reflect the memory layout with four + integer values for each chip-select line in use: + + <cs-number> 0 <physical address of mapping> <size> + + Currently, calculated values derived from the contents + of the per-CS register GPMC_CONFIG7 (as set up by the + bootloader) are used for the physical address decoding. + As this will change in the future, filling correct + values here is a requirement. + +Timing properties for child nodes. All are optional and default to 0. + + - gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds + + Chip-select signal timings corresponding to GPMC_CONFIG2: + - gpmc,cs-on: Assertion time + - gpmc,cs-rd-off: Read deassertion time + - gpmc,cs-wr-off: Write deassertion time + + ADV signal timings corresponding to GPMC_CONFIG3: + - gpmc,adv-on: Assertion time + - gpmc,adv-rd-off: Read deassertion time + - gpmc,adv-wr-off: Write deassertion time + + WE signals timings corresponding to GPMC_CONFIG4: + - gpmc,we-on: Assertion time + - gpmc,we-off: Deassertion time + + OE signals timings corresponding to GPMC_CONFIG4: + - gpmc,oe-on: Assertion time + - gpmc,oe-off: Deassertion time + + Access time and cycle time timings corresponding to GPMC_CONFIG5: + - gpmc,page-burst-access: Multiple access word delay + - gpmc,access: Start-cycle to first data valid delay + - gpmc,rd-cycle: Total read cycle time + - gpmc,wr-cycle: Total write cycle time + +The following are only applicable to OMAP3+ and AM335x: + - gpmc,wr-access + - gpmc,wr-data-mux-bus + + +Example for an AM33xx board: + + gpmc: gpmc at 50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x2000>; + interrupts = <100>; + + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ + + /* child nodes go here */ + };
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +76 -0
76 lines not on this page · raw message
arch/arm/mach-omap2/gpmc.c +173 -0
203 lines not on this page · raw message
Signature · 1 line
1.7.11.7
PATCH v8 5/5 ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
Quoted 11 lines · Daniel Mack
This patch adds basic DT bindings for OMAP GPMC.
The actual peripherals are instantiated from child nodes within the GPMC node, and the only type of device that is currently supported is NAND.
Code was added to parse the generic GPMC timing parameters and some documentation with examples on how to use them.
Successfully tested on an AM33xx board.
Signed-off-by Daniel Mack <[email protected]>
For all patches in this series:
PATCH v8 5/5 ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
Quoted 9 lines · Grant Likely
Quoted 8 lines · Daniel Mack
This patch adds basic DT bindings for OMAP GPMC.
The actual peripherals are instantiated from child nodes within the GPMC node, and the only type of device that is currently supported is NAND.
Code was added to parse the generic GPMC timing parameters and some documentation with examples on how to use them.
Quoted 6 lines
Quoted 3 lines
Successfully tested on an AM33xx board.
Signed-off-by Daniel Mack <[email protected]>For all patches in this series:
Acked-by Grant Likely <[email protected]>
Thanks Grant!
Tony, could you apply these patches somewhere so others can base upon them? As I said, I'm now travelling and can't continue my work, so I would much like to know these series at a safe place :)
Again thanks to everyone,
Daniel
PATCH v8 5/5 ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
In reply to Daniel MackHi Daniel,
Nice job!
Quoted 156 lines · Daniel Mack
This patch adds basic DT bindings for OMAP GPMC.
The actual peripherals are instantiated from child nodes within the GPMC node, and the only type of device that is currently supported is NAND.
Code was added to parse the generic GPMC timing parameters and some documentation with examples on how to use them.
Successfully tested on an AM33xx board.
Signed-off-by Daniel Mack <[email protected]>--- Documentation/devicetree/bindings/bus/ti-gpmc.txt | 84 ++++++++++ .../devicetree/bindings/mtd/gpmc-nand.txt | 76 +++++++++ arch/arm/mach-omap2/gpmc.c | 173 +++++++++++++++++++++ 3 files changed, 333 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/ti-gpmc.txt create mode 100644 Documentation/devicetree/bindings/mtd/gpmc-nand.txtDocumentation/devicetree/bindings/bus/ti-gpmc.txt new file +84
-0@@ -0,0 +1,84 @@ +Device tree bindings for OMAP general purpose memory controllers (GPMC) + +The actual devices are instantiated from the child nodes of a GPMC node. + +Required properties: + + - compatible: Should be set to one of the following: + + ti,omap2420-gpmc (omap2420) + ti,omap2430-gpmc (omap2430) + ti,omap3430-gpmc (omap3430 & omap3630) + ti,omap4430-gpmc (omap4430 & omap4460 & omap543x) + ti,am3352-gpmc (am335x devices) + + - reg: A resource specifier for the register space + (see the example below) + - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is + completed. + - #address-cells: Must be set to 2 to allow memory address translation + - #size-cells: Must be set to 1 to allow CS address passing + - gpmc,num-cs: The maximum number of chip-select lines that controller + can support. + - gpmc,num-waitpins: The maximum number of wait pins that controller can + support. + - ranges: Must be set up to reflect the memory layout with four + integer values for each chip-select line in use: + + <cs-number> 0 <physical address of mapping> <size> + + Currently, calculated values derived from the contents + of the per-CS register GPMC_CONFIG7 (as set up by the + bootloader) are used for the physical address decoding. + As this will change in the future, filling correct + values here is a requirement. + +Timing properties for child nodes. All are optional and default to 0. + + - gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds + + Chip-select signal timings corresponding to GPMC_CONFIG2: + - gpmc,cs-on: Assertion time + - gpmc,cs-rd-off: Read deassertion time + - gpmc,cs-wr-off: Write deassertion time + + ADV signal timings corresponding to GPMC_CONFIG3: + - gpmc,adv-on: Assertion time + - gpmc,adv-rd-off: Read deassertion time + - gpmc,adv-wr-off: Write deassertion time + + WE signals timings corresponding to GPMC_CONFIG4: + - gpmc,we-on: Assertion time + - gpmc,we-off: Deassertion time + + OE signals timings corresponding to GPMC_CONFIG4: + - gpmc,oe-on: Assertion time + - gpmc,oe-off: Deassertion time + + Access time and cycle time timings corresponding to GPMC_CONFIG5: + - gpmc,page-burst-access: Multiple access word delay + - gpmc,access: Start-cycle to first data valid delay + - gpmc,rd-cycle: Total read cycle time + - gpmc,wr-cycle: Total write cycle time + +The following are only applicable to OMAP3+ and AM335x: + - gpmc,wr-access + - gpmc,wr-data-mux-bus + + +Example for an AM33xx board: + + gpmc: gpmc at 50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x2000>; + interrupts = <100>; + + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ + + /* child nodes go here */ + };Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +41
-0@@ -0,0 +1,76 @@ +Device tree bindings for GPMC connected NANDs + +GPMC connected NAND (found on OMAP boards) are represented as child nodes of +the GPMC controller with a name of "nand". + +All timing relevant properties as well as generic gpmc child properties are +explained in a separate documents - please refer to +Documentation/devicetree/bindings/bus/ti-gpmc.txt + +For NAND specific properties such as ECC modes or bus width, please refer to +Documentation/devicetree/bindings/mtd/nand.txt + + +Required properties: + + - reg: The CS line the peripheral is connected to + +Optional properties: + + - nand-bus-width: Set this numeric value to 16 if the hardware + is wired that way. If not specified, a bus + width of 8 is assumed. + + - ti,nand-ecc-opt: A string setting the ECC layout to use. One of: + + "sw" Software method (default) + "hw" Hardware method + "hw-romcode" gpmc hamming mode method & romcode layout + "bch4" 4-bit BCH ecc code + "bch8" 8-bit BCH ecc code + +For inline partiton table parsing (optional): + + - #address-cells: should be set to 1 + - #size-cells: should be set to 1 + +Example for an AM33xx board: + + gpmc: gpmc at 50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc";
Documentation/devicetree/bindings/mtd/gpmc-nand.txt line 51
Quoted 10 lines
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +10
-0+ reg = <0x50000000 0x1000000>; + interrupts = <100>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND */ + + nand at 0,0 { + reg = <0 0 0>; /* CS0, offset 0 */
I'm a bit confused by this: what are the other two values in "reg"? I see you've only added a binding for CS.
I've extended a bit on your work and added a binding to enable OneNAND device on my IGEP board.
I might send some patches in case anyone wants to give it a try.
Thanks,
Ezequiel
Tony Lindgren
maintainerPATCH v8 5/5 ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
Quoted 21 lines · Ezequiel Garcia
Quoted 6 lines · Daniel Mack
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +6
-0+ +Example for an AM33xx board: + + gpmc: gpmc at 50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc";Documentation/devicetree/bindings/mtd/gpmc-nand.txt line 51
Quoted 10 lines
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +10
-0+ reg = <0x50000000 0x1000000>; + interrupts = <100>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND */ + + nand at 0,0 { + reg = <0 0 0>; /* CS0, offset 0 */I'm a bit confused by this: what are the other two values in "reg"? I see you've only added a binding for CS.
Quoted 4 lines
I've extended a bit on your work and added a binding to enable OneNAND device on my IGEP board.
I might send some patches in case anyone wants to give it a try.
Daniel, should this be updated to just pass the CS?
Regards,
Tony
PATCH v8 5/5 ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
Quoted 16 lines · Tony Lindgren
Quoted 14 lines · Ezequiel Garcia
Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Quoted 13 lines · Daniel Mack
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +13
-0+ +Example for an AM33xx board: + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x1000000>; + interrupts = <100>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND
*/
Quoted 7 lines
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Documentation/devicetree/bindings/mtd/gpmc-nand.txt line 51
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Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +3
-0+ + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */I'm a bit confused by this: what are the other two values in "reg"? I see you've only added a binding for CS.
Quoted 6 lines
Quoted 4 lines
I've extended a bit on your work and added a binding to enable OneNAND device on my IGEP board.
I might send some patches in case anyone wants to give it a try.
Daniel, should this be updated to just pass the CS?
No, as Rob pointed out earlier in a thread about this topic, the 'ranges' feature will help doing the math for the offset calculation eventually, so we need to pass all three values.
Regards,
Daniel
_______________________________________________
devicetree-discuss mailing list devicetree-discuss-uLR06cmDAlY/[email protected]
https://lists.ozlabs.org/listinfo/devicetree-discuss
Tony Lindgren
maintainerPATCH v8 5/5 ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
Quoted 28 lines · Daniel Mack
Quoted 16 lines · Tony Lindgren
Quoted 14 lines · Ezequiel Garcia
Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Quoted 13 lines · Daniel Mack
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +13
-0+ +Example for an AM33xx board: + + gpmc: gpmc at 50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x1000000>; + interrupts = <100>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND*/
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Documentation/devicetree/bindings/mtd/gpmc-nand.txt line 51
Quoted 3 lines
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +3
-0+ + nand at 0,0 { + reg = <0 0 0>; /* CS0, offset 0 */I'm a bit confused by this: what are the other two values in "reg"? I see you've only added a binding for CS.
I've extended a bit on your work and added a binding to enable OneNAND device on my IGEP board.
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
I might send some patches in case anyone wants to give it a try.
Daniel, should this be updated to just pass the CS?
No, as Rob pointed out earlier in a thread about this topic, the 'ranges' feature will help doing the math for the offset calculation eventually, so we need to pass all three values.
OK thanks. Applying this set into omap-for-v3.9/gpmc.
Also sounds like Ezequiel needs to update his follow up patches accordingly.
Regards,
Tony
PATCH v8 5/5 ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
Quoted 33 lines · Tony Lindgren
Quoted 32 lines · Daniel Mack
Quoted 16 lines · Tony Lindgren
Quoted 14 lines · Ezequiel Garcia
Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Quoted 13 lines · Daniel Mack
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +13
-0+ +Example for an AM33xx board: + + gpmc: gpmc at 50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x1000000>; + interrupts = <100>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND*/
Quoted 13 lines
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Documentation/devicetree/bindings/mtd/gpmc-nand.txt line 51
Quoted 3 lines
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +3
-0+ + nand at 0,0 { + reg = <0 0 0>; /* CS0, offset 0 */I'm a bit confused by this: what are the other two values in "reg"? I see you've only added a binding for CS.
I've extended a bit on your work and added a binding to enable OneNAND device on my IGEP board.
I might send some patches in case anyone wants to give it a try.
Daniel, should this be updated to just pass the CS?
Quoted 8 lines
Quoted 3 lines
No, as Rob pointed out earlier in a thread about this topic, the 'ranges' feature will help doing the math for the offset calculation eventually, so we need to pass all three values.
OK thanks. Applying this set into omap-for-v3.9/gpmc.
Also sounds like Ezequiel needs to update his follow up patches accordingly.
Ok, I'll do that anytime this week.
Thanks,
Signature · 1 line
Ezequiel
Tony Lindgren
maintainerPATCH v8 5/5 ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
Quoted 4 lines · Ezequiel Garcia
Quoted 3 lines · Tony Lindgren
* Daniel Mack <[email protected]> [130114 15:30]:
OK thanks. Applying this set into omap-for-v3.9/gpmc.
Looks like we need ack from for one of the patches Artem before I can push them out, replied to that patch with Artem in Cc.
Quoted 4 lines
Quoted 2 lines
Also sounds like Ezequiel needs to update his follow up patches accordingly.
Ok, I'll do that anytime this week.
OK thanks.
Tony
PATCH v8 5/5 ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
In reply to Tony LindgrenTony,
Quoted 33 lines · Tony Lindgren
Quoted 32 lines · Daniel Mack
Quoted 16 lines · Tony Lindgren
Quoted 14 lines · Ezequiel Garcia
Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Quoted 13 lines · Daniel Mack
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +13
-0+ +Example for an AM33xx board: + + gpmc: gpmc at 50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x1000000>; + interrupts = <100>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND*/
Quoted 13 lines
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Documentation/devicetree/bindings/mtd/gpmc-nand.txt line 51
Quoted 3 lines
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +3
-0+ + nand at 0,0 { + reg = <0 0 0>; /* CS0, offset 0 */I'm a bit confused by this: what are the other two values in "reg"? I see you've only added a binding for CS.
I've extended a bit on your work and added a binding to enable OneNAND device on my IGEP board.
I might send some patches in case anyone wants to give it a try.
Daniel, should this be updated to just pass the CS?
Quoted 8 lines
Quoted 3 lines
No, as Rob pointed out earlier in a thread about this topic, the 'ranges' feature will help doing the math for the offset calculation eventually, so we need to pass all three values.
OK thanks. Applying this set into omap-for-v3.9/gpmc.
Also sounds like Ezequiel needs to update his follow up patches accordingly.
The patches for OneNAND that were posted on the ML apply cleanly on top omap-for-v3.9/gpmc.
What do you want me to update?
Signature · 1 line
Ezequiel
Tony Lindgren
maintainerPATCH v8 5/5 ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
Quoted 42 lines · Ezequiel Garcia
Tony,
Quoted 39 lines · Tony Lindgren
Quoted 28 lines · Daniel Mack
Quoted 16 lines · Tony Lindgren
Quoted 14 lines · Ezequiel Garcia
Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Quoted 13 lines · Daniel Mack
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +13
-0+ +Example for an AM33xx board: + + gpmc: gpmc at 50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x1000000>; + interrupts = <100>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND*/
Quoted 10 lines
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Documentation/devicetree/bindings/mtd/gpmc-nand.txt line 51
Quoted 3 lines
Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file +3
-0+ + nand at 0,0 { + reg = <0 0 0>; /* CS0, offset 0 */I'm a bit confused by this: what are the other two values in "reg"? I see you've only added a binding for CS.
I've extended a bit on your work and added a binding to enable OneNAND device on my IGEP board.
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
I might send some patches in case anyone wants to give it a try.
Daniel, should this be updated to just pass the CS?
No, as Rob pointed out earlier in a thread about this topic, the 'ranges' feature will help doing the math for the offset calculation eventually, so we need to pass all three values.
OK thanks. Applying this set into omap-for-v3.9/gpmc.
Quoted 7 lines
Quoted 2 lines
Also sounds like Ezequiel needs to update his follow up patches accordingly.
The patches for OneNAND that were posted on the ML apply cleanly on top omap-for-v3.9/gpmc.
What do you want me to update?
Oh I though you need to update the binding for the reg for your patches based on the comments above?
Regards,
Tony
PATCH v8 5/5 ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
Quoted 46 lines · Tony Lindgren
Quoted 45 lines · Ezequiel Garcia
Tony,
Quoted 41 lines · Tony Lindgren
Quoted 28 lines · Daniel Mack
Quoted 16 lines · Tony Lindgren
Quoted 14 lines · Ezequiel Garcia
Review
Quoted 13 lines · Daniel Mack
(quoted diff) +13
-0+ +Example for an AM33xx board: + + gpmc: gpmc at 50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x1000000>; + interrupts = <100>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND*/
Quoted 10 lines
Quoted 10 lines
Review
Quoted 3 lines
(quoted diff) +3
-0+ + nand at 0,0 { + reg = <0 0 0>; /* CS0, offset 0 */I'm a bit confused by this: what are the other two values in "reg"? I see you've only added a binding for CS.
I've extended a bit on your work and added a binding to enable OneNAND device on my IGEP board.
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
I might send some patches in case anyone wants to give it a try.
Daniel, should this be updated to just pass the CS?
No, as Rob pointed out earlier in a thread about this topic, the 'ranges' feature will help doing the math for the offset calculation eventually, so we need to pass all three values.
OK thanks. Applying this set into omap-for-v3.9/gpmc.
Also sounds like Ezequiel needs to update his follow up patches accordingly.
Quoted 8 lines
Quoted 4 lines
The patches for OneNAND that were posted on the ML apply cleanly on top omap-for-v3.9/gpmc.
What do you want me to update?
Oh I though you need to update the binding for the reg for your patches based on the comments above?
Mmm... I believe there isn't anything to update (feel free to correct me). Actually, if you take a look at my patches you'll see they're almost identical to Daniel's NAND patches, adapted for OneNAND.
I'll re-send them, to fix a tiny typo in the added Documentation.
Thanks,
Signature · 1 line
Ezequiel