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ARM: Initial support for Tegra114 SoC

PATCH Applied Hiroshi Doyu 2 participants 8 messages Jan 24, 2013 – Jan 28, 2013

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Device tree bindings Arm (32-bit) Arm sub-architectures Tegra architecture support +1 more subsystems
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Hiroshi Doyu

author
#0 lore raw

v4 cover ARM: Initial support for Tegra114 SoC

Hi,

This patchset adds initial support for NVIDIA's new Tegra114 SoC (T114) based on the ARM Cortex-A15 MP. This has the minimal support to allow the kernel to boot up into shell console. This can be used as a basis for adding other device drivers for this SoC. Currently there are 2 evaluation boards available, "Dalmore" and "Pluto".

For those who want to try:

  $ make ARCH=arm tegra_defconfig
  $ scripts/config -e ARCH_TEGRA_114_SOC -d SMP -d DRM -d SUSPEND \
    	-d PM_RUNTIME -d CPU_FREQ -d CPU_IDLE -d HOTPLUG_CPU
  $ make ARCH=arm menuconfig # if needed to configure more
  $ make ARCH=arm all -j9

You may also want to enable CONFIG_ARM_APPENDED_DTB and CONFIG_ARM_ATAG_DTB_COMPAT if the bootloader doesn't support DT yet.

Verified that this single image booted up with "Dalmore(T114)", "Pluto(T114)" and "Cardhu(T30)". For "Cardhu(T30)" with this single image, SPI driver doesn't seem to afford the above configuration , it hangs at boot-up. With SPI disabled, it's ok.

The following changes since commit ac8963ed5d41573c724ce6c1e17f5182d476f2e6:

ARM: tegra: Add CPU nodes to Tegra30 device tree (2013-01-23 10:16:18 -0700)

are available in the git repository at:

git://nv-tegra.nvidia.com/user/hdoyu/linux.git tegra114-base

for you to fetch changes up to ce08503daaffdffd00e8ebdea8c425d68f287efb:

ARM: tegra: Add initial support for Tegra114 SoC. (2013-01-24 10:10:12 +0200)

----------------------------------------------------------------
v4:
Rebased onto Stephen's for-3.9/soc(inc. CCF)
Removed SCU related pathces.

v3:
Rebased onto next-20130115.
Dropped TSC/arch timer patch.
Use /cpus entry in DT to detect cpu core #.

v2:
Rebased against the latest Stephen Warren's linux-next_common Add /cpus entry in DT
Add comment to initialize TSC only in secure mode.

Hiroshi Doyu (6):
ARM: tegra: Use DT /cpu node to detect number of CPU core
ARM: tegra: fuse: Add chip ID Tegra114 0x35
ARM: dt: tegra114: Add new SoC base, Tegra114 SoC
ARM: dt: tegra114: Add new board, Dalmore
ARM: dt: tegra114: Add new board, Pluto
ARM: tegra: Add initial support for Tegra114 SoC.

 arch/arm/boot/dts/Makefile              |    4 +-
 arch/arm/boot/dts/tegra114-dalmore.dts  |   21 ++++++
 arch/arm/boot/dts/tegra114-pluto.dts    |   21 ++++++
 arch/arm/boot/dts/tegra114.dtsi         |  114 +++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/Kconfig             |   10 +++
 arch/arm/mach-tegra/Makefile            |    1 +
 arch/arm/mach-tegra/board-dt-tegra114.c |   48 +++++++++++++
 arch/arm/mach-tegra/common.c            |    1 +
 arch/arm/mach-tegra/fuse.h              |    1 +
 arch/arm/mach-tegra/platsmp.c           |   15 ----
 10 files changed, 220 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm/boot/dts/tegra114-dalmore.dts
 create mode 100644 arch/arm/boot/dts/tegra114-pluto.dts
 create mode 100644 arch/arm/boot/dts/tegra114.dtsi
 create mode 100644 arch/arm/mach-tegra/board-dt-tegra114.c
author
#1 lore raw

PATCH v4 1/6 ARM: tegra: Use DT /cpu node to detect number of CPU core

Tegra SoCs does not use SCU based to detect CPU core numbers but they use DT /cpu node. If it's not provided or failed, it continues as a single core.

Signed-off-by Hiroshi Doyu <[email protected]>
Reviewed-by Lorenzo Pieralisi <[email protected]>

---
Based on the discussion:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-January/140608.html

---
 arch/arm/mach-tegra/platsmp.c |   15 ---------------
 1 file changed, 15 deletions(-)
arch/arm/mach-tegra/platsmp.c +0 -15
index 3ec7fc4..ee847896 100644
@@ -177,23 +177,8 @@ done:
 	return status;
 }
 
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
 static void __init tegra_smp_init_cpus(void)
 {
-	unsigned int i, ncores = scu_get_core_count(scu_base);
-
-	if (ncores > nr_cpu_ids) {
-		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
-			ncores, nr_cpu_ids);
-		ncores = nr_cpu_ids;
-	}
-
-	for (i = 0; i < ncores; i++)
-		set_cpu_possible(i, true);
-
 	set_smp_cross_call(gic_raise_softirq);
 }
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Applied
#2 lore raw

Re: [v4 1/6] ARM: tegra: Use DT /cpu node to detect number of CPU core

Quoted 3 lines · Hiroshi Doyu

Tegra SoCs does not use SCU based to detect CPU core numbers but they use DT /cpu node. If it's not provided or failed, it continues as a single core.

I've applied patch 1 to Tegra's for-3.9/scu-base-rework branch, and patches 2-6 to Tegra's for-3.9/soc-t114 branch.

author
#3 lore raw

PATCH v4 2/6 ARM: tegra: fuse: Add chip ID Tegra114 0x35

In reply to Hiroshi Doyu

Add tegra_chip_id TEGRA114 0x35

Signed-off-by Hiroshi Doyu <[email protected]>
---
 arch/arm/mach-tegra/fuse.h |    1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-tegra/fuse.h +1 -0
index ff1383d..da78434 100644
@@ -37,6 +37,7 @@ enum tegra_revision {
 
 #define TEGRA20		0x20
 #define TEGRA30		0x30
+#define TEGRA114	0x35
 
 extern int tegra_sku_id;
 extern int tegra_cpu_process_id;
Signature · 1 line
1.7.9.5
author
#4 lore raw

PATCH v4 3/6 ARM: dt: tegra114: Add new SoC base, Tegra114 SoC

In reply to Hiroshi Doyu

Initial support for Tegra 114 SoC. This is expected to be included in the board DTS files, Tegra 114 SoC based evaluation board family.

Signed-off-by Hiroshi Doyu <[email protected]>
---
 arch/arm/boot/dts/tegra114.dtsi |  114 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)
 create mode 100644 arch/arm/boot/dts/tegra114.dtsi
arch/arm/boot/dts/tegra114.dtsi new file +114 -0
new file mode 100644
index 0000000..c567916
@@ -0,0 +1,114 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra114";
+	interrupt-parent = <&gic>;
+
+	gic: interrupt-controller {
+		compatible = "arm,cortex-a15-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x50041000 0x1000>,
+		      <0x50042000 0x1000>,
+		      <0x50044000 0x2000>,
+		      <0x50046000 0x2000>;
+		interrupts = <1 9 0xf04>;
+	};
+
+	timer at 60005000 {
+		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
+		reg = <0x60005000 0x400>;
+		interrupts = <0 0 0x04
+			      0 1 0x04
+			      0 41 0x04
+			      0 42 0x04
+			      0 121 0x04
+			      0 122 0x04>;
+	};
+
+	tegra_car: clock {
+		compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	serial at 70006000 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006000 0x40>;
+		reg-shift = <2>;
+		interrupts = <0 36 0x04>;
+		status = "disabled";
+	};
+
+	serial at 70006040 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006040 0x40>;
+		reg-shift = <2>;
+		interrupts = <0 37 0x04>;
+		status = "disabled";
+	};
+
+	serial at 70006200 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006200 0x100>;
+		reg-shift = <2>;
+		interrupts = <0 46 0x04>;
+		status = "disabled";
+	};
+
+	serial at 70006300 {
+		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+		reg = <0x70006300 0x100>;
+		reg-shift = <2>;
+		interrupts = <0 90 0x04>;
+		status = "disabled";
+	};
+
+	rtc {
+		compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
+		reg = <0x7000e000 0x100>;
+		interrupts = <0 2 0x04>;
+	};
+
+	pmc {
+		compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
+		reg = <0x7000e400 0x400>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0>;
+		};
+
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <1>;
+		};
+
+		cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <2>;
+		};
+
+		cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <3>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <1 13 0xf08>,
+			     <1 14 0xf08>,
+			     <1 11 0xf08>,
+			     <1 10 0xf08>;
+	};
+};
Signature · 1 line
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author
#5 lore raw

PATCH v4 4/6 ARM: dt: tegra114: Add new board, Dalmore

In reply to Hiroshi Doyu

Add a new evaluation board, Dalmore for Tegra 114 family.

Signed-off-by Hiroshi Doyu <[email protected]>
---
 arch/arm/boot/dts/Makefile             |    3 ++-
 arch/arm/boot/dts/tegra114-dalmore.dts |   21 +++++++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/tegra114-dalmore.dts
arch/arm/boot/dts/Makefile +2 -1
index e44da40..88ea9fc 100644
@@ -143,7 +143,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 	tegra20-ventana.dtb \
 	tegra20-whistler.dtb \
 	tegra30-cardhu-a02.dtb \
-	tegra30-cardhu-a04.dtb
+	tegra30-cardhu-a04.dtb \
+	tegra114-dalmore.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
 	vexpress-v2p-ca9.dtb \
 	vexpress-v2p-ca15-tc1.dtb \
arch/arm/boot/dts/tegra114-dalmore.dts new file +21 -0
new file mode 100644
index 0000000..a30aca6
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+/include/ "tegra114.dtsi"
+
+/ {
+	model = "NVIDIA Tegra114 Dalmore evaluation board";
+	compatible = "nvidia,dalmore", "nvidia,tegra114";
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	serial at 70006300 {
+		status = "okay";
+		clock-frequency = <408000000>;
+	};
+
+	pmc {
+		nvidia,invert-interrupt;
+	};
+};
Signature · 1 line
1.7.9.5
author
#6 lore raw

PATCH v4 5/6 ARM: dt: tegra114: Add new board, Pluto

In reply to Hiroshi Doyu

Add a new evaluation board, Pluto for Tegra 114 family.

Signed-off-by Hiroshi Doyu <[email protected]>
---
 arch/arm/boot/dts/Makefile           |    3 ++-
 arch/arm/boot/dts/tegra114-pluto.dts |   21 +++++++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/tegra114-pluto.dts
arch/arm/boot/dts/Makefile +2 -1
index 88ea9fc..b53f18f 100644
@@ -144,7 +144,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 	tegra20-whistler.dtb \
 	tegra30-cardhu-a02.dtb \
 	tegra30-cardhu-a04.dtb \
-	tegra114-dalmore.dtb
+	tegra114-dalmore.dtb \
+	tegra114-pluto.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
 	vexpress-v2p-ca9.dtb \
 	vexpress-v2p-ca15-tc1.dtb \
arch/arm/boot/dts/tegra114-pluto.dts new file +21 -0
new file mode 100644
index 0000000..9bea8f5
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+/include/ "tegra114.dtsi"
+
+/ {
+	model = "NVIDIA Tegra114 Pluto evaluation board";
+	compatible = "nvidia,pluto", "nvidia,tegra114";
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	serial at 70006300 {
+		status = "okay";
+		clock-frequency = <408000000>;
+	};
+
+	pmc {
+		nvidia,invert-interrupt;
+	};
+};
Signature · 1 line
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author
#7 lore raw

PATCH v4 6/6 ARM: tegra: Add initial support for Tegra114 SoC.

In reply to Hiroshi Doyu

Add new Tegra 114 SoC support.

Signed-off-by Hiroshi Doyu <[email protected]>
---
 arch/arm/mach-tegra/Kconfig             |   10 +++++++
 arch/arm/mach-tegra/Makefile            |    1 +
 arch/arm/mach-tegra/board-dt-tegra114.c |   48 +++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/common.c            |    1 +
 4 files changed, 60 insertions(+)
 create mode 100644 arch/arm/mach-tegra/board-dt-tegra114.c
arch/arm/mach-tegra/Kconfig +10 -0
index abc688f..eada60f 100644
@@ -45,6 +45,16 @@ config ARCH_TEGRA_3x_SOC
 	  Support for NVIDIA Tegra T30 processor family, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
 
+config ARCH_TEGRA_114_SOC
+	bool "Enable support for Tegra114 family"
+	select ARM_GIC
+	select CPU_V7
+	select ARM_L1_CACHE_SHIFT_6
+	select ARM_ARCH_TIMER
+	help
+	  Support for NVIDIA Tegra T114 processor family, based on the
+	  ARM CortexA15MP CPU
+
 config TEGRA_PCI
 	bool "PCI Express support"
 	depends on ARCH_TEGRA_2x_SOC
arch/arm/mach-tegra/Makefile +1 -0
index 432f2a5..e1eaf30 100644
@@ -28,6 +28,7 @@ obj-$(CONFIG_TEGRA_PCI)			+= pcie.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-dt-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= board-dt-tegra114.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-harmony-pcie.o
arch/arm/mach-tegra/board-dt-tegra114.c new file +48 -0

48 lines not on this page · raw message

arch/arm/mach-tegra/common.c +1 -0
index 87dd69c..2f13513 100644
@@ -59,6 +59,7 @@ u32 tegra_uart_config[4] = {
 
 #ifdef CONFIG_OF
 static const struct of_device_id tegra_dt_irq_match[] __initconst = {
+	{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init },
 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
 	{ }
 };
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