Preparatory GIC patches for arm64 support
Subsystems (21)
v2 cover Preparatory GIC patches for arm64 support
Hi,
That's the second version of the GIC clean-up patches to support arm64. The only change from v1 is that the second patch (chained_irq.h) also covers drivers/gpio and drivers/pinctrl (#include change).
Catalin
Catalin Marinas (4):
arm: Move the set_handle_irq and handle_arch_irq declarations to
asm/irq.h
arm: Move chained_irq_(enter|exit) to a generic file
irqchip: gic: Call handle_bad_irq() directly
irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
arch/arm/include/asm/irq.h | 5 +++ arch/arm/include/asm/mach/irq.h | 36 -------------------- arch/arm/mach-at91/gpio.c | 3 +- arch/arm/mach-exynos/common.c | 1 + arch/arm/mach-exynos/platsmp.c | 8 ----- arch/arm/mach-highbank/platsmp.c | 7 ---- arch/arm/mach-imx/platsmp.c | 12 ------- arch/arm/mach-msm/platsmp.c | 8 ----- arch/arm/mach-omap2/omap-smp.c | 7 ---- arch/arm/mach-shmobile/smp-emev2.c | 7 ---- arch/arm/mach-shmobile/smp-r8a7779.c | 7 ---- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ---- arch/arm/mach-socfpga/platsmp.c | 12 ------- arch/arm/mach-spear13xx/platsmp.c | 8 ----- arch/arm/mach-tegra/platsmp.c | 8 ----- arch/arm/mach-ux500/platsmp.c | 8 ----- arch/arm/plat-samsung/irq-vic-timer.c | 3 +- arch/arm/plat-samsung/s5p-irq-gpioint.c | 3 +- arch/arm/plat-versatile/platsmp.c | 8 ----- drivers/gpio/gpio-msm-v2.c | 3 +- drivers/gpio/gpio-mxc.c | 2 +- drivers/gpio/gpio-omap.c | 3 +- drivers/gpio/gpio-pl061.c | 2 +- drivers/gpio/gpio-pxa.c | 3 +- drivers/gpio/gpio-tegra.c | 3 +- drivers/irqchip/irq-gic.c | 32 +++++++++++++----- drivers/irqchip/irq-vic.c | 2 +- drivers/pinctrl/pinctrl-at91.c | 3 +- drivers/pinctrl/pinctrl-exynos.c | 3 +- drivers/pinctrl/pinctrl-nomadik.c | 2 +- drivers/pinctrl/pinctrl-sirf.c | 2 +- drivers/pinctrl/spear/pinctrl-plgpio.c | 2 +- drivers/staging/imx-drm/ipu-v3/ipu-common.c | 2 +- include/linux/irqchip/arm-gic.h | 1 - include/linux/irqchip/chained_irq.h | 52 +++++++++++++++++++++++++++++ 35 files changed, 97 insertions(+), 178 deletions(-) create mode 100644 include/linux/irqchip/chained_irq.h
PATCH v2 1/4 arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h
This patch prepares the removal of <asm/mach/irq.h> include in the GIC and VIC irqchip drivers.
--- arch/arm/include/asm/irq.h | 5 +++++ arch/arm/include/asm/mach/irq.h | 5 ----- drivers/irqchip/irq-vic.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-)
arch/arm/include/asm/irq.h +5 -0
@@ -30,6 +30,11 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *);void handle_IRQ (unsigned int ,struct pt_regs *);void init_IRQ (void ); +#ifdef CONFIG_MULTI_IRQ_HANDLER +extern void (*handle_arch_irq)(struct pt_regs *); +extern void set_handle_irq (void (*handle_irq)(struct pt_regs *)); +#endif +#endif #endif
arch/arm/include/asm/mach/irq.h +0 -5
@@ -20,11 +20,6 @@ struct seq_file;extern void init_FIQ (int );extern int show_fiq_list (struct seq_file *,int ); -#ifdef CONFIG_MULTI_IRQ_HANDLER -extern void (*handle_arch_irq)(struct pt_regs *); -extern void set_handle_irq (void (*handle_irq)(struct pt_regs *)); -#endif -/* * This is for easy migration, but should be changed in the source */
drivers/irqchip/irq-vic.c +1 -1
@@ -33,7 +33,7 @@#include <linux/irqchip/arm-vic.h> #include <asm/exception.h> -#include <asm/mach/irq.h> +#include <asm/irq.h> #include "irqchip.h"
PATCH v2 2/4 arm: Move chained_irq_(enter|exit) to a generic file
In reply to Catalin MarinasThese functions have been introduced by commit 10a8c383 (irq: introduce entry and exit functions for chained handlers) in asm/mach/irq.h. This patch moves them to linux/irqchip/chained_irq.h so that generic irqchip drivers do not rely on architecture specific header files.
--- arch/arm/include/asm/mach/irq.h | 31 ----------------- arch/arm/mach-at91/gpio.c | 3 +- arch/arm/mach-exynos/common.c | 1 + arch/arm/plat-samsung/irq-vic-timer.c | 3 +- arch/arm/plat-samsung/s5p-irq-gpioint.c | 3 +- drivers/gpio/gpio-msm-v2.c | 3 +- drivers/gpio/gpio-mxc.c | 2 +- drivers/gpio/gpio-omap.c | 3 +- drivers/gpio/gpio-pl061.c | 2 +- drivers/gpio/gpio-pxa.c | 3 +- drivers/gpio/gpio-tegra.c | 3 +- drivers/irqchip/irq-gic.c | 1 + drivers/pinctrl/pinctrl-at91.c | 3 +- drivers/pinctrl/pinctrl-exynos.c | 3 +- drivers/pinctrl/pinctrl-nomadik.c | 2 +- drivers/pinctrl/pinctrl-sirf.c | 2 +- drivers/pinctrl/spear/pinctrl-plgpio.c | 2 +- drivers/staging/imx-drm/ipu-v3/ipu-common.c | 2 +- include/linux/irqchip/chained_irq.h | 52 +++++++++++++++++++++++++++++ 19 files changed, 69 insertions(+), 55 deletions(-) create mode 100644 include/linux/irqchip/chained_irq.h
arch/arm/include/asm/mach/irq.h +0 -31
@@ -30,35 +30,4 @@ do { \raw_spin_unlock (&desc->lock); \ } while(0) -#ifndef __ASSEMBLY__ -/* -* Entry/exit functions for chained handlers where the primary IRQ chip -* may implement either fasteoi or level-trigger flow control. -*/ -static inline void chained_irq_enter (struct irq_chip *chip, -struct irq_desc *desc) -{ -/* FastEOI controllers require no action on entry. */ -if (chip->irq_eoi) -return ; - -if (chip->irq_mask_ack) { - chip->irq_mask_ack (&desc->irq_data); - }else { - chip->irq_mask (&desc->irq_data); -if (chip->irq_ack) - chip->irq_ack (&desc->irq_data); - } -} - -static inline void chained_irq_exit (struct irq_chip *chip, -struct irq_desc *desc) -{ -if (chip->irq_eoi) - chip->irq_eoi (&desc->irq_data); -else - chip->irq_unmask (&desc->irq_data); -} -#endif -#endif
arch/arm/mach-at91/gpio.c +1 -2
@@ -22,10 +22,9 @@#include <linux/module.h> #include <linux/io.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/of_address.h> -#include <asm/mach/irq.h> -#include <mach/hardware.h> #include <mach/at91_pio.h>
arch/arm/mach-exynos/common.c +1 -0
@@ -25,6 +25,7 @@#include <linux/irqchip.h> #include <linux/of_address.h> #include <linux/irqchip/arm-gic.h> +#include <linux/irqchip/chained_irq.h> #include <asm/proc-fns.h> #include <asm/exception.h>
arch/arm/plat-samsung/irq-vic-timer.c +1 -2
@@ -16,6 +16,7 @@#include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> #include <linux/io.h> #include <mach/map.h>
@@ -23,8 +24,6 @@#include <plat/irq-vic-timer.h> #include <plat/regs-timer.h> -#include <asm/mach/irq.h> -static void s3c_irq_demux_vic_timer (unsigned int irq,struct irq_desc *desc) {struct irq_chip *chip =irq_get_chip (irq);
arch/arm/plat-samsung/s5p-irq-gpioint.c +1 -2
@@ -14,6 +14,7 @@#include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> #include <linux/io.h> #include <linux/gpio.h> #include <linux/slab.h>
@@ -22,8 +23,6 @@#include <plat/gpio-core.h> #include <plat/gpio-cfg.h> -#include <asm/mach/irq.h> -#define GPIO_BASE (chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))#define CON_OFFSET 0x700
drivers/gpio/gpio-msm-v2.c +1 -2
@@ -23,13 +23,12 @@#include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <linux/irqchip/chained_irq.h> #include <linux/irq.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/spinlock.h> -#include <asm/mach/irq.h> -#include <mach/msm_gpiomux.h> #include <mach/msm_iomap.h>
drivers/gpio/gpio-mxc.c +1 -1
@@ -24,6 +24,7 @@#include <linux/io.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/slab.h>
@@ -32,7 +33,6 @@#include <linux/of_device.h> #include <linux/module.h> #include <asm-generic/bug.h> -#include <asm/mach/irq.h> enum mxc_gpio_hwtype {IMX1_GPIO ,/* runs on i.mx1 */
drivers/gpio/gpio-omap.c +1 -2
@@ -25,11 +25,10 @@#include <linux/of.h> #include <linux/of_device.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/gpio.h> #include <linux/platform_data/gpio-omap.h> -#include <asm/mach/irq.h> -#define OFF_MODE 1static LIST_HEAD (omap_gpio_list);
drivers/gpio/gpio-pl061.c +1 -1
@@ -15,6 +15,7 @@#include <linux/io.h> #include <linux/ioport.h> #include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> #include <linux/bitops.h> #include <linux/workqueue.h> #include <linux/gpio.h>
@@ -23,7 +24,6 @@#include <linux/amba/pl061.h> #include <linux/slab.h> #include <linux/pm.h> -#include <asm/mach/irq.h> #define GPIODIR 0x400#define GPIOIS 0x404
drivers/gpio/gpio-pxa.c +1 -2
@@ -19,6 +19,7 @@#include <linux/init.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_device.h>
@@ -26,8 +27,6 @@#include <linux/syscore_ops.h> #include <linux/slab.h> -#include <asm/mach/irq.h> -#include <mach/irqs.h> /*
drivers/gpio/gpio-tegra.c +1 -2
@@ -27,11 +27,10 @@#include <linux/platform_device.h> #include <linux/module.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/pinctrl/consumer.h> #include <linux/pm.h> -#include <asm/mach/irq.h> -#define GPIO_BANK (x) ((x) >> 5)#define GPIO_PORT (x) (((x) >> 3) & 0x3)#define GPIO_BIT (x) ((x) & 0x7)
drivers/irqchip/irq-gic.c +1 -0
@@ -38,6 +38,7 @@#include <linux/interrupt.h> #include <linux/percpu.h> #include <linux/slab.h> +#include <linux/irqchip/chained_irq.h> #include <linux/irqchip/arm-gic.h> #include <asm/irq.h>
drivers/pinctrl/pinctrl-at91.c +1 -2
@@ -18,6 +18,7 @@#include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/io.h> #include <linux/gpio.h> #include <linux/pinctrl/machine.h>
@@ -27,8 +28,6 @@/* Since we request GPIOs from ourself */ #include <linux/pinctrl/consumer.h> -#include <asm/mach/irq.h> -#include <mach/hardware.h> #include <mach/at91_pio.h>
drivers/pinctrl/pinctrl-exynos.c +1 -2
@@ -23,13 +23,12 @@#include <linux/interrupt.h> #include <linux/irqdomain.h> #include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> #include <linux/of_irq.h> #include <linux/io.h> #include <linux/slab.h> #include <linux/err.h> -#include <asm/mach/irq.h> -#include "pinctrl-samsung.h" #include "pinctrl-exynos.h"
drivers/pinctrl/pinctrl-nomadik.c +1 -1
@@ -23,6 +23,7 @@#include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/slab.h> #include <linux/of_device.h> #include <linux/of_address.h>
@@ -33,7 +34,6 @@/* Since we request GPIOs from ourself */ #include <linux/pinctrl/consumer.h> #include <linux/platform_data/pinctrl-nomadik.h> -#include <asm/mach/irq.h> #include "pinctrl-nomadik.h" #include "core.h"
drivers/pinctrl/pinctrl-sirf.c +1 -1
@@ -14,6 +14,7 @@#include <linux/slab.h> #include <linux/err.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> #include <linux/pinctrl/consumer.h>
@@ -25,7 +26,6 @@#include <linux/bitops.h> #include <linux/gpio.h> #include <linux/of_gpio.h> -#include <asm/mach/irq.h> #define DRIVER_NAME "pinmux-sirf"
drivers/pinctrl/spear/pinctrl-plgpio.c +1 -1
@@ -15,12 +15,12 @@#include <linux/io.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/irqchip/chained_irq.h> #include <linux/module.h> #include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <linux/pm.h> #include <linux/spinlock.h> -#include <asm/mach/irq.h> #define MAX_GPIO_PER_REG 32#define PIN_OFFSET (pin) (pin % MAX_GPIO_PER_REG)
drivers/staging/imx-drm/ipu-v3/ipu-common.c +1 -1
@@ -25,8 +25,8 @@#include <linux/clk.h> #include <linux/list.h> #include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> #include <linux/of_device.h> -#include <asm/mach/irq.h> #include "imx-ipu-v3.h" #include "ipu-prv.h"
include/linux/irqchip/chained_irq.h new file +52 -0
52 lines not on this page · raw message
PATCH v2 3/4 irqchip: gic: Call handle_bad_irq() directly
In reply to Catalin MarinasPreviously, the gic_handle_cascade_irq() function was calling the ARM-specific do_bad_IRQ() function which calls handle_bad_irq() after acquiring the desk->lock. Locking the cascaded IRQ desc is not needed for error reporting, so just call handle_bad_irq() directly.
--- drivers/irqchip/irq-gic.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/irqchip/irq-gic.c +1 -2
@@ -44,7 +44,6 @@#include <asm/irq.h> #include <asm/exception.h> #include <asm/smp_plat.h> -#include <asm/mach/irq.h> #include "irqchip.h"
@@ -324,7 +323,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) cascade_irq =irq_find_mapping (chip_data->domain, gic_irq);if (unlikely (gic_irq <32 || gic_irq >1020 )) -do_bad_IRQ (cascade_irq, desc); +handle_bad_irq (cascade_irq, desc);else generic_handle_irq (cascade_irq);
PATCH v2 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
In reply to Catalin MarinasAll the calls to gic_secondary_init() pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.
--- arch/arm/mach-exynos/platsmp.c | 8 -------- arch/arm/mach-highbank/platsmp.c | 7 ------- arch/arm/mach-imx/platsmp.c | 12 ------------ arch/arm/mach-msm/platsmp.c | 8 -------- arch/arm/mach-omap2/omap-smp.c | 7 ------- arch/arm/mach-shmobile/smp-emev2.c | 7 ------- arch/arm/mach-shmobile/smp-r8a7779.c | 7 ------- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ------- arch/arm/mach-socfpga/platsmp.c | 12 ------------ arch/arm/mach-spear13xx/platsmp.c | 8 -------- arch/arm/mach-tegra/platsmp.c | 8 -------- arch/arm/mach-ux500/platsmp.c | 8 -------- arch/arm/plat-versatile/platsmp.c | 8 -------- drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++------- include/linux/irqchip/arm-gic.h | 1 - 15 files changed, 21 insertions(+), 115 deletions(-)
arch/arm/mach-exynos/platsmp.c +0 -8
@@ -20,7 +20,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h>
@@ -77,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock);static void __cpuinit exynos_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */
arch/arm/mach-highbank/platsmp.c +0 -7
@@ -17,7 +17,6 @@#include <linux/init.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/smp_scu.h>
@@ -25,11 +24,6 @@extern void secondary_startup (void ); -static void __cpuinit highbank_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit highbank_boot_secondary (unsigned int cpu,struct task_struct *idle) {highbank_set_cpu_jump (cpu, secondary_startup);
@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)struct smp_operations highbank_smp_ops__initdata = { .smp_init_cpus = highbank_smp_init_cpus, .smp_prepare_cpus = highbank_smp_prepare_cpus, - .smp_secondary_init = highbank_secondary_init, .smp_boot_secondary = highbank_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = highbank_cpu_die,
arch/arm/mach-imx/platsmp.c +0 -12
@@ -12,7 +12,6 @@#include <linux/init.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/page.h> #include <asm/smp_scu.h> #include <asm/mach/map.h>
@@ -42,16 +41,6 @@ void __init imx_scu_map_io(void) scu_base =IMX_IO_ADDRESS (base); } -static void __cpuinit imx_secondary_init (unsigned int cpu) -{ -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -} -static int __cpuinit imx_boot_secondary (unsigned int cpu,struct task_struct *idle) {imx_set_cpu_jump (cpu, v7_secondary_startup);
@@ -86,7 +75,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)struct smp_operations imx_smp_ops__initdata = { .smp_init_cpus = imx_smp_init_cpus, .smp_prepare_cpus = imx_smp_prepare_cpus, - .smp_secondary_init = imx_secondary_init, .smp_boot_secondary = imx_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = imx_cpu_die,
arch/arm/mach-msm/platsmp.c +0 -8
@@ -15,7 +15,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/cputype.h>
@@ -42,13 +41,6 @@ static inline int get_core_count(void)static void __cpuinit msm_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */
arch/arm/mach-omap2/omap-smp.c +0 -7
@@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu) 4, 0, 0, 0, 0, 0);/* -* If any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * Synchronise with the boot thread. */ spin_lock (&boot_lock);
arch/arm/mach-shmobile/smp-emev2.c +0 -7
@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/emev2.h> #include <asm/smp_plat.h>
@@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu) } -static void __cpuinit emev2_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit emev2_boot_secondary (unsigned int cpu,struct task_struct *idle) { cpu =cpu_logical_map (cpu);
@@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)struct smp_operations emev2_smp_ops__initdata = { .smp_init_cpus = emev2_smp_init_cpus, .smp_prepare_cpus = emev2_smp_prepare_cpus, - .smp_secondary_init = emev2_secondary_init, .smp_boot_secondary = emev2_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = emev2_cpu_kill,
arch/arm/mach-shmobile/smp-r8a7779.c +0 -7
@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/r8a7779.h> #include <asm/smp_plat.h>
@@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) } -static void __cpuinit r8a7779_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit r8a7779_boot_secondary (unsigned int cpu,struct task_struct *idle) {struct r8a7779_pm_ch *ch =NULL ;
@@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)struct smp_operations r8a7779_smp_ops__initdata = { .smp_init_cpus = r8a7779_smp_init_cpus, .smp_prepare_cpus = r8a7779_smp_prepare_cpus, - .smp_secondary_init = r8a7779_secondary_init, .smp_boot_secondary = r8a7779_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = r8a7779_cpu_kill,
arch/arm/mach-shmobile/smp-sh73a0.c +0 -7
@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h>
@@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)return scu_get_core_count (scu_base); } -static void __cpuinit sh73a0_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit sh73a0_boot_secondary (unsigned int cpu,struct task_struct *idle) { cpu =cpu_logical_map (cpu);
@@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)struct smp_operations sh73a0_smp_ops__initdata = { .smp_init_cpus = sh73a0_smp_init_cpus, .smp_prepare_cpus = sh73a0_smp_prepare_cpus, - .smp_secondary_init = sh73a0_secondary_init, .smp_boot_secondary = sh73a0_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = sh73a0_cpu_kill,
arch/arm/mach-socfpga/platsmp.c +0 -12
@@ -22,7 +22,6 @@#include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_scu.h>
@@ -33,16 +32,6 @@extern void __iomem *sys_manager_base_addr;extern void __iomem *rst_manager_base_addr; -static void __cpuinit socfpga_secondary_init (unsigned int cpu) -{ -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -} -static int __cpuinit socfpga_boot_secondary (unsigned int cpu,struct task_struct *idle) {int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
@@ -106,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu)struct smp_operations socfpga_smp_ops__initdata = { .smp_init_cpus = socfpga_smp_init_cpus, .smp_prepare_cpus = socfpga_smp_prepare_cpus, - .smp_secondary_init = socfpga_secondary_init, .smp_boot_secondary = socfpga_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = socfpga_cpu_die,
arch/arm/mach-spear13xx/platsmp.c +0 -8
@@ -15,7 +15,6 @@#include <linux/jiffies.h> #include <linux/io.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_scu.h> #include <mach/spear.h>
@@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);static void __cpuinit spear13xx_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */
arch/arm/mach-tegra/platsmp.c +0 -8
@@ -18,7 +18,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <linux/clk/tegra.h> #include <asm/cacheflush.h>
@@ -45,13 +44,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);static void __cpuinit tegra_secondary_init (unsigned int cpu) { -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -cpumask_set_cpu (cpu, &tegra_cpu_init_mask); }
arch/arm/mach-ux500/platsmp.c +0 -8
@@ -16,7 +16,6 @@#include <linux/device.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h>
@@ -55,13 +54,6 @@ static DEFINE_SPINLOCK(boot_lock);static void __cpuinit ux500_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */
arch/arm/plat-versatile/platsmp.c +0 -8
@@ -14,7 +14,6 @@#include <linux/device.h> #include <linux/jiffies.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h>
@@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);void __cpuinit versatile_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */
drivers/irqchip/irq-gic.c +21 -7
@@ -28,6 +28,7 @@#include <linux/module.h> #include <linux/list.h> #include <linux/smp.h> +#include <linux/cpu.h> #include <linux/cpu_pm.h> #include <linux/cpumask.h> #include <linux/io.h>
@@ -678,6 +679,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,return 0 ; } +#ifdef CONFIG_SMP +static int __cpuinit gic_secondary_init (struct notifier_block *nfb, +unsigned long action,void *hcpu) +{ +if (action ==CPU_STARTING ) +gic_cpu_init (&gic_data[0 ]); +return NOTIFY_OK ; +} + +/* +* Notifier for enabling the GIC CPU interface. Set an arbitrarily high +* priority because the GIC needs to be up before the ARM generic timers. +*/ +static struct notifier_block __cpuinitdata gic_cpu_notifier = { + .notifier_call = gic_secondary_init, + .priority =100 , +}; +#endif +const struct irq_domain_ops gic_irq_domain_ops = { .map = gic_irq_domain_map, .xlate = gic_irq_domain_xlate,
@@ -768,6 +788,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,#ifdef CONFIG_SMP set_smp_cross_call (gic_raise_softirq); +register_cpu_notifier (&gic_cpu_notifier);#endif set_handle_irq (gic_handle_irq);
@@ -778,13 +799,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,gic_pm_init (gic); } -void __cpuinit gic_secondary_init (unsigned int gic_nr) -{ -BUG_ON (gic_nr >=MAX_GIC_NR ); - -gic_cpu_init (&gic_data[gic_nr]); -} -#ifdef CONFIG_OF static int gic_cnt__initdata =0 ;
include/linux/irqchip/arm-gic.h +0 -1
@@ -36,7 +36,6 @@ extern struct irq_chip gic_arch_extn;void gic_init_bases (unsigned int ,int ,void __iomem *,void __iomem *,u32 offset,struct device_node *); -void gic_secondary_init (unsigned int );void gic_cascade_irq (unsigned int gic_nr,unsigned int irq); static inline void gic_init(unsigned int nr, int start,
PATCH v2 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 16 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.Signed-off-by Catalin Marinas <[email protected]>Acked-by Stephen Warren <[email protected]>Acked-by Viresh Kumar <[email protected]>Acked-by Rob Herring <[email protected]>Acked-by Simon Horman <[email protected]>Tested-by Simon Horman <[email protected]>Acked-by Srinidhi Kasagar <[email protected]>Cc Russell King <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Kukjin Kim <[email protected]>
Quoted 8 lines
Cc Sascha Hauer <[email protected]>Cc David Brown <[email protected]>Cc Bryan Huntsman <[email protected]>Cc Tony Lindgren <[email protected]>Cc Magnus Damm <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Shiraz Hashim <[email protected]>Cc Linus Walleij <[email protected]>
What is your plan in terms of merge path and schedule? My mcpm series would depend on this.
Quoted 472 lines
--- arch/arm/mach-exynos/platsmp.c | 8 -------- arch/arm/mach-highbank/platsmp.c | 7 ------- arch/arm/mach-imx/platsmp.c | 12 ------------ arch/arm/mach-msm/platsmp.c | 8 -------- arch/arm/mach-omap2/omap-smp.c | 7 ------- arch/arm/mach-shmobile/smp-emev2.c | 7 ------- arch/arm/mach-shmobile/smp-r8a7779.c | 7 ------- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ------- arch/arm/mach-socfpga/platsmp.c | 12 ------------ arch/arm/mach-spear13xx/platsmp.c | 8 -------- arch/arm/mach-tegra/platsmp.c | 8 -------- arch/arm/mach-ux500/platsmp.c | 8 -------- arch/arm/plat-versatile/platsmp.c | 8 -------- drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++------- include/linux/irqchip/arm-gic.h | 1 - 15 files changed, 21 insertions(+), 115 deletions(-)arch/arm/mach-exynos/platsmp.c +0
-8@@ -20,7 +20,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -77,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock);static void __cpuinit exynos_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ arch/arm/mach-highbank/platsmp.c +0
-7@@ -17,7 +17,6 @@#include <linux/init.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/smp_scu.h> @@ -25,11 +24,6 @@extern void secondary_startup (void ); -static void __cpuinit highbank_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit highbank_boot_secondary (unsigned int cpu,struct task_struct *idle) {highbank_set_cpu_jump (cpu, secondary_startup);@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)struct smp_operations highbank_smp_ops__initdata = { .smp_init_cpus = highbank_smp_init_cpus, .smp_prepare_cpus = highbank_smp_prepare_cpus, - .smp_secondary_init = highbank_secondary_init, .smp_boot_secondary = highbank_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = highbank_cpu_die,arch/arm/mach-imx/platsmp.c +0
-12@@ -12,7 +12,6 @@#include <linux/init.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/page.h> #include <asm/smp_scu.h> #include <asm/mach/map.h> @@ -42,16 +41,6 @@ void __init imx_scu_map_io(void) scu_base =IMX_IO_ADDRESS (base); } -static void __cpuinit imx_secondary_init (unsigned int cpu) -{ -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -} -static int __cpuinit imx_boot_secondary (unsigned int cpu,struct task_struct *idle) {imx_set_cpu_jump (cpu, v7_secondary_startup);@@ -86,7 +75,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)struct smp_operations imx_smp_ops__initdata = { .smp_init_cpus = imx_smp_init_cpus, .smp_prepare_cpus = imx_smp_prepare_cpus, - .smp_secondary_init = imx_secondary_init, .smp_boot_secondary = imx_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = imx_cpu_die,arch/arm/mach-msm/platsmp.c +0
-8@@ -15,7 +15,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> @@ -42,13 +41,6 @@ static inline int get_core_count(void)static void __cpuinit msm_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ arch/arm/mach-omap2/omap-smp.c +0
-7@@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu) 4, 0, 0, 0, 0, 0);/* -* If any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * Synchronise with the boot thread. */ spin_lock (&boot_lock);arch/arm/mach-shmobile/smp-emev2.c +0
-7@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/emev2.h> #include <asm/smp_plat.h> @@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu) } -static void __cpuinit emev2_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit emev2_boot_secondary (unsigned int cpu,struct task_struct *idle) { cpu =cpu_logical_map (cpu);@@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)struct smp_operations emev2_smp_ops__initdata = { .smp_init_cpus = emev2_smp_init_cpus, .smp_prepare_cpus = emev2_smp_prepare_cpus, - .smp_secondary_init = emev2_secondary_init, .smp_boot_secondary = emev2_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = emev2_cpu_kill,arch/arm/mach-shmobile/smp-r8a7779.c +0
-7@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/r8a7779.h> #include <asm/smp_plat.h> @@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) } -static void __cpuinit r8a7779_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit r8a7779_boot_secondary (unsigned int cpu,struct task_struct *idle) {struct r8a7779_pm_ch *ch =NULL ;@@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)struct smp_operations r8a7779_smp_ops__initdata = { .smp_init_cpus = r8a7779_smp_init_cpus, .smp_prepare_cpus = r8a7779_smp_prepare_cpus, - .smp_secondary_init = r8a7779_secondary_init, .smp_boot_secondary = r8a7779_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = r8a7779_cpu_kill,arch/arm/mach-shmobile/smp-sh73a0.c +0
-7@@ -23,7 +23,6 @@#include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> -#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)return scu_get_core_count (scu_base); } -static void __cpuinit sh73a0_secondary_init (unsigned int cpu) -{ -gic_secondary_init (0 ); -} -static int __cpuinit sh73a0_boot_secondary (unsigned int cpu,struct task_struct *idle) { cpu =cpu_logical_map (cpu);@@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)struct smp_operations sh73a0_smp_ops__initdata = { .smp_init_cpus = sh73a0_smp_init_cpus, .smp_prepare_cpus = sh73a0_smp_prepare_cpus, - .smp_secondary_init = sh73a0_secondary_init, .smp_boot_secondary = sh73a0_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = sh73a0_cpu_kill,arch/arm/mach-socfpga/platsmp.c +0
-12@@ -22,7 +22,6 @@#include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_scu.h> @@ -33,16 +32,6 @@extern void __iomem *sys_manager_base_addr;extern void __iomem *rst_manager_base_addr; -static void __cpuinit socfpga_secondary_init (unsigned int cpu) -{ -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -} -static int __cpuinit socfpga_boot_secondary (unsigned int cpu,struct task_struct *idle) {int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;@@ -106,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu)struct smp_operations socfpga_smp_ops__initdata = { .smp_init_cpus = socfpga_smp_init_cpus, .smp_prepare_cpus = socfpga_smp_prepare_cpus, - .smp_secondary_init = socfpga_secondary_init, .smp_boot_secondary = socfpga_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = socfpga_cpu_die,arch/arm/mach-spear13xx/platsmp.c +0
-8@@ -15,7 +15,6 @@#include <linux/jiffies.h> #include <linux/io.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_scu.h> #include <mach/spear.h> @@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);static void __cpuinit spear13xx_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ arch/arm/mach-tegra/platsmp.c +0
-8@@ -18,7 +18,6 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <linux/clk/tegra.h> #include <asm/cacheflush.h> @@ -45,13 +44,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);static void __cpuinit tegra_secondary_init (unsigned int cpu) { -/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); -cpumask_set_cpu (cpu, &tegra_cpu_init_mask); }arch/arm/mach-ux500/platsmp.c +0
-8@@ -16,7 +16,6 @@#include <linux/device.h> #include <linux/smp.h> #include <linux/io.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -55,13 +54,6 @@ static DEFINE_SPINLOCK(boot_lock);static void __cpuinit ux500_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ arch/arm/plat-versatile/platsmp.c +0
-8@@ -14,7 +14,6 @@#include <linux/device.h> #include <linux/jiffies.h> #include <linux/smp.h> -#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);void __cpuinit versatile_secondary_init (unsigned int cpu) {/* -* if any interrupts are already enabled for the primary -* core (e.g. timer irq), then they will not have been enabled -* for us: do so -*/ -gic_secondary_init (0 ); - -/* * let the primary processor know we're out of the * pen, then head off into the C entry point */ drivers/irqchip/irq-gic.c +21
-7@@ -28,6 +28,7 @@#include <linux/module.h> #include <linux/list.h> #include <linux/smp.h> +#include <linux/cpu.h> #include <linux/cpu_pm.h> #include <linux/cpumask.h> #include <linux/io.h> @@ -678,6 +679,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,return 0 ; } +#ifdef CONFIG_SMP +static int __cpuinit gic_secondary_init (struct notifier_block *nfb, +unsigned long action,void *hcpu) +{ +if (action ==CPU_STARTING ) +gic_cpu_init (&gic_data[0 ]); +return NOTIFY_OK ; +} + +/* +* Notifier for enabling the GIC CPU interface. Set an arbitrarily high +* priority because the GIC needs to be up before the ARM generic timers. +*/ +static struct notifier_block __cpuinitdata gic_cpu_notifier = { + .notifier_call = gic_secondary_init, + .priority =100 , +}; +#endif +const struct irq_domain_ops gic_irq_domain_ops = { .map = gic_irq_domain_map, .xlate = gic_irq_domain_xlate,@@ -768,6 +788,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,#ifdef CONFIG_SMP set_smp_cross_call (gic_raise_softirq); +register_cpu_notifier (&gic_cpu_notifier);#endif set_handle_irq (gic_handle_irq);@@ -778,13 +799,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,gic_pm_init (gic); } -void __cpuinit gic_secondary_init (unsigned int gic_nr) -{ -BUG_ON (gic_nr >=MAX_GIC_NR ); - -gic_cpu_init (&gic_data[gic_nr]); -} -#ifdef CONFIG_OF static int gic_cnt__initdata =0 ;include/linux/irqchip/arm-gic.h +0
-1@@ -36,7 +36,6 @@ extern struct irq_chip gic_arch_extn;void gic_init_bases (unsigned int ,int ,void __iomem *,void __iomem *,u32 offset,struct device_node *); -void gic_secondary_init (unsigned int );void gic_cascade_irq (unsigned int gic_nr,unsigned int irq); static inline void gic_init(unsigned int nr, int start,_______________________________________________
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PATCH v2 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 27 lines · Nicolas Pitre
Quoted 16 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.Signed-off-by Catalin Marinas <[email protected]>Acked-by Stephen Warren <[email protected]>Acked-by Viresh Kumar <[email protected]>Acked-by Rob Herring <[email protected]>Acked-by Simon Horman <[email protected]>Tested-by Simon Horman <[email protected]>Acked-by Srinidhi Kasagar <[email protected]>Cc Russell King <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Kukjin Kim <[email protected]>Quoted 8 lines
Cc Sascha Hauer <[email protected]>Cc David Brown <[email protected]>Cc Bryan Huntsman <[email protected]>Cc Tony Lindgren <[email protected]>Cc Magnus Damm <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Shiraz Hashim <[email protected]>Cc Linus Walleij <[email protected]>
Quoted 1 line
Acked-by Nicolas Pitre <[email protected]>
Thanks.
Quoted 2 lines
What is your plan in terms of merge path and schedule? My mcpm series would depend on this.
I would like to get them in as soon as possible (ideally 3.9) as AArch64 needs GIC support. I can base them on Rob's branch (already in -next) and send them the same route (the arm-soc tree if Olof/Arnd are ok to take them).
Signature · 1 line
Catalin
PATCH v2 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 32 lines · Catalin Marinas
Quoted 27 lines · Nicolas Pitre
Quoted 16 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.Signed-off-by Catalin Marinas <[email protected]>Acked-by Stephen Warren <[email protected]>Acked-by Viresh Kumar <[email protected]>Acked-by Rob Herring <[email protected]>Acked-by Simon Horman <[email protected]>Tested-by Simon Horman <[email protected]>Acked-by Srinidhi Kasagar <[email protected]>Cc Russell King <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Kukjin Kim <[email protected]>Quoted 8 lines
Cc Sascha Hauer <[email protected]>Cc David Brown <[email protected]>Cc Bryan Huntsman <[email protected]>Cc Tony Lindgren <[email protected]>Cc Magnus Damm <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Shiraz Hashim <[email protected]>Cc Linus Walleij <[email protected]>Quoted 1 line
Acked-by Nicolas Pitre <[email protected]>Thanks.
Quoted 7 lines
Quoted 2 lines
What is your plan in terms of merge path and schedule? My mcpm series would depend on this.
I would like to get them in as soon as possible (ideally 3.9) as AArch64 needs GIC support. I can base them on Rob's branch (already in -next) and send them the same route (the arm-soc tree if Olof/Arnd are ok to take them).
Well... I'd prefer if my series was merged by RMK since this is mostly core ARM code. That is posing dependency issues.
I think I'll just ignore your change for now and we'll fix things up during the v3.9-rc period.
Nicolas
PATCH v2 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 11 lines · Nicolas Pitre
Quoted 4 lines · Catalin Marinas
I would like to get them in as soon as possible (ideally 3.9) as AArch64 needs GIC support. I can base them on Rob's branch (already in -next) and send them the same route (the arm-soc tree if Olof/Arnd are ok to take them).
Well... I'd prefer if my series was merged by RMK since this is mostly core ARM code. That is posing dependency issues.
I think I'll just ignore your change for now and we'll fix things up during the v3.9-rc period.
Given that the ARM kernel seems to be rather broken at the moment, that's not going to happen until the 32-bit kernel gets some loving attention to make it work again.
Our primary responsibility is not to stuff the kernel with new features as quickly as we possibly can. It's to make sure that the kernel works, and at the moment, it doesn't. I'm not talking about ancient architectures. I'm talking about platforms using ARMv6 and above - platforms with the GIC which I'd be able to test this change on.
Realview EB (MPCore)
- Various failures yesterday but now works in my tree. Fixes queued for the next -rc. (But the hardware randomly locks up during kernel boot, normally around the time when the CLCD is enabled, so this can't really be used for testing.)
OMAP4430SDP (Cortex A9)
- Fails to boot even with proper uImage addresses (no idea yet). No kernel output.
OMAP3430LDP (Cortex A8 iirc)
- Ditto. No kernel output.
I haven't tried Versatile Express yet as it has the TC2 tile on, and I don't yet a boot loader on it which is capable of TFTP (which makes it rather useless to me - I've been saying this for a time now but this is probably the first time publically.) I'm thinking about putting the CA9x4 tile back on because that's a lot more functionally useful to me than TC2.
PATCH v2 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 17 lines · Russell King - ARM Linux
Quoted 11 lines · Nicolas Pitre
Quoted 4 lines · Catalin Marinas
I would like to get them in as soon as possible (ideally 3.9) as AArch64 needs GIC support. I can base them on Rob's branch (already in -next) and send them the same route (the arm-soc tree if Olof/Arnd are ok to take them).
Well... I'd prefer if my series was merged by RMK since this is mostly core ARM code. That is posing dependency issues.
I think I'll just ignore your change for now and we'll fix things up during the v3.9-rc period.
Given that the ARM kernel seems to be rather broken at the moment, that's not going to happen until the 32-bit kernel gets some loving attention to make it work again.
Quoted 5 lines
Our primary responsibility is not to stuff the kernel with new features as quickly as we possibly can. It's to make sure that the kernel works, and at the moment, it doesn't. I'm not talking about ancient architectures. I'm talking about platforms using ARMv6 and above - platforms with the GIC which I'd be able to test this change on.
FWIW, I tested this on vexpress with CA9x4 tile with both 3.8-rc3 (Rob's branch) and latest linux-next.
If you want to test this change for longer, I'm ok to leave it for 3.10 and stick it in -next at some point (after 3.9-rc1 since there are many conflicts). I'd like however to push the other trivial code-moving patches in this series.
Signature · 1 line
Catalin
PATCH v2 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
In reply to Russell King - ARM LinuxQuoted 6 lines · Russell King - ARM Linux
I haven't tried Versatile Express yet as it has the TC2 tile on, and I don't yet a boot loader on it which is capable of TFTP (which makes it rather useless to me - I've been saying this for a time now but this is probably the first time publically.) I'm thinking about putting the CA9x4 tile back on because that's a lot more functionally useful to me than TC2.
You might be interested by this then:
http://lists.linaro.org/pipermail/linaro-dev/2012-October/014136.html
Nicolas
PATCH v2 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 9 lines · Nicolas Pitre
Quoted 6 lines · Russell King - ARM Linux
I haven't tried Versatile Express yet as it has the TC2 tile on, and I don't yet a boot loader on it which is capable of TFTP (which makes it rather useless to me - I've been saying this for a time now but this is probably the first time publically.) I'm thinking about putting the CA9x4 tile back on because that's a lot more functionally useful to me than TC2.
Quoted 3 lines
You might be interested by this then:
http://lists.linaro.org/pipermail/linaro-dev/2012-October/014136.html
Great news. Everyone has been telling me that there's no uboot for TC2, or "we think Linaro might have something but we don't really know".
PATCH v2 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 10 lines · Russell King - ARM Linux
Quoted 9 lines · Nicolas Pitre
Quoted 6 lines · Russell King - ARM Linux
I haven't tried Versatile Express yet as it has the TC2 tile on, and I don't yet a boot loader on it which is capable of TFTP (which makes it rather useless to me - I've been saying this for a time now but this is probably the first time publically.) I'm thinking about putting the CA9x4 tile back on because that's a lot more functionally useful to me than TC2.
Quoted 6 lines
Quoted 3 lines
You might be interested by this then:
http://lists.linaro.org/pipermail/linaro-dev/2012-October/014136.html
Great news. Everyone has been telling me that there's no uboot for TC2, or "we think Linaro might have something but we don't really know".
Note that I cobbled those instructions on my own and the result is not officially supported by Linaro. This is obviously not suitable for setting up products or demo systems, but for a kernel developer I think such a setup is invaluable.
Nicolas
PATCH v2 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 16 lines · Nicolas Pitre
Quoted 14 lines · Russell King - ARM Linux
Quoted 12 lines · Nicolas Pitre
Quoted 6 lines · Russell King - ARM Linux
I haven't tried Versatile Express yet as it has the TC2 tile on, and I don't yet a boot loader on it which is capable of TFTP (which makes it rather useless to me - I've been saying this for a time now but this is probably the first time publically.) I'm thinking about putting the CA9x4 tile back on because that's a lot more functionally useful to me than TC2.
You might be interested by this then:
http://lists.linaro.org/pipermail/linaro-dev/2012-October/014136.html
Quoted 7 lines
Quoted 2 lines
Great news. Everyone has been telling me that there's no uboot for TC2, or "we think Linaro might have something but we don't really know".
Note that I cobbled those instructions on my own and the result is not officially supported by Linaro. This is obviously not suitable for setting up products or demo systems, but for a kernel developer I think such a setup is invaluable.
If I remember correctly, you will also only get 1GB of RAM available not the 2GB most TC2 boards have. (I did take a quick look at hacking U-Boot to get around that but couldn't get anything to work.)
Signature · 1 line
Tixy
PATCH v2 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
Quoted 20 lines · Jon Medhurst (Tixy)
Quoted 19 lines · Nicolas Pitre
Quoted 16 lines · Russell King - ARM Linux
Quoted 9 lines · Nicolas Pitre
Quoted 6 lines · Russell King - ARM Linux
I haven't tried Versatile Express yet as it has the TC2 tile on, and I don't yet a boot loader on it which is capable of TFTP (which makes it rather useless to me - I've been saying this for a time now but this is probably the first time publically.) I'm thinking about putting the CA9x4 tile back on because that's a lot more functionally useful to me than TC2.
Quoted 3 lines
You might be interested by this then:
http://lists.linaro.org/pipermail/linaro-dev/2012-October/014136.html
Great news. Everyone has been telling me that there's no uboot for TC2, or "we think Linaro might have something but we don't really know".
Quoted 8 lines
Quoted 4 lines
Note that I cobbled those instructions on my own and the result is not officially supported by Linaro. This is obviously not suitable for setting up products or demo systems, but for a kernel developer I think such a setup is invaluable.
If I remember correctly, you will also only get 1GB of RAM available not the 2GB most TC2 boards have. (I did take a quick look at hacking U-Boot to get around that but couldn't get anything to work.)
I simply added "mem=2048m at 0x80000000" to my kernel cmdline.
Nicolas
PATCH v2 4/4 irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
In reply to Catalin MarinasHi Catalina,
Quoted 47 lines · Catalin Marinas
All the calls to
gic_secondary_init()pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code.Signed-off-by Catalin Marinas <[email protected]>Acked-by Stephen Warren <[email protected]>Acked-by Viresh Kumar <[email protected]>Acked-by Rob Herring <[email protected]>Acked-by Simon Horman <[email protected]>Tested-by Simon Horman <[email protected]>Acked-by Srinidhi Kasagar <[email protected]>Cc Russell King <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Kukjin Kim <[email protected]>Cc Sascha Hauer <[email protected]>Cc David Brown <[email protected]>Cc Bryan Huntsman <[email protected]>Cc Tony Lindgren <[email protected]>Cc Magnus Damm <[email protected]>Cc Dinh Nguyen <[email protected]>Cc Shiraz Hashim <[email protected]>Cc Linus Walleij <[email protected]>--- arch/arm/mach-exynos/platsmp.c | 8 -------- arch/arm/mach-highbank/platsmp.c | 7 ------- arch/arm/mach-imx/platsmp.c | 12 ------------ arch/arm/mach-msm/platsmp.c | 8 -------- arch/arm/mach-omap2/omap-smp.c | 7 ------- arch/arm/mach-shmobile/smp-emev2.c | 7 ------- arch/arm/mach-shmobile/smp-r8a7779.c | 7 ------- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ------- arch/arm/mach-socfpga/platsmp.c | 12 ------------ arch/arm/mach-spear13xx/platsmp.c | 8 -------- arch/arm/mach-tegra/platsmp.c | 8 -------- arch/arm/mach-ux500/platsmp.c | 8 -------- arch/arm/plat-versatile/platsmp.c | 8 -------- drivers/irqchip/irq-gic.c | 28 +++++++++++++++++++++------- include/linux/irqchip/arm-gic.h | 1 - 15 files changed, 21 insertions(+), 115 deletions(-)arch/arm/mach-exynos/platsmp.c +0
-0
arch/arm/mach-exynos/platsmp.c line 22
Quoted 3 lines
arch/arm/mach-exynos/platsmp.c +0
-0@@ -20,7 +20,6 @@#include <linux/jiffies.h> #include <linux/smp.h>
For mach-socfpga:
Thanks,
Dinh
v2 cover Preparatory GIC patches for arm64 support
In reply to Catalin MarinasOlof, Arnd,
Quoted 3 lines · Catalin Marinas
That's the second version of the GIC clean-up patches to support arm64. The only change from v1 is that the second patch (
chained_irq.h) also coversdrivers/gpioanddrivers/pinctrl(#include change).
Are you ok to merge this series via the arm-soc tree for 3.9-rc1? There are no complaints so far (only acks ;). This would allow me to push GIC support for arm64.
Thanks,
Catalin
Stats below for reference:
Quoted 44 lines
Catalin Marinas (4):
arm: Move theset_handle_irqandhandle_arch_irqdeclarations to
asm/irq.h
arm: Movechained_irq_(enter|exit)to a generic file
irqchip: gic: Callhandle_bad_irq()directly
irqchip: gic: Perform thegic_secondary_init()call via CPU notifierarch/arm/include/asm/irq.h | 5 +++ arch/arm/include/asm/mach/irq.h | 36 -------------------- arch/arm/mach-at91/gpio.c | 3 +- arch/arm/mach-exynos/common.c | 1 + arch/arm/mach-exynos/platsmp.c | 8 ----- arch/arm/mach-highbank/platsmp.c | 7 ---- arch/arm/mach-imx/platsmp.c | 12 ------- arch/arm/mach-msm/platsmp.c | 8 ----- arch/arm/mach-omap2/omap-smp.c | 7 ---- arch/arm/mach-shmobile/smp-emev2.c | 7 ---- arch/arm/mach-shmobile/smp-r8a7779.c | 7 ---- arch/arm/mach-shmobile/smp-sh73a0.c | 7 ---- arch/arm/mach-socfpga/platsmp.c | 12 ------- arch/arm/mach-spear13xx/platsmp.c | 8 ----- arch/arm/mach-tegra/platsmp.c | 8 ----- arch/arm/mach-ux500/platsmp.c | 8 ----- arch/arm/plat-samsung/irq-vic-timer.c | 3 +- arch/arm/plat-samsung/s5p-irq-gpioint.c | 3 +- arch/arm/plat-versatile/platsmp.c | 8 ----- drivers/gpio/gpio-msm-v2.c | 3 +- drivers/gpio/gpio-mxc.c | 2 +- drivers/gpio/gpio-omap.c | 3 +- drivers/gpio/gpio-pl061.c | 2 +- drivers/gpio/gpio-pxa.c | 3 +- drivers/gpio/gpio-tegra.c | 3 +- drivers/irqchip/irq-gic.c | 32 +++++++++++++----- drivers/irqchip/irq-vic.c | 2 +- drivers/pinctrl/pinctrl-at91.c | 3 +- drivers/pinctrl/pinctrl-exynos.c | 3 +- drivers/pinctrl/pinctrl-nomadik.c | 2 +- drivers/pinctrl/pinctrl-sirf.c | 2 +- drivers/pinctrl/spear/pinctrl-plgpio.c | 2 +- drivers/staging/imx-drm/ipu-v3/ipu-common.c | 2 +- include/linux/irqchip/arm-gic.h | 1 - include/linux/irqchip/chained_irq.h | 52 +++++++++++++++++++++++++++++ 35 files changed, 97 insertions(+), 178 deletions(-) create mode 100644 include/linux/irqchip/chained_irq.h
v2 cover Preparatory GIC patches for arm64 support
Quoted 10 lines · Catalin Marinas
Olof, Arnd,
Quoted 3 lines · Catalin Marinas
That's the second version of the GIC clean-up patches to support arm64. The only change from v1 is that the second patch (
chained_irq.h) also coversdrivers/gpioanddrivers/pinctrl(#include change).Are you ok to merge this series via the arm-soc tree for 3.9-rc1? There are no complaints so far (only acks ;). This would allow me to push GIC support for arm64.
So I don't exist anymore to you?
Catalin, it's already been suggested to you that this series is more core ARM stuff than SoC stuff, and it's also been suggested that you merge this through my tree.
No, I guess this figures after all your excessively negative replies on all of my comments during the review of ARM64.
v2 cover Preparatory GIC patches for arm64 support
Quoted 11 lines · Russell King - ARM Linux
Quoted 8 lines · Catalin Marinas
Quoted 3 lines · Catalin Marinas
That's the second version of the GIC clean-up patches to support arm64. The only change from v1 is that the second patch (
chained_irq.h) also coversdrivers/gpioanddrivers/pinctrl(#include change).Are you ok to merge this series via the arm-soc tree for 3.9-rc1? There are no complaints so far (only acks ;). This would allow me to push GIC support for arm64.
So I don't exist anymore to you?
You do ;) and you've been cc'ed on these patches. Just wasn't sure you care about patches that have 'arm64' in the cover email ;).
Since Rob's series went through the arm-soc, I consider that further changes should go the same route as there is a dependency and I'd like to get them merged sooner. These patches touch primarily SoC code, apart from some trivial code moving and the CPU notifier in irq-gic.c (you are the original author of this driver) and I'm ok if you want to merge it.
I really don't mind if you or Olof merge the whole series as long as it gets upstream at some point. As you expressed an opinion on these patches and you want to merge them, they'll have to wait until after 3.9-rc1 for Rob's patches to get in.
Quoted 3 lines
Catalin, it's already been suggested to you that this series is more core ARM stuff than SoC stuff, and it's also been suggested that you merge this through my tree.
No, it hasn't. Just Nico saying that he'd prefer *his* series was merged by RMK (and I agree). A way to sort the dependency issue for Nico is to at least push some of this series in 3.9-rc1. Otherwise we just postpone the dependency issue.
Quoted 2 lines
No, I guess this figures after all your excessively negative replies on all of my comments during the review of ARM64.
It's all relative - negative reply to negative reply would make it positive ;).
Signature · 1 line
Catalin