Add TI814x EVM Support

index ab31326..b186b32 100644
@@ -141,11 +141,11 @@ int arch_misc_init(void)
 {
 #ifdef CONFIG_AM335X_USB0
 	musb_register(&otg0_plat, &otg0_board_data,
-		(void *)AM335X_USB0_OTG_BASE);
+		(void *)USB0_OTG_BASE);
 #endif
 #ifdef CONFIG_AM335X_USB1
 	musb_register(&otg1_plat, &otg1_board_data,
-		(void *)AM335X_USB1_OTG_BASE);
+		(void *)USB1_OTG_BASE);
 #endif
 	return 0;
 }

index 6dd3296..7016e25 100644
@@ -84,14 +84,14 @@
 #define GPMC_BASE			0x50000000
 
 /* CPSW Config space */
-#define AM335X_CPSW_BASE		0x4A100000
-#define AM335X_CPSW_MDIO_BASE		0x4A101000
+#define CPSW_BASE			0x4A100000
+#define CPSW_MDIO_BASE			0x4A101000
 
 /* RTC base address */
-#define AM335X_RTC_BASE			0x44E3E000
+#define RTC_BASE			0x44E3E000
 
 /* OTG */
-#define AM335X_USB0_OTG_BASE		0x47401000
-#define AM335X_USB1_OTG_BASE		0x47401800
+#define USB0_OTG_BASE			0x47401000
+#define USB1_OTG_BASE			0x47401800
 
 #endif /* __AM33XX_HARDWARE_H */

index 55bc018..471725a 100644
@@ -61,7 +61,7 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
 static void rtc32k_enable(void)
 {
-	struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
 	/*
 	 * Unlock the RTC's registers.  For more details please see the

@@ -199,8 +199,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 };
 
 static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= AM335X_CPSW_MDIO_BASE,
-	.cpsw_base		= AM335X_CPSW_BASE,
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
 	.mdio_div		= 0xff,
 	.channels		= 8,
 	.cpdma_reg_ofs		= 0x800,

index 48e6896..0948889 100644
@@ -134,7 +134,7 @@ static int read_eeprom(void)
 
 static void rtc32k_enable(void)
 {
-	struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
 	/*
 	 * Unlock the RTC's registers.  For more details please see the

@@ -411,8 +411,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 };
 
 static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= AM335X_CPSW_MDIO_BASE,
-	.cpsw_base		= AM335X_CPSW_BASE,
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
 	.mdio_div		= 0xff,
 	.channels		= 8,
 	.cpdma_reg_ofs		= 0x800,

index fd9fc4a..4b771c8 100644
@@ -24,15 +24,20 @@ http://www.ti.com/
 /**
  * Base address for EMIF instances
  */
-static struct emif_reg_struct *emif_reg = {
-				(struct emif_reg_struct *)EMIF4_0_CFG_BASE};
+static struct emif_reg_struct *emif_reg[2] = {
+				(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
+				(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
 
 /**
- * Base address for DDR instance
+ * Base addresses for DDR PHY cmd/data regs
  */
-static struct ddr_regs *ddr_reg[2] = {
-				(struct ddr_regs *)DDR_PHY_BASE_ADDR,
-				(struct ddr_regs *)DDR_PHY_BASE_ADDR2};
+static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
+				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
+				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
+
+static struct ddr_data_regs *ddr_data_reg[2] = {
+				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
+				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
 
 /**
  * Base address for ddr io control instances

@@ -43,70 +48,84 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
 /**
  * Configure SDRAM
  */
-void config_sdram(const struct emif_regs *regs)
+void config_sdram(const struct emif_regs *regs, int nr)
 {
-	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
-	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 	if (regs->zq_config){
-		writel(regs->zq_config, &emif_reg->emif_zq_config);
+		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 	}
-	writel(regs->sdram_config, &emif_reg->emif_sdram_config);
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 }
 
 /**
  * Set SDRAM timings
  */
-void set_sdram_timings(const struct emif_regs *regs)
+void set_sdram_timings(const struct emif_regs *regs, int nr)
 {
-	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
-	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
-	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
-	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
-	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
-	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
+	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
+	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
+	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
+	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 }
 
 /**
  * Configure DDR PHY
  */
-void config_ddr_phy(const struct emif_regs *regs)
+void config_ddr_phy(const struct emif_regs *regs, int nr)
 {
-	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
+	writel(regs->emif_ddr_phy_ctlr_1,
+		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1,
+		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 }
 
 /**
  * Configure DDR CMD control registers
  */
-void config_cmd_ctrl(const struct cmd_control *cmd)
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 {
-	writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
-	writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
-	writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
+	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
+	writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
+	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 
-	writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
-	writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
-	writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
+	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
+	writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
+	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 
-	writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
-	writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
-	writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
+	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
+	writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
+	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 }
 
 /**
  * Configure DDR DATA registers
  */
-void config_ddr_data(int macrono, const struct ddr_data *data)
+void config_ddr_data(const struct ddr_data *data, int nr)
 {
-	writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
-	writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
-	writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
-	writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
-	writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
-	writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
-	writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
-	writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
+	int i;
+
+	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
+		writel(data->datardsratio0,
+			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
+		writel(data->datawdsratio0,
+			&(ddr_data_reg[nr]+i)->dt0wdsratio0);
+		writel(data->datawiratio0,
+			&(ddr_data_reg[nr]+i)->dt0wiratio0);
+		writel(data->datagiratio0,
+			&(ddr_data_reg[nr]+i)->dt0giratio0);
+		writel(data->datafwsratio0,
+			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
+		writel(data->datawrsratio0,
+			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
+		writel(data->datauserank0delay,
+			&(ddr_data_reg[nr]+i)->dt0rdelays0);
+		writel(data->datadldiff0,
+			&(ddr_data_reg[nr]+i)->dt0dldiff0);
+	}
 }
 
 void config_io_ctrl(unsigned long val)

index 01e3a52..76459d8 100644
@@ -44,44 +44,48 @@ void dram_init_banksize(void)
 
 
 #ifdef CONFIG_SPL_BUILD
-static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
+static struct vtp_reg *vtpreg[2] = {
+				(struct vtp_reg *)VTP0_CTRL_ADDR,
+				(struct vtp_reg *)VTP1_CTRL_ADDR};
+#ifdef CONFIG_AM33XX
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+#endif
 
-static void config_vtp(void)
+static void config_vtp(int nr)
 {
-	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
-			&vtpreg->vtp0ctrlreg);
-	writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
-			&vtpreg->vtp0ctrlreg);
-	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
-			&vtpreg->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
+			&vtpreg[nr]->vtp0ctrlreg);
 
 	/* Poll for READY */
-	while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
+	while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
 			VTP_CTRL_READY)
 		;
 }
 
 void config_ddr(unsigned int pll, unsigned int ioctrl,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
-		const struct emif_regs *regs)
+		const struct emif_regs *regs, int nr)
 {
 	enable_emif_clocks();
 	ddr_pll_config(pll);
-	config_vtp();
-	config_cmd_ctrl(ctrl);
-
-	config_ddr_data(0, data);
-	config_ddr_data(1, data);
+	config_vtp(nr);
+	config_cmd_ctrl(ctrl, nr);
 
+	config_ddr_data(data, nr);
+#ifdef CONFIG_AM33XX
 	config_io_ctrl(ioctrl);
 
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+#endif
 
 	/* Program EMIF instance */
-	config_ddr_phy(regs);
-	set_sdram_timings(regs);
-	config_sdram(regs);
+	config_ddr_phy(regs, nr);
+	set_sdram_timings(regs, nr);
+	config_sdram(regs, nr);
 }
 #endif

81 lines not on this page · raw message

index 7016e25..24a9b8d 100644
@@ -3,7 +3,7 @@
  *
  * hardware specific header
  *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

@@ -20,6 +20,11 @@
 #define __AM33XX_HARDWARE_H
 
 #include <asm/arch/omap.h>
+#ifdef CONFIG_AM33XX
+#include <asm/arch/hardware_am33xx.h>
+#elif defined(CONFIG_TI814X)
+#include <asm/arch/hardware_ti814x.h>
+#endif
 
 /* Module base addresses */
 #define UART0_BASE			0x44E09000

@@ -66,13 +71,13 @@
 #define PRM_DEVICE			0x44E00F00
 
 /* VTP Base address */
-#define VTP0_CTRL_ADDR			0x44E10E0C
+#define VTP1_CTRL_ADDR			0x48140E10
 
 /* DDR Base address */
 #define DDR_CTRL_ADDR			0x44E10E04
 #define DDR_CONTROL_BASE_ADDR		0x44E11404
-#define DDR_PHY_BASE_ADDR		0x44E12000
-#define DDR_PHY_BASE_ADDR2		0x44E120A4
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
 
 /* UART */
 #define DEFAULT_UART_BASE		UART0_BASE

new file mode 100644
index 0000000..7a4070c
@@ -0,0 +1,30 @@
+/*
+ * hardware_am33xx.h
+ *
+ * AM33xx hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AM33XX_HARDWARE_AM33XX_H
+#define __AM33XX_HARDWARE_AM33XX_H
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR			0x44E10E0C
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR		0x44E12000
+#define DDR_PHY_DATA_ADDR		0x44E120C8
+#define DDR_DATA_REGS_NR		2
+
+#endif /* __AM33XX_HARDWARE_AM33XX_H */

new file mode 100644
index 0000000..af7d1d8
@@ -0,0 +1,30 @@
+/*
+ * hardware_ti814x.h
+ *
+ * TI814x hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AM33XX_HARDWARE_TI814X_H
+#define __AM33XX_HARDWARE_TI814X_H
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR			0x48140E0C
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR		0x47C0C400
+#define DDR_PHY_DATA_ADDR		0x47C0C4C8
+#define DDR_DATA_REGS_NR		4
+
+#endif /* __AM33XX_HARDWARE_TI814X_H */

index 471725a..1708ac2 100644
@@ -159,7 +159,7 @@ void s_init(void)
 	enable_board_pin_mux();
 
 	config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
-			&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+			&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 #endif
 }
 

index 0948889..930c886 100644
@@ -343,13 +343,13 @@ void s_init(void)
 
 	if (board_is_evm_sk() || board_is_bone_lt())
 		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
-			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 	else if (board_is_evm_15_or_later())
 		config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
-			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data);
+			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 	else
 		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
-			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
+			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 #endif
 }
 

similarity index 91%
rename from arch/arm/cpu/armv7/am33xx/clock.c
rename to arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index d7d98d1..65cb9f8 100644
@@ -1,9 +1,9 @@
 /*
- * clock.c
+ * clock_am33xx.c
  *
  * clocks for AM33XX based boards
  *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

@@ -42,6 +42,36 @@
 #define CPGMAC0_IDLE		0x30000
 #define DPLL_CLKDCOLDO_GATE_CTRL        0x300
 
+#define OSC	(V_OSCK/1000000)
+
+/* MAIN PLL Fdll = 550 MHZ, */
+#define MPUPLL_M	550
+#define MPUPLL_N	(OSC-1)
+#define MPUPLL_M2	1
+
+/* Core PLL Fdll = 1 GHZ, */
+#define COREPLL_M	1000
+#define COREPLL_N	(OSC-1)
+
+#define COREPLL_M4	10	/* CORE_CLKOUTM4 = 200 MHZ */
+#define COREPLL_M5	8	/* CORE_CLKOUTM5 = 250 MHZ */
+#define COREPLL_M6	4	/* CORE_CLKOUTM6 = 500 MHZ */
+
+/*
+ * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
+ * frequency needs to be set to 960 MHZ. Hence,
+ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
+ */
+#define PERPLL_M	960
+#define PERPLL_N	(OSC-1)
+#define PERPLL_M2	5
+
+/* DDR Freq is 266 MHZ for now */
+/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
+#define DDRPLL_M	266
+#define DDRPLL_N	(OSC-1)
+#define DDRPLL_M2	1
+
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;

406 lines not on this page · raw message

index 872ff82..ecb5901 100644
@@ -3,7 +3,7 @@
  *
  * clock header
  *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

index d748dd2..f089b41 100644
@@ -3,7 +3,7 @@
  *
  * AM33xx clock define
  *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

@@ -19,37 +19,8 @@
 #ifndef _CLOCKS_AM33XX_H_
 #define _CLOCKS_AM33XX_H_
 
-#define OSC	(V_OSCK/1000000)
-
-/* MAIN PLL Fdll = 550 MHZ, */
-#define MPUPLL_M	550
-#define MPUPLL_N	(OSC-1)
-#define MPUPLL_M2	1
-
-/* Core PLL Fdll = 1 GHZ, */
-#define COREPLL_M	1000
-#define COREPLL_N	(OSC-1)
-
-#define COREPLL_M4	10	/* CORE_CLKOUTM4 = 200 MHZ */
-#define COREPLL_M5	8	/* CORE_CLKOUTM5 = 250 MHZ */
-#define COREPLL_M6	4	/* CORE_CLKOUTM6 = 500 MHZ */
-
-/*
- * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
- * frequency needs to be set to 960 MHZ. Hence,
- * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
- */
-#define PERPLL_M	960
-#define PERPLL_N	(OSC-1)
-#define PERPLL_M2	5
-
-/* DDR Freq is 266 MHZ for now */
-/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
-#define DDRPLL_M	266
-#define DDRPLL_N	(OSC-1)
-#define DDRPLL_M2	1
-
 extern void pll_init(void);
 extern void enable_emif_clocks(void);
+extern void enable_dmm_clocks(void);
 
 #endif	/* endif _CLOCKS_AM33XX_H_ */

index 460ac1c..1c6b65f 100644
@@ -1,7 +1,7 @@
 /*
  * mux.h
  *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

@@ -19,234 +19,15 @@
 #include <common.h>
 #include <asm/io.h>
 
-#define MUX_CFG(value, offset)	\
-	__raw_writel(value, (CTRL_BASE + offset));
-
-/* PAD Control Fields */
-#define SLEWCTRL	(0x1 << 6)
-#define RXACTIVE	(0x1 << 5)
-#define PULLDOWN_EN	(0x0 << 4) /* Pull Down Selection */
-#define PULLUP_EN	(0x1 << 4) /* Pull Up Selection */
-#define PULLUDEN	(0x0 << 3) /* Pull up enabled */
-#define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
-#define MODE(val)	val	/* used for Readability */
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
-	int gpmc_ad0;
-	int gpmc_ad1;
-	int gpmc_ad2;
-	int gpmc_ad3;
-	int gpmc_ad4;
-	int gpmc_ad5;
-	int gpmc_ad6;
-	int gpmc_ad7;
-	int gpmc_ad8;
-	int gpmc_ad9;
-	int gpmc_ad10;
-	int gpmc_ad11;
-	int gpmc_ad12;
-	int gpmc_ad13;
-	int gpmc_ad14;
-	int gpmc_ad15;
-	int gpmc_a0;
-	int gpmc_a1;
-	int gpmc_a2;
-	int gpmc_a3;
-	int gpmc_a4;
-	int gpmc_a5;
-	int gpmc_a6;
-	int gpmc_a7;
-	int gpmc_a8;
-	int gpmc_a9;
-	int gpmc_a10;
-	int gpmc_a11;
-	int gpmc_wait0;
-	int gpmc_wpn;
-	int gpmc_be1n;
-	int gpmc_csn0;
-	int gpmc_csn1;
-	int gpmc_csn2;
-	int gpmc_csn3;
-	int gpmc_clk;
-	int gpmc_advn_ale;
-	int gpmc_oen_ren;
-	int gpmc_wen;
-	int gpmc_be0n_cle;
-	int lcd_data0;
-	int lcd_data1;
-	int lcd_data2;
-	int lcd_data3;
-	int lcd_data4;
-	int lcd_data5;
-	int lcd_data6;
-	int lcd_data7;
-	int lcd_data8;
-	int lcd_data9;
-	int lcd_data10;
-	int lcd_data11;
-	int lcd_data12;
-	int lcd_data13;
-	int lcd_data14;
-	int lcd_data15;
-	int lcd_vsync;
-	int lcd_hsync;
-	int lcd_pclk;
-	int lcd_ac_bias_en;
-	int mmc0_dat3;
-	int mmc0_dat2;
-	int mmc0_dat1;
-	int mmc0_dat0;
-	int mmc0_clk;
-	int mmc0_cmd;
-	int mii1_col;
-	int mii1_crs;
-	int mii1_rxerr;
-	int mii1_txen;
-	int mii1_rxdv;
-	int mii1_txd3;
-	int mii1_txd2;
-	int mii1_txd1;
-	int mii1_txd0;
-	int mii1_txclk;
-	int mii1_rxclk;
-	int mii1_rxd3;
-	int mii1_rxd2;
-	int mii1_rxd1;
-	int mii1_rxd0;
-	int rmii1_refclk;
-	int mdio_data;
-	int mdio_clk;
-	int spi0_sclk;
-	int spi0_d0;
-	int spi0_d1;
-	int spi0_cs0;
-	int spi0_cs1;
-	int ecap0_in_pwm0_out;
-	int uart0_ctsn;
-	int uart0_rtsn;
-	int uart0_rxd;
-	int uart0_txd;
-	int uart1_ctsn;
-	int uart1_rtsn;
-	int uart1_rxd;
-	int uart1_txd;
-	int i2c0_sda;
-	int i2c0_scl;
-	int mcasp0_aclkx;
-	int mcasp0_fsx;
-	int mcasp0_axr0;
-	int mcasp0_ahclkr;
-	int mcasp0_aclkr;
-	int mcasp0_fsr;
-	int mcasp0_axr1;
-	int mcasp0_ahclkx;
-	int xdma_event_intr0;
-	int xdma_event_intr1;
-	int nresetin_out;
-	int porz;
-	int nnmi;
-	int osc0_in;
-	int osc0_out;
-	int rsvd1;
-	int tms;
-	int tdi;
-	int tdo;
-	int tck;
-	int ntrst;
-	int emu0;
-	int emu1;
-	int osc1_in;
-	int osc1_out;
-	int pmic_power_en;
-	int rtc_porz;
-	int rsvd2;
-	int ext_wakeup;
-	int enz_kaldo_1p8v;
-	int usb0_dm;
-	int usb0_dp;
-	int usb0_ce;
-	int usb0_id;
-	int usb0_vbus;
-	int usb0_drvvbus;
-	int usb1_dm;
-	int usb1_dp;
-	int usb1_ce;
-	int usb1_id;
-	int usb1_vbus;
-	int usb1_drvvbus;
-	int ddr_resetn;
-	int ddr_csn0;
-	int ddr_cke;
-	int ddr_ck;
-	int ddr_nck;
-	int ddr_casn;
-	int ddr_rasn;
-	int ddr_wen;
-	int ddr_ba0;
-	int ddr_ba1;
-	int ddr_ba2;
-	int ddr_a0;
-	int ddr_a1;
-	int ddr_a2;
-	int ddr_a3;
-	int ddr_a4;
-	int ddr_a5;
-	int ddr_a6;
-	int ddr_a7;
-	int ddr_a8;
-	int ddr_a9;
-	int ddr_a10;
-	int ddr_a11;
-	int ddr_a12;
-	int ddr_a13;
-	int ddr_a14;
-	int ddr_a15;
-	int ddr_odt;
-	int ddr_d0;
-	int ddr_d1;
-	int ddr_d2;
-	int ddr_d3;
-	int ddr_d4;
-	int ddr_d5;
-	int ddr_d6;
-	int ddr_d7;
-	int ddr_d8;
-	int ddr_d9;
-	int ddr_d10;
-	int ddr_d11;
-	int ddr_d12;
-	int ddr_d13;
-	int ddr_d14;
-	int ddr_d15;
-	int ddr_dqm0;
-	int ddr_dqm1;
-	int ddr_dqs0;
-	int ddr_dqsn0;
-	int ddr_dqs1;
-	int ddr_dqsn1;
-	int ddr_vref;
-	int ddr_vtp;
-	int ddr_strben0;
-	int ddr_strben1;
-	int ain7;
-	int ain6;
-	int ain5;
-	int ain4;
-	int ain3;
-	int ain2;
-	int ain1;
-	int ain0;
-	int vrefp;
-	int vrefn;
-};
+#ifdef CONFIG_AM33XX
+#include <asm/arch/mux_am33xx.h>
+#elif defined(CONFIG_TI814X)
+#include <asm/arch/mux_ti814x.h>
+#endif
 
 struct module_pin_mux {
 	short reg_offset;
-	unsigned char val;
+	unsigned int val;
 };
 
 /* Pad control register offset */

@@ -259,4 +40,4 @@ struct module_pin_mux {
  */
 void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
 
-#endif
+#endif /* endif _MUX_H */

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index 507b618..402127c 100644
@@ -98,6 +98,9 @@ int print_cpuinfo(void)
 	case AM335X:
 		cpu_s = "AM335X";
 		break;
+	case TI81XX:
+		cpu_s = "TI81XX";
+		break;
 	default:
 		cpu_s = "Unknown cpu type";
 		break;

index 16e8a80..3d3a7c8 100644
@@ -42,9 +42,10 @@
 #define HS_DEVICE			0x2
 #define GP_DEVICE			0x3
 
-/* cpu-id for AM33XX family */
+/* cpu-id for AM33XX and TI81XX family */
 #define AM335X				0xB944
-#define DEVICE_ID			0x44E10600
+#define TI81XX				0xB81E
+#define DEVICE_ID			(CTRL_BASE + 0x0600)
 
 /* This gives the status of the boot mode pins on the evm */
 #define SYSBOOT_MASK			(BIT(0) | BIT(1) | BIT(2)\

@@ -52,9 +53,11 @@
 
 /* Reset control */
 #ifdef CONFIG_AM33XX
-#define PRM_RSTCTRL			0x44E00F00
-#define PRM_RSTST			0x44E00F08
+#define PRM_RSTCTRL			(PRCM_BASE + 0x0F00)
+#elif defined(CONFIG_TI814X)
+#define PRM_RSTCTRL			(PRCM_BASE + 0x00A0)
 #endif
+#define PRM_RSTST			(PRM_RSTCTRL + 8)
 #define PRM_RSTCTRL_RESET		0x01
 #define PRM_RSTST_WARM_RESET_MASK	0x232
 

index 24a9b8d..5a27f9c 100644
@@ -19,6 +19,7 @@
 #ifndef __AM33XX_HARDWARE_H
 #define __AM33XX_HARDWARE_H
 
+#include <config.h>
 #include <asm/arch/omap.h>
 #ifdef CONFIG_AM33XX
 #include <asm/arch/hardware_am33xx.h>

@@ -26,8 +27,9 @@
 #include <asm/arch/hardware_ti814x.h>
 #endif
 
-/* Module base addresses */
-#define UART0_BASE			0x44E09000
+/*
+ * Common hardware definitions
+ */
 
 /* DM Timer base addresses */
 #define DM_TIMER0_BASE			0x4802C000

@@ -42,21 +44,10 @@
 /* GPIO Base address */
 #define GPIO0_BASE			0x48032000
 #define GPIO1_BASE			0x4804C000
-#define GPIO2_BASE			0x481AC000
 
 /* BCH Error Location Module */
 #define ELM_BASE			0x48080000
 
-/* Watchdog Timer */
-#define WDT_BASE			0x44E35000
-
-/* Control Module Base Address */
-#define CTRL_BASE			0x44E10000
-#define CTRL_DEVICE_BASE		0x44E10600
-
-/* PRCM Base Address */
-#define PRCM_BASE			0x44E00000
-
 /* EMIF Base address */
 #define EMIF4_0_CFG_BASE		0x4C000000
 #define EMIF4_1_CFG_BASE		0x4D000000

@@ -90,10 +81,6 @@
 
 /* CPSW Config space */
 #define CPSW_BASE			0x4A100000
-#define CPSW_MDIO_BASE			0x4A101000
-
-/* RTC base address */
-#define RTC_BASE			0x44E3E000
 
 /* OTG */
 #define USB0_OTG_BASE			0x47401000

index 7a4070c..fa02f19 100644
@@ -19,6 +19,24 @@
 #ifndef __AM33XX_HARDWARE_AM33XX_H
 #define __AM33XX_HARDWARE_AM33XX_H
 
+/* Module base addresses */
+
+/* UART Base Address */
+#define UART0_BASE			0x44E09000
+
+/* GPIO Base address */
+#define GPIO2_BASE			0x481AC000
+
+/* Watchdog Timer */
+#define WDT_BASE			0x44E35000
+
+/* Control Module Base Address */
+#define CTRL_BASE			0x44E10000
+#define CTRL_DEVICE_BASE		0x44E10600
+
+/* PRCM Base Address */
+#define PRCM_BASE			0x44E00000
+
 /* VTP Base address */
 #define VTP0_CTRL_ADDR			0x44E10E0C
 

@@ -27,4 +45,10 @@
 #define DDR_PHY_DATA_ADDR		0x44E120C8
 #define DDR_DATA_REGS_NR		2
 
+/* CPSW Config space */
+#define CPSW_MDIO_BASE			0x4A101000
+
+/* RTC base address */
+#define RTC_BASE			0x44E3E000
+
 #endif /* __AM33XX_HARDWARE_AM33XX_H */

index af7d1d8..a950ac3 100644
@@ -19,6 +19,23 @@
 #ifndef __AM33XX_HARDWARE_TI814X_H
 #define __AM33XX_HARDWARE_TI814X_H
 
+/* Module base addresses */
+
+/* UART Base Address */
+#define UART0_BASE			0x48020000
+
+/* Watchdog Timer */
+#define WDT_BASE			0x481C7000
+
+/* Control Module Base Address */
+#define CTRL_BASE			0x48140000
+
+/* PRCM Base Address */
+#define PRCM_BASE			0x48180000
+
+/* PLL Subsystem Base Address */
+#define PLL_SUBSYS_BASE			0x481C5000
+
 /* VTP Base address */
 #define VTP0_CTRL_ADDR			0x48140E0C
 

@@ -27,4 +44,10 @@
 #define DDR_PHY_DATA_ADDR		0x47C0C4C8
 #define DDR_DATA_REGS_NR		4
 
+/* CPSW Config space */
+#define CPSW_MDIO_BASE			0x4A100800
+
+/* RTC base address */
+#define RTC_BASE			0x480C0000
+
 #endif /* __AM33XX_HARDWARE_TI814X_H */

index 850f8a5..d28f9a8 100644
@@ -28,8 +28,13 @@
  * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
  * at 0x40304000(EMU base) so that our code works for both EMU and GP
  */
+#ifdef CONFIG_AM33XX
 #define NON_SECURE_SRAM_START	0x40304000
 #define NON_SECURE_SRAM_END	0x4030E000
+#elif defined(CONFIG_TI814X)
+#define NON_SECURE_SRAM_START	0x40300000
+#define NON_SECURE_SRAM_END	0x40320000
+#endif
 
 /* ROM code defines */
 /* Boot device */

index 644ff35..9b5fe9e 100644
@@ -25,8 +25,13 @@
 
 #define BOOT_DEVICE_XIP       	2
 #define BOOT_DEVICE_NAND	5
+#ifdef CONFIG_AM33XX
 #define BOOT_DEVICE_MMC1	8
 #define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
+#elif defined(CONFIG_TI814X)
+#define BOOT_DEVICE_MMC1	9
+#define BOOT_DEVICE_MMC2	8	/* ROM only supports 2nd instance */
+#endif
 #define BOOT_DEVICE_SPI		11
 #define BOOT_DEVICE_UART	65
 #define BOOT_DEVICE_CPGMAC	70

index 76459d8..aa84e96 100644
@@ -44,6 +44,8 @@ void dram_init_banksize(void)
 
 
 #ifdef CONFIG_SPL_BUILD
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+				(struct dmm_lisa_map_regs *)DMM_BASE;
 static struct vtp_reg *vtpreg[2] = {
 				(struct vtp_reg *)VTP0_CTRL_ADDR,
 				(struct vtp_reg *)VTP1_CTRL_ADDR};

@@ -51,6 +53,21 @@ static struct vtp_reg *vtpreg[2] = {
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 #endif
 
+void config_dmm(const struct dmm_lisa_map_regs *regs)
+{
+	enable_dmm_clocks();
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
+}
+
 static void config_vtp(int nr)
 {
 	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,

index 1cbadff..15ca4c1 100644
@@ -100,6 +100,11 @@
 #define MT41J512M8RH125_IOCTRL_VALUE		0x18B
 
 /**
+ * Configure DMM
+ */
+void config_dmm(const struct dmm_lisa_map_regs *regs);
+
+/**
  * Configure SDRAM
  */
 void config_sdram(const struct emif_regs *regs, int nr);

index 1f597c0..e0a3b8b 100644
@@ -153,7 +153,11 @@ typedef struct hsmmc {
 #define MMC_CMD0	(INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 
 /* Clock Configurations and Macros */
+#ifdef CONFIG_AM33XX
 #define MMC_CLOCK_REFERENCE	96 /* MHz */
+#elif defined(CONFIG_TI814X)
+#define MMC_CLOCK_REFERENCE	192 /* MHz */
+#endif
 
 #define mmc_reg_out(addr, mask, val)\
 	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))

index 87a0917..02bc85b 100644
@@ -43,7 +43,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 
 	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
-					defined(CONFIG_AM33XX)
+			defined(CONFIG_AM33XX) || defined(CONFIG_TI814X)
 	serial_out(0x7, &com_port->mdr1);	/* mode select reset TL16C750*/
 #endif
 	serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr);

@@ -57,7 +57,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 	serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
 	serial_out(UART_LCRVAL, &com_port->lcr);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
-	defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX)
+	defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
+	defined(CONFIG_TI814X)
 
 #if defined(CONFIG_APTIX)
 	/* /13 mode so Aptix 6MHz can hit 115200 */

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new file mode 100644
index 0000000..40f8710
@@ -0,0 +1,7 @@
+#ifndef _EVM_H
+#define _EVM_H
+
+void enable_uart0_pin_mux(void);
+void enable_mmc1_pin_mux(void);
+
+#endif /* _EVM_H */

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