ARM: imx6q{dl}: add the WEIM driver
Subsystems (2)
v4 cover ARM: imx6q{dl}: add the WEIM driver
This patch set adds a new driver for WEIM in the imx6q{dl}-sabreauto boards.
The WEIM(Wireless External Interface Module) works like a bus. You can attach many different devices on it, such as NOR, onenand.
In the case of i.MX6q-sabreauto, only the NOR is connected to WEIM.
v3 --> v4:
[0] use a more proper pad value for the data pins.
[1] remove the weim_remove() hook.
[2] remove the blank line.
[3] use the lower case for the hex value.
[4] add returne value for weim_parse_dt().
[5] rename the pinctrls.
v2 --> v3:
[0] split the NOR pinctrl.
[1] make the driver unloaded. change to bool type in Kconfig.
[2] use the of_platform_populate().
[3] remove the unused "interrupt" property from the Doc.
v1 --> v2:
[0] remove used PADs.
[1] fix the wrong pad values, (thanks Alison Chaiken)
[2] remove the weim-cs-index.
[3] add "fsl" for the weim-cs-timing.
[4] remove the partitions info in the document.
[5] rewrite the drivers(follow Sascha and Shawn's comments)
Huang Shijie (6):
drivers: bus: add a new driver for WEIM
ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIM
ARM: dts: imx6qdl: add more information for WEIM
ARM: dts: imx6q: add pinctrls for WEIM NOR
ARM: dts: imx6dl: add pinctrls for WEIM NOR
ARM: dts: imx6qdl-sabreauto: enable the WEIM NOR
Documentation/devicetree/bindings/bus/imx-weim.txt | 49 +++++++ arch/arm/boot/dts/imx6dl-sabreauto.dts | 9 +- arch/arm/boot/dts/imx6dl.dtsi | 58 ++++++++ arch/arm/boot/dts/imx6q-sabreauto.dts | 9 +- arch/arm/boot/dts/imx6q.dtsi | 59 +++++++++ arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 21 +++- arch/arm/boot/dts/imx6qdl.dtsi | 4 +- drivers/bus/Kconfig | 9 ++ drivers/bus/Makefile | 1 + drivers/bus/imx-weim.c | 138 ++++++++++++++++++++ 10 files changed, 353 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt create mode 100644 drivers/bus/imx-weim.c
PATCH v4 1/6 drivers: bus: add a new driver for WEIM
The WEIM(Wireless External Interface Module) works like a bus. You can attach many different devices on it, such as NOR, onenand.
In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
This patch also adds the devicetree binding document. The driver only works when the devicetree is enabled.
--- Documentation/devicetree/bindings/bus/imx-weim.txt | 49 +++++++ drivers/bus/Kconfig | 9 ++ drivers/bus/Makefile | 1 + drivers/bus/imx-weim.c | 138 ++++++++++++++++++++ 4 files changed, 197 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt create mode 100644 drivers/bus/imx-weim.c
Documentation/devicetree/bindings/bus/imx-weim.txt new file +49 -0
@@ -0,0 +1,49 @@ +Device tree bindings for i.MX Wireless External Interface Module (WEIM) + +The term "wireless" does not imply that the WEIM is literally an interface +without wires. It simply means that this module was originally designed for +wireless and mobile applications that use low-power technology. + +The actual devices are instantiated from the child nodes of a WEIM node. + +Required properties: + + - compatible: Should be set to "fsl,imx6q-weim" + - reg: A resource specifier for the register space + (see the example below) + - clocks: the clock, see the example below. + - #address-cells: Must be set to 2 to allow memory address translation + - #size-cells: Must be set to 1 to allow CS address passing + - ranges: Must be set up to reflect the memory layout with four + integer values for each chip-select line in use: + + <cs-number> 0 <physical address of mapping> <size> + +Timing property for child nodes. It is mandatory, not optional. + + - fsl,weim-cs-timing: The timing array, contains 6 timing values for the + child node. We can get the CS index from the child + node's "reg" property. This property contains the values + for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1, + EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order. + +Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: + + weim: weim at 021b8000 { + compatible = "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + clocks = <&clks 196>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x08000000>; + + nor at 0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; + };
drivers/bus/Kconfig +9 -0
@@ -4,6 +4,15 @@ menu "Bus devices" +config IMX_WEIM + bool "Freescale EIM DRIVER" + depends on ARCH_MXC + help + Driver for i.MX6 WEIM controller. + The WEIM(Wireless External Interface Module) works like a bus. + You can attach many different devices on it, such as NOR, onenand. + But now, we only support the Parallel NOR. + config MVEBU_MBUS bool depends on PLAT_ORION
drivers/bus/Makefile +1 -0
@@ -2,6 +2,7 @@ # Makefile for the bus drivers. # +obj-$(CONFIG_IMX_WEIM) += imx-weim.o obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
drivers/bus/imx-weim.c new file +138 -0
138 lines not on this page · raw message
Signature · 1 line
1.7.1
Sascha Hauer
maintainerPATCH v4 1/6 drivers: bus: add a new driver for WEIM
Quoted 9 lines · Huang Shijie
The WEIM(Wireless External Interface Module) works like a bus. You can attach many different devices on it, such as NOR, onenand.
In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
This patch also adds the devicetree binding document. The driver only works when the devicetree is enabled.
Signed-off-by Huang Shijie <[email protected]>
Looks good to me now. Thanks for working on this.
Sascha
Signature · 4 lines
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PATCH v4 1/6 drivers: bus: add a new driver for WEIM
In reply to Huang ShijieHi Arnd,
Quoted 8 lines · Huang Shijie
The WEIM(Wireless External Interface Module) works like a bus. You can attach many different devices on it, such as NOR, onenand.
In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
This patch also adds the devicetree binding document. The driver only works when the devicetree is enabled.
Quoted 6 lines
Signed-off-by Huang Shijie <[email protected]>--- Documentation/devicetree/bindings/bus/imx-weim.txt | 49 +++++++ drivers/bus/Kconfig | 9 ++ drivers/bus/Makefile | 1 + drivers/bus/imx-weim.c | 138 ++++++++++++++++++++
What's the general merge path for drivers/bus/ ones? It's not clear to me who is collecting those drivers/bus/ patches.
Shawn
Quoted 3 lines
4 files changed, 197 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt create mode 100644 drivers/bus/imx-weim.c
PATCH v4 1/6 drivers: bus: add a new driver for WEIM
In reply to Huang ShijieQuoted 9 lines · Huang Shijie
The WEIM(Wireless External Interface Module) works like a bus. You can attach many different devices on it, such as NOR, onenand.
In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
This patch also adds the devicetree binding document. The driver only works when the devicetree is enabled.
Signed-off-by Huang Shijie <[email protected]>
Quoted 8 lines
--- Documentation/devicetree/bindings/bus/imx-weim.txt | 49 +++++++ drivers/bus/Kconfig | 9 ++ drivers/bus/Makefile | 1 + drivers/bus/imx-weim.c | 138 ++++++++++++++++++++ 4 files changed, 197 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt create mode 100644 drivers/bus/imx-weim.c
Since no one is collecting drivers/bus/ patches right now, I just applied the whole series to have the patch go via imx -> arm-soc. Please let me know if there is any problem.
Shawn
PATCH v4 1/6 drivers: bus: add a new driver for WEIM
Quoted 3 lines · Shawn Guo
Since no one is collecting
drivers/bus/patches right now, I just applied the whole series to have the patch go via imx -> arm-soc. Please let me know if there is any problem.
I think that's fine.
Arnd
PATCH v4 1/6 drivers: bus: add a new driver for WEIM
In reply to Shawn GuoQuoted 20 lines · On Thursday 06 June 2013 23:09:37 Shawn Guo wrote:
Quoted 9 lines · Huang Shijie
The WEIM(Wireless External Interface Module) works like a bus. You can attach many different devices on it, such as NOR, onenand.
In the case of i.MX6q-sabreauto, the NOR is connected to WEIM.
This patch also adds the devicetree binding document. The driver only works when the devicetree is enabled.
Signed-off-by Huang Shijie <[email protected]>Quoted 8 lines
--- Documentation/devicetree/bindings/bus/imx-weim.txt | 49 +++++++ drivers/bus/Kconfig | 9 ++ drivers/bus/Makefile | 1 + drivers/bus/imx-weim.c | 138 ++++++++++++++++++++ 4 files changed, 197 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt create mode 100644 drivers/bus/imx-weim.c
Quoted 3 lines
Since no one is collecting
drivers/bus/patches right now, I just applied the whole series to have the patch go via imx -> arm-soc. Please let me know if there is any problem.
Sounds ok to me. If we see a lot of these, we can try to find a maintainer.
Arnd
PATCH v4 2/6 ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIM
In reply to Huang ShijieIn the imx6q-sabreauto and imx6dl-sabreauto boards, the pin MX6Q{DL}_PAD_EIM_D19 is used as a GPIO for SPI NOR, but it is used as a data pin for the WEIM NOR.
In order to fix the conflict, this patch removes the pin from the hog, and adds a new board-level pinctrl: pinctrl_ecspi1_sabreauto.
The SPI NOR selects this pinctrl_ecspi1_sabreauto when it is enabled.
--- arch/arm/boot/dts/imx6dl-sabreauto.dts | 9 ++++++++- arch/arm/boot/dts/imx6q-sabreauto.dts | 9 ++++++++- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 2 +- 3 files changed, 17 insertions(+), 3 deletions(-)
arch/arm/boot/dts/imx6dl-sabreauto.dts +8 -1
@@ -25,7 +25,14 @@ fsl,pins = < MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 - MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { + fsl,pins = < + MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000 >; }; };
arch/arm/boot/dts/imx6q-sabreauto.dts +8 -1
@@ -29,7 +29,14 @@ fsl,pins = < MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 - MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { + fsl,pins = < + MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 >; }; };
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +1 -1
@@ -20,7 +20,7 @@ fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_1>; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>; status = "disabled"; /* pin conflict with WEIM NOR */ flash: m25p80 at 0 {
Signature · 1 line
1.7.1
PATCH v4 3/6 ARM: dts: imx6qdl: add more information for WEIM
In reply to Huang ShijieAdd the clock and compatible information for the weim. Also adds the weim label.
--- arch/arm/boot/dts/imx6qdl.dtsi | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-)
arch/arm/boot/dts/imx6qdl.dtsi +3 -1
@@ -744,9 +744,11 @@ reg = <0x021b4000 0x4000>; }; - weim at 021b8000 { + weim: weim at 021b8000 { + compatible = "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; interrupts = <0 14 0x04>; + clocks = <&clks 196>; }; ocotp at 021bc000 {
Signature · 1 line
1.7.1
PATCH v4 4/6 ARM: dts: imx6q: add pinctrls for WEIM NOR
In reply to Huang ShijieAdd two pinctrls for WEIM:
one for the weim nor, another for the chipselect.
--- arch/arm/boot/dts/imx6q.dtsi | 59 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 59 insertions(+), 0 deletions(-)
arch/arm/boot/dts/imx6q.dtsi +59 -0
@@ -323,6 +323,65 @@ >; }; }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weimnorgrp-1 { + fsl,pins = < + MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + /* data */ + MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + /* address */ + MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + + }; }; };
Signature · 1 line
1.7.1
PATCH v4 5/6 ARM: dts: imx6dl: add pinctrls for WEIM NOR
In reply to Huang ShijieAdd two pinctrls for WEIM:
one for the weim nor, another for the chipselect.
--- arch/arm/boot/dts/imx6dl.dtsi | 58 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 58 insertions(+), 0 deletions(-)
arch/arm/boot/dts/imx6dl.dtsi +58 -0
@@ -183,6 +183,64 @@ }; }; + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + /* data */ + MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + /* address */ + MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + + }; };
Signature · 1 line
1.7.1
PATCH v4 6/6 ARM: dts: imx6qdl-sabreauto: enable the WEIM NOR
In reply to Huang ShijieEnable the WEIM NOR for imx6q{dl}-sabreauto boards.
For the pin conflict with SPI NOR, its status is set to "disabled".
--- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-)
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +19 -0
@@ -58,3 +58,22 @@ wp-gpios = <&gpio1 13 0>; status = "okay"; }; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x08000000>; + status = "disabled"; /* pin conflict with SPI NOR */ + + nor at 0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; +};
Signature · 1 line
1.7.1