tegra: change clocksource driver to be more lowlevel

PATCH New Lucas Stach 1 participant 6 messages Jun 4, 2013

Subsystems (7)

Arm (32-bit) Arm sub-architectures Common clk Tegra architecture support +3 more subsystems

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Lucas Stach

author

2013-06-04 07:29 UTC #0 lore raw

PATCH 1/6 tegra: change clocksource driver to be more lowlevel

In order to properly bring up the system PLLs we need a reliable clocksource. To break the circular dependency between the clocksource and the CAR driver, get the OSC frequency with a lowlevel function.

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 23 +++++++++++++++++++++++
 arch/arm/mach-tegra/tegra20-timer.c         | 16 +++-------------
 2 files changed, 26 insertions(+), 13 deletions(-)

arch/arm/mach-tegra/include/mach/lowlevel.h +23 -0

index b7c01c0..071416f 100644
@@ -142,5 +142,28 @@ static inline long tegra20_get_debuguart_base(void)
 	return uart_id_to_base[id];
 }
 
+#define CRC_OSC_CTRL			0x050
+#define CRC_OSC_CTRL_OSC_FREQ_SHIFT	30
+#define CRC_OSC_CTRL_OSC_FREQ_MASK	(0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT)
+
+static inline unsigned int tegra_get_osc_clock(void)
+{
+	u32 osc_ctrl = readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL);
+
+	switch ((osc_ctrl & CRC_OSC_CTRL_OSC_FREQ_MASK) >>
+		CRC_OSC_CTRL_OSC_FREQ_SHIFT) {
+	case 0:
+		return 13000000;
+	case 1:
+		return 19200000;
+	case 2:
+		return 12000000;
+	case 3:
+		return 26000000;
+	default:
+		return 0;
+	}
+}
+
 /* reset vector for the main CPU complex */
 void tegra_maincomplex_entry(void);

arch/arm/mach-tegra/tegra20-timer.c +3 ~~-13~~

index aafbfd4..2b32647 100644
@@ -24,6 +24,7 @@
 #include <init.h>
 #include <io.h>
 #include <linux/clk.h>
+#include <mach/lowlevel.h>
 
 /* register definitions */
 #define TIMERUS_CNTR_1US	0x10

@@ -43,8 +44,6 @@ static struct clocksource cs = {
 
 static int tegra20_timer_probe(struct device_d *dev)
 {
-	struct clk *timer_clk;
-	unsigned long rate;
 	u32 reg;
 
 	/* use only one timer */

@@ -57,22 +56,13 @@ static int tegra20_timer_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	timer_clk = clk_get(dev, NULL);
-	if (!timer_clk) {
-		dev_err(dev, "could not get clock\n");
-		return -ENODEV;
-	}
-
-	clk_enable(timer_clk);
-
 	/*
 	 * calibrate timer to run at 1MHz
 	 * TIMERUS_USEC_CFG selects the scale down factor with bits [0:7]
 	 * representing the divisor and bits [8:15] representing the dividend
 	 * each in n+1 form.
 	 */
-	rate = clk_get_rate(timer_clk);
-	switch (rate) {
+	switch (tegra_get_osc_clock()) {
 	case 12000000:
 		reg = 0x000b;
 		break;

@@ -116,4 +106,4 @@ static int tegra20_timer_init(void)
 {
 	return platform_driver_register(&tegra20_timer_driver);
 }
-coredevice_initcall(tegra20_timer_init);
+core_initcall(tegra20_timer_init);

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Lucas Stach

author

2013-06-04 07:29 UTC #1 lore raw

PATCH 2/6 clk: allow to instanciate clk gate without registering it

Allows to reuse the clk gate code within other clocks.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/clk/clk-gate.c | 31 +++++++++++++++++++++++++------
 include/linux/clk.h    |  4 ++++
 2 files changed, 29 insertions(+), 6 deletions(-)

drivers/clk/clk-gate.c +25 -6

index a455094..e4e9967 100644
@@ -27,6 +27,8 @@ struct clk_gate {
 	const char *parent;
 };
 
+#define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
+
 static int clk_gate_enable(struct clk *clk)
 {
 	struct clk_gate *g = container_of(clk, struct clk_gate, clk);

@@ -68,11 +70,10 @@ struct clk_ops clk_gate_ops = {
 	.is_enabled = clk_gate_is_enabled,
 };
 
-struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg,
-		u8 shift)
+struct clk *clk_gate_alloc(const char *name, const char *parent,
+		void __iomem *reg, u8 shift)
 {
 	struct clk_gate *g = xzalloc(sizeof(*g));
-	int ret;
 
 	g->parent = parent;
 	g->reg = reg;

@@ -82,11 +83,29 @@ struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg,
 	g->clk.parent_names = &g->parent;
 	g->clk.num_parents = 1;
 
-	ret = clk_register(&g->clk);
+	return &g->clk;
+}
+
+void clk_gate_free(struct clk *clk_gate)
+{
+	struct clk_gate *g = to_clk_gate(clk_gate);
+
+	free(g);
+}
+
+struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg,
+		u8 shift)
+{
+	struct clk *g;
+	int ret;
+
+	g = clk_gate_alloc(name , parent, reg, shift);
+
+	ret = clk_register(g);
 	if (ret) {
-		free(g);
+		free(to_clk_gate(g));
 		return ERR_PTR(ret);
 	}
 
-	return &g->clk;
+	return g;
 }

include/linux/clk.h +4 -0

index 0f7158a..cf41bd7 100644
@@ -199,6 +199,10 @@ struct clk *clk_fixed_factor(const char *name,
 		const char *parent, unsigned int mult, unsigned int div);
 struct clk *clk_mux(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parents, u8 num_parents);
+
+struct clk *clk_gate_alloc(const char *name, const char *parent,
+		void __iomem *reg, u8 shift);
+void clk_gate_free(struct clk *clk_gate);
 struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg,
 		u8 shift);

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Lucas Stach

author

2013-06-04 07:30 UTC #2 lore raw

PATCH 3/6 clk: allow to instanciate clk mux without registering it

In reply to Lucas Stach

Allows to reuse clk mux code within other clocks.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/clk/clk-mux.c | 29 ++++++++++++++++++++++++-----
 include/linux/clk.h   |  4 ++++
 2 files changed, 28 insertions(+), 5 deletions(-)

drivers/clk/clk-mux.c +24 -5

index cb5f1a1..47efe12 100644
@@ -27,6 +27,8 @@ struct clk_mux {
 	int width;
 };
 
+#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
+
 static int clk_mux_get_parent(struct clk *clk)
 {
 	struct clk_mux *m = container_of(clk, struct clk_mux, clk);

@@ -53,11 +55,10 @@ struct clk_ops clk_mux_ops = {
 	.set_parent = clk_mux_set_parent,
 };
 
-struct clk *clk_mux(const char *name, void __iomem *reg,
+struct clk *clk_mux_alloc(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parents, u8 num_parents)
 {
 	struct clk_mux *m = xzalloc(sizeof(*m));
-	int ret;
 
 	m->reg = reg;
 	m->shift = shift;

@@ -67,11 +68,29 @@ struct clk *clk_mux(const char *name, void __iomem *reg,
 	m->clk.parent_names = parents;
 	m->clk.num_parents = num_parents;
 
-	ret = clk_register(&m->clk);
+	return &m->clk;
+}
+
+void clk_mux_free(struct clk *clk_mux)
+{
+	struct clk_mux *m = to_clk_mux(clk_mux);
+
+	free(m);
+}
+
+struct clk *clk_mux(const char *name, void __iomem *reg,
+		u8 shift, u8 width, const char **parents, u8 num_parents)
+{
+	struct clk *m;
+	int ret;
+
+	m = clk_mux_alloc(name, reg, shift, width, parents, num_parents);
+
+	ret = clk_register(m);
 	if (ret) {
-		free(m);
+		free(to_clk_mux(m));
 		return ERR_PTR(ret);
 	}
 
-	return &m->clk;
+	return m;
 }

include/linux/clk.h +4 -0

index cf41bd7..d5e5b6b 100644
@@ -197,6 +197,10 @@ struct clk *clk_divider_table(const char *name,
 		const struct clk_div_table *table);
 struct clk *clk_fixed_factor(const char *name,
 		const char *parent, unsigned int mult, unsigned int div);
+
+struct clk *clk_mux_alloc(const char *name, void __iomem *reg,
+		u8 shift, u8 width, const char **parents, u8 num_parents);
+void clk_mux_free(struct clk *clk_mux);
 struct clk *clk_mux(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parents, u8 num_parents);

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Lucas Stach

author

2013-06-04 07:30 UTC #3 lore raw

PATCH 4/6 tegra: deduplicate clk defines

In reply to Lucas Stach

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/mach-tegra/include/mach/tegra20-car.h | 90 +++++++++-----------------
 arch/arm/mach-tegra/tegra_avp_init.c           |  6 +-
 2 files changed, 33 insertions(+), 63 deletions(-)

arch/arm/mach-tegra/include/mach/tegra20-car.h +30 ~~-60~~

index 5669732..54c74c7 100644
@@ -111,68 +111,38 @@
 #define CRC_PLLX_MISC_VCOCON_MASK	(0xf << CRC_PLLX_MISC_VCOCON_SHIFT)
 
 #define CRC_RST_DEV_L_SET		0x300
-#define CRC_RST_DEV_L_SET_CACHE2	(1 << 31)
-#define CRC_RST_DEV_L_SET_VCP		(1 << 29)
-#define CRC_RST_DEV_L_SET_HOST1X	(1 << 28)
-#define CRC_RST_DEV_L_SET_DISP1		(1 << 27)
-#define CRC_RST_DEV_L_SET_DISP2		(1 << 26)
-#define CRC_RST_DEV_L_SET_IDE		(1 << 25)
-#define CRC_RST_DEV_L_SET_3D		(1 << 24)
-#define CRC_RST_DEV_L_SET_ISP		(1 << 23)
-#define CRC_RST_DEV_L_SET_USBD		(1 << 22)
-#define CRC_RST_DEV_L_SET_2D		(1 << 21)
-#define CRC_RST_DEV_L_SET_VI		(1 << 20)
-#define CRC_RST_DEV_L_SET_EPP		(1 << 19)
-#define CRC_RST_DEV_L_SET_I2S2		(1 << 18)
-#define CRC_RST_DEV_L_SET_PWM		(1 << 17)
-#define CRC_RST_DEV_L_SET_TWC		(1 << 16)
-#define CRC_RST_DEV_L_SET_SDMMC4	(1 << 15)
-#define CRC_RST_DEV_L_SET_SDMMC1	(1 << 14)
-#define CRC_RST_DEV_L_SET_NDFLASH	(1 << 13)
-#define CRC_RST_DEV_L_SET_I2C1		(1 << 12)
-#define CRC_RST_DEV_L_SET_I2S1		(1 << 11)
-#define CRC_RST_DEV_L_SET_SPDIF		(1 << 10)
-#define CRC_RST_DEV_L_SET_SDMMC2	(1 << 9)
-#define CRC_RST_DEV_L_SET_GPIO		(1 << 8)
-#define CRC_RST_DEV_L_SET_UART2		(1 << 7)
-#define CRC_RST_DEV_L_SET_UART1		(1 << 6)
-#define CRC_RST_DEV_L_SET_TMR		(1 << 5)
-#define CRC_RST_DEV_L_SET_AC97		(1 << 3)
-#define CRC_RST_DEV_L_SET_SYS		(1 << 2)
-#define CRC_RST_DEV_L_SET_COP		(1 << 1)
-#define CRC_RST_DEV_L_SET_CPU		(1 << 0)
+#define CRC_RST_DEV_L_CACHE2		(1 << 31)
+#define CRC_RST_DEV_L_VCP		(1 << 29)
+#define CRC_RST_DEV_L_HOST1X		(1 << 28)
+#define CRC_RST_DEV_L_DISP1		(1 << 27)
+#define CRC_RST_DEV_L_DISP2		(1 << 26)
+#define CRC_RST_DEV_L_IDE		(1 << 25)
+#define CRC_RST_DEV_L_3D		(1 << 24)
+#define CRC_RST_DEV_L_ISP		(1 << 23)
+#define CRC_RST_DEV_L_USBD		(1 << 22)
+#define CRC_RST_DEV_L_2D		(1 << 21)
+#define CRC_RST_DEV_L_VI		(1 << 20)
+#define CRC_RST_DEV_L_EPP		(1 << 19)
+#define CRC_RST_DEV_L_I2S2		(1 << 18)
+#define CRC_RST_DEV_L_PWM		(1 << 17)
+#define CRC_RST_DEV_L_TWC		(1 << 16)
+#define CRC_RST_DEV_L_SDMMC4		(1 << 15)
+#define CRC_RST_DEV_L_SDMMC1		(1 << 14)
+#define CRC_RST_DEV_L_NDFLASH		(1 << 13)
+#define CRC_RST_DEV_L_I2C1		(1 << 12)
+#define CRC_RST_DEV_L_I2S1		(1 << 11)
+#define CRC_RST_DEV_L_SPDIF		(1 << 10)
+#define CRC_RST_DEV_L_SDMMC2		(1 << 9)
+#define CRC_RST_DEV_L_GPIO		(1 << 8)
+#define CRC_RST_DEV_L_UART2		(1 << 7)
+#define CRC_RST_DEV_L_UART1		(1 << 6)
+#define CRC_RST_DEV_L_TMR		(1 << 5)
+#define CRC_RST_DEV_L_AC97		(1 << 3)
+#define CRC_RST_DEV_L_SYS		(1 << 2)
+#define CRC_RST_DEV_L_COP		(1 << 1)
+#define CRC_RST_DEV_L_CPU		(1 << 0)
 
 #define CRC_RST_DEV_L_CLR		0x304
-#define CRC_RST_DEV_L_CLR_CACHE2	(1 << 31)
-#define CRC_RST_DEV_L_CLR_VCP		(1 << 29)
-#define CRC_RST_DEV_L_CLR_HOST1X	(1 << 28)
-#define CRC_RST_DEV_L_CLR_DISP1		(1 << 27)
-#define CRC_RST_DEV_L_CLR_DISP2		(1 << 26)
-#define CRC_RST_DEV_L_CLR_IDE		(1 << 25)
-#define CRC_RST_DEV_L_CLR_3D		(1 << 24)
-#define CRC_RST_DEV_L_CLR_ISP		(1 << 23)
-#define CRC_RST_DEV_L_CLR_USBD		(1 << 22)
-#define CRC_RST_DEV_L_CLR_2D		(1 << 21)
-#define CRC_RST_DEV_L_CLR_VI		(1 << 20)
-#define CRC_RST_DEV_L_CLR_EPP		(1 << 19)
-#define CRC_RST_DEV_L_CLR_I2S2		(1 << 18)
-#define CRC_RST_DEV_L_CLR_PWM		(1 << 17)
-#define CRC_RST_DEV_L_CLR_TWC		(1 << 16)
-#define CRC_RST_DEV_L_CLR_SDMMC4	(1 << 15)
-#define CRC_RST_DEV_L_CLR_SDMMC1	(1 << 14)
-#define CRC_RST_DEV_L_CLR_NDFLASH	(1 << 13)
-#define CRC_RST_DEV_L_CLR_I2C1		(1 << 12)
-#define CRC_RST_DEV_L_CLR_I2S1		(1 << 11)
-#define CRC_RST_DEV_L_CLR_SPDIF		(1 << 10)
-#define CRC_RST_DEV_L_CLR_SDMMC2	(1 << 9)
-#define CRC_RST_DEV_L_CLR_GPIO		(1 << 8)
-#define CRC_RST_DEV_L_CLR_UART2		(1 << 7)
-#define CRC_RST_DEV_L_CLR_UART1		(1 << 6)
-#define CRC_RST_DEV_L_CLR_TMR		(1 << 5)
-#define CRC_RST_DEV_L_CLR_AC97		(1 << 3)
-#define CRC_RST_DEV_L_CLR_SYS		(1 << 2)
-#define CRC_RST_DEV_L_CLR_COP		(1 << 1)
-#define CRC_RST_DEV_L_CLR_CPU		(1 << 0)
 
 #define CRC_RST_CPU_CMPLX_SET		0x340

arch/arm/mach-tegra/tegra_avp_init.c +3 -3

index 4823733..5099e91 100644
@@ -54,14 +54,14 @@ static void assert_maincomplex_reset(int num_cores)
 		mask |= 0x1111 << i;
 
 	writel(mask, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_SET);
-	writel(CRC_RST_DEV_L_SET_CPU, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_SET);
+	writel(CRC_RST_DEV_L_CPU, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_SET);
 }
 
 /* release reset state of the first core of the main CPU complex */
 static void deassert_cpu0_reset(void)
 {
 	writel(0x1111, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_CLR);
-	writel(CRC_RST_DEV_L_CLR_CPU, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_CLR);
+	writel(CRC_RST_DEV_L_CPU, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_CLR);
 }
 
 /* stop all internal and external clocks to the main CPU complex */

@@ -220,7 +220,7 @@ void barebox_arm_reset_vector(void)
 	deassert_cpu0_reset();
 
 	/* assert AVP reset to stop execution here */
-	writel(CRC_RST_DEV_L_SET_COP, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_SET);
+	writel(CRC_RST_DEV_L_COP, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_SET);
 
 	unreachable();
 }

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Lucas Stach

author

2013-06-04 07:40 UTC #4 lore raw

PATCH 5/6 tegra: add new clock framework driver

In reply to Lucas Stach

This removes the existing Tegra CAR driver and replaces it with code ported from the Linux clock framework.

In the current state only the relevant PLLs are supported, but this is no functional regression from the existing code.

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/mach-tegra/Makefile                   |   1 -
 arch/arm/mach-tegra/include/mach/tegra20-car.h |  36 ++
 arch/arm/mach-tegra/tegra20-car.c              | 120 -------
 drivers/clk/Makefile                           |   3 +
 drivers/clk/tegra/Makefile                     |   6 +
 drivers/clk/tegra/clk-divider.c                | 201 +++++++++++
 drivers/clk/tegra/clk-pll-out.c                | 139 ++++++++
 drivers/clk/tegra/clk-pll.c                    | 451 +++++++++++++++++++++++++
 drivers/clk/tegra/clk-tegra20.c                | 326 ++++++++++++++++++
 drivers/clk/tegra/clk.c                        |  57 ++++
 drivers/clk/tegra/clk.h                        | 127 +++++++
 11 files changed, 1346 insertions(+), 121 deletions(-)
 delete mode 100644 arch/arm/mach-tegra/tegra20-car.c
 create mode 100644 drivers/clk/tegra/Makefile
 create mode 100644 drivers/clk/tegra/clk-divider.c
 create mode 100644 drivers/clk/tegra/clk-pll-out.c
 create mode 100644 drivers/clk/tegra/clk-pll.c
 create mode 100644 drivers/clk/tegra/clk-tegra20.c
 create mode 100644 drivers/clk/tegra/clk.c
 create mode 100644 drivers/clk/tegra/clk.h

arch/arm/mach-tegra/Makefile +0 -1

index f9c771f..fd6a870 100644
@@ -2,6 +2,5 @@ CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
 lwl-y += tegra_avp_init.o
 lwl-y += tegra_maincomplex_init.o
 obj-y += tegra20.o
-obj-y += tegra20-car.o
 obj-y += tegra20-pmc.o
 obj-y += tegra20-timer.o

arch/arm/mach-tegra/include/mach/tegra20-car.h +36 -0

index 54c74c7..b770ae3 100644
@@ -82,6 +82,39 @@
 #define CRC_OSC_CTRL_PLL_REF_DIV_SHIFT	28
 #define CRC_OSC_CTRL_PLL_REF_DIV_MASK	(0x3 << CRC_OSC_CTRL_PLL_REF_DIV_SHIFT)
 
+#define CRC_PLL_BASE_LOCK		27
+#define CRC_PLLE_MISC_LOCK		11
+
+#define CRC_PLL_MISC_LOCK_ENABLE	18
+#define CRC_PLLDU_MISC_LOCK_ENABLE	22
+#define CRC_PLLE_MISC_LOCK_ENABLE	9
+
+#define CRC_PLLS_BASE			0x0f0
+#define CRC_PLLS_MISC			0x0f4
+
+#define CRC_PLLC_BASE			0x080
+#define CRC_PLLC_OUT			0x084
+#define CRC_PLLC_MISC			0x08c
+
+#define CRC_PLLM_BASE			0x090
+#define CRC_PLLM_OUT			0x094
+#define CRC_PLLM_MISC			0x09c
+
+#define CRC_PLLP_BASE			0x0a0
+#define CRC_PLLP_OUTA			0x0a4
+#define CRC_PLLP_OUTB			0x0a8
+#define CRC_PLLP_MISC			0x0ac
+
+#define CRC_PLLA_BASE			0x0b0
+#define CRC_PLLA_OUT			0x0b4
+#define CRC_PLLA_MISC			0x0bc
+
+#define CRC_PLLU_BASE			0x0c0
+#define CRC_PLLU_MISC			0x0cc
+
+#define CRC_PLLD_BASE			0x0d0
+#define CRC_PLLD_MISC			0x0dc
+
 #define CRC_PLLX_BASE			0x0e0
 #define CRC_PLLX_BASE_BYPASS		(1 << 31)
 #define CRC_PLLX_BASE_ENABLE		(1 << 30)

@@ -110,6 +143,9 @@
 #define CRC_PLLX_MISC_VCOCON_SHIFT	0
 #define CRC_PLLX_MISC_VCOCON_MASK	(0xf << CRC_PLLX_MISC_VCOCON_SHIFT)
 
+#define CRC_PLLE_BASE			0x0e8
+#define CRC_PLLE_MISC			0x0ec
+
 #define CRC_RST_DEV_L_SET		0x300
 #define CRC_RST_DEV_L_CACHE2		(1 << 31)
 #define CRC_RST_DEV_L_VCP		(1 << 29)

arch/arm/mach-tegra/tegra20-car.c deleted +0 ~~-120~~

120 lines not on this page · raw message

drivers/clk/Makefile +3 -0

index 656b859..b19ce91 100644
@@ -1,3 +1,6 @@
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed.o clk-divider.o clk-fixed-factor.o \
 				clk-mux.o clk-gate.o clk-divider-table.o
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
+
+#SoC specific
+obj-$(CONFIG_ARCH_TEGRA)	+= tegra/

drivers/clk/tegra/Makefile new file +6 -0

new file mode 100644
index 0000000..be58c20
@@ -0,0 +1,6 @@
+obj-y	+= clk.o
+obj-y	+= clk-divider.o
+obj-y	+= clk-pll.o
+obj-y	+= clk-pll-out.o
+
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= clk-tegra20.o
\ No newline at end of file

drivers/clk/tegra/clk-divider.c new file +201 -0

201 lines not on this page · raw message

drivers/clk/tegra/clk-pll-out.c new file +139 -0

139 lines not on this page · raw message

drivers/clk/tegra/clk-pll.c new file +451 -0

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drivers/clk/tegra/clk-tegra20.c new file +326 -0

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drivers/clk/tegra/clk.c new file +57 -0

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drivers/clk/tegra/clk.h new file +127 -0

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1.8.2.1


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Lucas Stach

author

2013-06-04 07:30 UTC #5 lore raw

PATCH 6/6 tegra: add peripheral clocks

In reply to Lucas Stach

Only UART clocks are included for now, but the code should cover other peripherals need too.

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/mach-tegra/include/mach/tegra20-car.h |  49 ++++++
 drivers/clk/tegra/Makefile                     |   1 +
 drivers/clk/tegra/clk-periph.c                 | 202 +++++++++++++++++++++++++
 drivers/clk/tegra/clk-tegra20.c                |  28 ++++
 drivers/clk/tegra/clk.h                        |  23 +++
 5 files changed, 303 insertions(+)
 create mode 100644 drivers/clk/tegra/clk-periph.c

arch/arm/mach-tegra/include/mach/tegra20-car.h +49 -0

index b770ae3..d4cb238 100644
@@ -146,6 +146,55 @@
 #define CRC_PLLE_BASE			0x0e8
 #define CRC_PLLE_MISC			0x0ec
 
+#define CRC_CLK_SOURCE_I2S1		0x100
+#define CRC_CLK_SOURCE_I2S2		0x104
+#define CRC_CLK_SOURCE_SPDIF_OUT	0x108
+#define CRC_CLK_SOURCE_SPDIF_IN		0x10c
+#define CRC_CLK_SOURCE_PWM		0x110
+#define CRC_CLK_SOURCE_SPI		0x114
+#define CRC_CLK_SOURCE_SBC1		0x134
+#define CRC_CLK_SOURCE_SBC2		0x118
+#define CRC_CLK_SOURCE_SBC3		0x11c
+#define CRC_CLK_SOURCE_SBC4		0x1b4
+#define CRC_CLK_SOURCE_XIO		0x120
+#define CRC_CLK_SOURCE_TWC		0x12c
+#define CRC_CLK_SOURCE_IDE		0x144
+#define CRC_CLK_SOURCE_NDFLASH		0x160
+#define CRC_CLK_SOURCE_VFIR		0x168
+#define CRC_CLK_SOURCE_SDMMC1		0x150
+#define CRC_CLK_SOURCE_SDMMC2		0x154
+#define CRC_CLK_SOURCE_SDMMC3		0x1bc
+#define CRC_CLK_SOURCE_SDMMC4		0x164
+#define CRC_CLK_SOURCE_CVE		0x140
+#define CRC_CLK_SOURCE_TVO		0x188
+#define CRC_CLK_SOURCE_TVDAC		0x194
+#define CRC_CLK_SOURCE_HDMI		0x18c
+#define CRC_CLK_SOURCE_DISP1		0x138
+#define CRC_CLK_SOURCE_DISP2		0x13c
+#define CRC_CLK_SOURCE_CSITE		0x1d4
+#define CRC_CLK_SOURCE_LA		0x1f8
+#define CRC_CLK_SOURCE_OWR		0x1cc
+#define CRC_CLK_SOURCE_NOR		0x1d0
+#define CRC_CLK_SOURCE_MIPI		0x174
+#define CRC_CLK_SOURCE_I2C1		0x124
+#define CRC_CLK_SOURCE_I2C2		0x198
+#define CRC_CLK_SOURCE_I2C3		0x1b8
+#define CRC_CLK_SOURCE_DVC		0x128
+#define CRC_CLK_SOURCE_UARTA		0x178
+#define CRC_CLK_SOURCE_UARTB		0x17c
+#define CRC_CLK_SOURCE_UARTC		0x1a0
+#define CRC_CLK_SOURCE_UARTD		0x1c0
+#define CRC_CLK_SOURCE_UARTE		0x1c4
+#define CRC_CLK_SOURCE_3D		0x158
+#define CRC_CLK_SOURCE_2D		0x15c
+#define CRC_CLK_SOURCE_MPE		0x170
+#define CRC_CLK_SOURCE_EPP		0x16c
+#define CRC_CLK_SOURCE_HOST1X		0x180
+#define CRC_CLK_SOURCE_VDE		0x1c8
+#define CRC_CLK_SOURCE_VI		0x148
+#define CRC_CLK_SOURCE_VI_SENSOR	0x1a8
+#define CRC_CLK_SOURCE_EMC		0x19c
+
 #define CRC_RST_DEV_L_SET		0x300
 #define CRC_RST_DEV_L_CACHE2		(1 << 31)
 #define CRC_RST_DEV_L_VCP		(1 << 29)

drivers/clk/tegra/Makefile +1 -0

index be58c20..e614722 100644
@@ -1,5 +1,6 @@
 obj-y	+= clk.o
 obj-y	+= clk-divider.o
+obj-y	+= clk-periph.o
 obj-y	+= clk-pll.o
 obj-y	+= clk-pll-out.o

drivers/clk/tegra/clk-periph.c new file +202 -0

202 lines not on this page · raw message

drivers/clk/tegra/clk-tegra20.c +28 -0

index 5f668cb..e70f99a 100644
@@ -275,6 +275,28 @@ static void tegra20_pll_init(void)
 			TEGRA_PLL_HAS_CPCON, pll_u_freq_table);
 }
 
+static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
+
+static void tegra20_periph_init(void)
+{
+	/* peripheral clocks without a divider */
+	clks[uarta] = tegra_clk_register_periph_nodiv("uarta", mux_pllpcm_clkm,
+			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTA, uarta, TEGRA_PERIPH_ON_APB);
+	clks[uartb] = tegra_clk_register_periph_nodiv("uartb", mux_pllpcm_clkm,
+			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTB, uartb, TEGRA_PERIPH_ON_APB);
+	clks[uartc] = tegra_clk_register_periph_nodiv("uartc", mux_pllpcm_clkm,
+			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTC, uartc, TEGRA_PERIPH_ON_APB);
+	clks[uartd] = tegra_clk_register_periph_nodiv("uartd", mux_pllpcm_clkm,
+			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTD, uartd, TEGRA_PERIPH_ON_APB);
+	clks[uarte] = tegra_clk_register_periph_nodiv("uarte", mux_pllpcm_clkm,
+			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTE, uarte, TEGRA_PERIPH_ON_APB);
+}
+
 static struct tegra_clk_init_table init_table[] = {
 	{pll_p,		clk_max,	216000000,	1},
 	{pll_p_out1,	clk_max,	28800000,	1},

@@ -283,6 +305,11 @@ static struct tegra_clk_init_table init_table[] = {
 	{pll_p_out4,	clk_max,	24000000,	1},
 	{pll_c,		clk_max,	600000000,	1},
 	{pll_c_out1,	clk_max,	120000000,	1},
+	{uarta,		pll_p,		0,		1},
+	{uartb,		pll_p,		0,		1},
+	{uartc,		pll_p,		0,		1},
+	{uartd,		pll_p,		0,		1},
+	{uarte,		pll_p,		0,		1},
 	{clk_max,	clk_max,	0,		0}, /* sentinel */
 };

@@ -294,6 +321,7 @@ static int tegra20_car_probe(struct device_d *dev)
 
 	tegra20_osc_clk_init();
 	tegra20_pll_init();
+	tegra20_periph_init();
 
 	tegra_init_from_table(init_table, clks, clk_max);

drivers/clk/tegra/clk.h +23 -0

index 2bc3698..9bb8f1c 100644
@@ -115,6 +115,29 @@ struct clk *tegra_clk_register_pll_out(const char *name,
 		const char *parent_name, void __iomem *reg, u8 shift,
 		u8 divider_flags);
 
+/* struct clk-periph - peripheral clock */
+struct tegra_clk_periph {
+	struct clk	hw;
+	struct clk	*gate;
+	struct clk	*mux;
+	struct clk	*div;
+	u8 		flags;
+	u8		rst_shift;
+	void __iomem	*rst_reg;
+};
+
+#define TEGRA_PERIPH_NO_RESET BIT(0)
+#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
+#define TEGRA_PERIPH_ON_APB BIT(2)
+
+struct clk *tegra_clk_register_periph_nodiv(const char *name,
+		const char **parent_names, int num_parents,
+		void __iomem *clk_base, u32 reg_offset, u8 id, u8 flags);
+
+struct clk *tegra_clk_register_periph(const char *name,
+		const char **parent_names, int num_parents,
+		void __iomem *clk_base, u32 reg_offset, u8 id, u8 flags);
+
 /* struct clk_init_table - clock initialization table */
 struct tegra_clk_init_table {
 	unsigned int	clk_id;

Signature · 7 lines

1.8.2.1


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