i2c: vt8500: Add support for I2C bus on Wondermedia SoCs

PATCH Applied Tony Prisk 2 participants 4 messages Jun 14, 2013 – Jun 17, 2013

Subsystems (2)

Device tree bindings I2C subsystem host drivers

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Tony Prisk

author

2013-06-14 21:52 UTC #0 lore raw

PATCH v3 1/1 i2c: vt8500: Add support for I2C bus on Wondermedia SoCs

This patch adds support for the I2C bus controllers found on Wondermedia 8xxx-series SoCs. Only master-mode is supported.

Signed-off-by Tony Prisk <[email protected]>

---
v3 changes:
Included the v2 changes for clarity.
Tidy up the I2C_NO_START code properly.
Remove the alias handling and allow the core to do it. Change MODULE_LICENSE to "GPL" as per module.h comments.

v2 changes:
Rewrite wmt_i2c_wait_bus_not_busy() as per Wolfram/Russell.
Fix init_completion and INIT_COMPLETION usages.
Remove magic value in wmt_i2c_reset_hardware().
Remove test for (!np) in wmt_i2c_probe() as we only support devicetree anyway. Remove reference to ->class = I2C_CLASS_HWMON.

 .../devicetree/bindings/i2c/i2c-vt8500.txt         |   24 +
 MAINTAINERS                                        |    1 +
 drivers/i2c/busses/Kconfig                         |   10 +
 drivers/i2c/busses/Makefile                        |    1 +
 drivers/i2c/busses/i2c-wmt.c                       |  479 ++++++++++++++++++++
 5 files changed, 515 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
 create mode 100644 drivers/i2c/busses/i2c-wmt.c

Documentation/devicetree/bindings/i2c/i2c-vt8500.txt new file +24 -0

new file mode 100644
index 0000000..94a425e
@@ -0,0 +1,24 @@
+* Wondermedia I2C Controller
+
+Required properties :
+
+ - compatible : should be "wm,wm8505-i2c"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number
+ - clocks : phandle to the I2C clock source
+
+Optional properties :
+
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+	Valid values are 100000 and 400000.
+	Default to 100000 if not specified, or invalid value.
+
+Example :
+
+	i2c_0: i2c at d8280000 {
+		compatible = "wm,wm8505-i2c";
+		reg = <0xd8280000 0x1000>;
+		interrupts = <19>;
+		clocks = <&clki2c0>;
+		clock-frequency = <400000>;
+	};

MAINTAINERS +1 -0

index 3d7782b..44ea994 100644
@@ -1285,6 +1285,7 @@ S:	Maintained
 F:	arch/arm/mach-vt8500/
 F:	drivers/clocksource/vt8500_timer.c
 F:	drivers/gpio/gpio-vt8500.c
+F:	drivers/i2c/busses/i2c-wmt.c
 F:	drivers/mmc/host/wmt-sdmmc.c
 F:	drivers/pwm/pwm-vt8500.c
 F:	drivers/rtc/rtc-vt8500.c

drivers/i2c/busses/Kconfig +10 -0

index 631736e..89e7ec2 100644
@@ -724,6 +724,16 @@ config I2C_VERSATILE
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-versatile.
 
+config I2C_WMT
+	tristate "Wondermedia WM8xxx SoC I2C bus support"
+	depends on ARCH_VT8500
+	help
+	  Say yes if you want to support the I2C bus on Wondermedia 8xxx-series
+	  SoCs.
+
+	  This driver can also be built as a module. If so, the module will be
+	  called i2c-wmt.
+
 config I2C_OCTEON
 	tristate "Cavium OCTEON I2C bus support"
 	depends on CPU_CAVIUM_OCTEON

drivers/i2c/busses/Makefile +1 -0

index 8f4fc23..3ba94a9 100644
@@ -71,6 +71,7 @@ obj-$(CONFIG_I2C_SIRF)		+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)	+= i2c-stu300.o
 obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o
+obj-$(CONFIG_I2C_WMT)		+= i2c-wmt.o
 obj-$(CONFIG_I2C_OCTEON)	+= i2c-octeon.o
 obj-$(CONFIG_I2C_XILINX)	+= i2c-xiic.o
 obj-$(CONFIG_I2C_XLR)		+= i2c-xlr.o

drivers/i2c/busses/i2c-wmt.c new file +479 -0

479 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Wolfram Sang

2013-06-15 11:16 UTC #1 lore raw

Quoted 5 lines · Tony Prisk

This patch adds support for the I2C bus controllers found on Wondermedia 8xxx-series SoCs. Only master-mode is supported.
Signed-off-by Tony Prisk <[email protected]>
---

...

drivers/i2c/busses/i2c-wmt.c line 74

Quoted 2 lines

drivers/i2c/busses/i2c-wmt.c new file +2 -0
+/* REG_TR */
+#define SCL_TIMEOUT(x)		(((x) & 0xFF) << 16)

I assume this should be << 8 since all regs are 16 bit wide.

Fixed it locally and ready to apply. Please confirm or send a proper fix. Rest looks fine.

Thanks for the submission!

Tony Prisk

author

2013-06-15 21:58 UTC #2 lore raw

Quoted 8 lines · Wolfram Sang

Quoted 5 lines · Tony Prisk
This patch adds support for the I2C bus controllers found on Wondermedia 8xxx-series SoCs. Only master-mode is supported.
Signed-off-by Tony Prisk <[email protected]>
---
...

Quoted 9 lines

drivers/i2c/busses/i2c-wmt.c line 74
Quoted 2 lines
drivers/i2c/busses/i2c-wmt.c new file +2 -0
+/* REG_TR */
+#define SCL_TIMEOUT(x)		(((x) & 0xFF) << 16)
I assume this should be << 8 since all regs are 16 bit wide.
Fixed it locally and ready to apply. Please confirm or send a proper fix. Rest looks fine.
Thanks for the submission!

It should be << 8. Please apply your locally corrected version.

Regards
Tony Prisk

Wolfram Sang

Applied

2013-06-17 07:11 UTC #3 lore raw

Quoted 13 lines · Tony Prisk

Quoted 12 lines · Wolfram Sang
Quoted 5 lines · Tony Prisk
This patch adds support for the I2C bus controllers found on Wondermedia 8xxx-series SoCs. Only master-mode is supported.
Signed-off-by Tony Prisk <[email protected]>
---
...
drivers/i2c/busses/i2c-wmt.c line 74
Quoted 2 lines
drivers/i2c/busses/i2c-wmt.c new file +2 -0
+/* REG_TR */
+#define SCL_TIMEOUT(x)		(((x) & 0xFF) << 16)
I assume this should be << 8 since all regs are 16 bit wide.

Quoted 6 lines

Quoted 5 lines
Fixed it locally and ready to apply. Please confirm or send a proper fix. Rest looks fine.
Thanks for the submission!
It should be << 8. Please apply your locally corrected version.

Applied to for-next, thanks!