ARM: dt: tegra30: iommu: Add "nvidia,swgroups"
Subsystems (3)
PATCH 2/23 ARM: dt: tegra30: iommu: Add "nvidia,swgroups"
This is a bitmap that indicates which HardWare Accelerators(HWA) are supported on Tegra30 SoC.
--- Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt | 6 +++++- arch/arm/boot/dts/tegra30.dtsi | 1 + 2 files changed, 6 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt +5 -1
@@ -8,14 +8,18 @@ Required properties: - nvidia,#asids : # of ASIDs - dma-window : IOVA start address and length. - nvidia,ahb : phandle to the ahb bus connected to SMMU. +- nvidia,swgroups: A bit map of supported HardWare Accelerators(HWA). + Each bit represents one sgroup. The assignments may be found in header + file <dt-bindings/iommu/tegra-swgid.h>. Example: - smmu { + iommu { compatible = "nvidia,tegra30-smmu"; reg = <0x7000f010 0x02c 0x7000f1f0 0x010 0x7000f228 0x05c>; nvidia,#asids = <4>; /* # of ASIDs */ dma-window = <0 0x40000000>; /* IOVA start & length */ + nvidia,swgroups = <0x00000000 0x000779ff>; nvidia,ahb = <&ahb>; };
arch/arm/boot/dts/tegra30.dtsi +1 -0
@@ -461,6 +461,7 @@ 0x7000f228 0x05c>; nvidia,#asids = <4>; /* # of ASIDs */ dma-window = <0 0x40000000>; /* IOVA start & length */ + nvidia,swgroups = <0x00000000 0x000779ff>; nvidia,ahb = <&ahb>; };
Signature · 1 line
1.8.1.5
PATCH 2/23 ARM: dt: tegra30: iommu: Add "nvidia,swgroups"
Quoted 14 lines · Hiroshi Doyu
This is a bitmap that indicates which HardWare Accelerators(HWA) are supported on Tegra30 SoC.
Signed-off-by Hiroshi Doyu <[email protected]>--- Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt | 6 +++++- arch/arm/boot/dts/tegra30.dtsi | 1 + 2 files changed, 6 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt +0
-0
Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt Required properties: · line 11
Quoted 4 lines
Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt +1
-0@@ -8,14 +8,18 @@ Required properties: - nvidia,#asids : # of ASIDs - dma-window : IOVA start address and length. - nvidia,ahb : phandle to the ahb bus connected to SMMU. +- nvidia,swgroups: A bit map of supported HardWare Accelerators(HWA).
Nit: you use the spelling "bitmap" in the subject but "bit map" here. Both are correct but perhaps we should stick to one.
Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt Required properties: · line 12
Quoted 1 line
Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt +1
-0+ Each bit represents one sgroup. The assignments may be found in header
Nit: "swgroup"
Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt Required properties: · line 16
Quoted 2 lines
Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt +1
-1- smmu { + iommu {
This change isn't really related, but given that the tegra30.dtsi already uses it I guess we can keep it as part of this patch.
Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt Required properties: · line 23
Quoted 7 lines
Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt +1
-0compatible = "nvidia,tegra30-smmu"; reg = <0x7000f010 0x02c 0x7000f1f0 0x010 0x7000f228 0x05c>; nvidia,#asids = <4>; /* # of ASIDs */ dma-window = <0 0x40000000>; /* IOVA start & length */ + nvidia,swgroups = <0x00000000 0x000779ff>;
Perhaps this should be a symbolic name too? Perhaps something like TEGRA30_SWGID_ALL?
Thierry
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