clk: Add APM X-Gene SoC clock driver
Subsystems (2)
v5 cover clk: Add APM X-Gene SoC clock driver
This patch adds APM X-Gene SoC clock driver support. Reference, PCP PLL, SoC PCP, and Ethernet clocks are defined via the DTS.
-v5:
* Remove duplicate code for soc/pcp clk init function
* Remove un-used flags field from structure
* Merge error handler code for device clock init function
* Update binding documentation
-v4:
* Remove flags from DTS and check status instead
* Change DTS reg entry to be identified by reg-names property
-v3:
* Make DTS compatible type for SoC PLL and PCP PLL
* Make use of of_iomap instead direct ioremap call
* Make kzalloc with variable instead structure
* Remove DTS binding for fixed-clock and fixed_factor_clock
* Remove unnecessary arch_initcall
-v2:
* Make depends on ARM64
* Fix duplicate registration
-v1 - Initial post
Loc Ho (3):
clk: Add APM X-Gene SoC clock driver for reference, PLL, and device
clocks.
clk: arm64: Add DTS clock entry for APM X-Gene Storm SoC with
reference to
Documentation: Add documentation for APM X-Gene clock binding with
PLL and
Documentation/devicetree/bindings/clock/xgene.txt | 111 +++++ arch/arm64/boot/dts/apm-storm.dtsi | 75 +++ drivers/clk/Kconfig | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk-xgene.c | 521 +++++++++++++++++++++ 5 files changed, 715 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/xgene.txt create mode 100644 drivers/clk/clk-xgene.c
PATCH v5 1/3 clk: Add APM X-Gene SoC clock driver
clk: Add APM X-Gene SoC clock driver for reference, PLL, and device clocks.
Signed-off-by Loc Ho <[email protected]>
Signed-off-by Kumar Sankaran <[email protected]>
Signed-off-by Vinayak Kale <[email protected]>
Signed-off-by Feng Kan <[email protected]>
--- drivers/clk/Kconfig | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk-xgene.c | 521 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 529 insertions(+), 0 deletions(-) create mode 100644 drivers/clk/clk-xgene.c
drivers/clk/Kconfig +7 -0
@@ -81,6 +81,13 @@ config COMMON_CLK_AXI_CLKGEN Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx FPGAs. It is commonly used in Analog Devices' reference designs. +config COMMON_CLK_XGENE + bool "Clock driver for APM XGene SoC" + default y + depends on ARM64 + ---help--- + Sypport for the APM X-Gene SoC reference, PLL, and device clocks. + endmenu source "drivers/clk/mvebu/Kconfig"
drivers/clk/Makefile +1 -0
@@ -39,3 +39,4 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o +obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
drivers/clk/clk-xgene.c new file +521 -0
521 lines not on this page · raw message
Signature · 1 line
1.5.5
PATCH v5 2/3 clk: arm64: Add DTS clock entry for APM X-Gene Storm SoC
clk: arm64: Add DTS clock entry for APM X-Gene Storm SoC with reference to reference, PCP PLL, SoC PLL, and Ethernet clocks.
Signed-off-by Loc Ho <[email protected]>
Signed-off-by Kumar Sankaran <[email protected]>
Signed-off-by Vinayak Kale <[email protected]>
Signed-off-by Feng Kan <[email protected]>
--- arch/arm64/boot/dts/apm-storm.dtsi | 75 ++++++++++++++++++++++++++++++++++++ 1 files changed, 75 insertions(+), 0 deletions(-)
arch/arm64/boot/dts/apm-storm.dtsi +75 -0
@@ -103,6 +103,81 @@ #size-cells = <2>; ranges; + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <100000000>; + clock-output-names = "refclk"; + }; + + pcppll: pcppll at 17000100 { + compatible = "apm,xgene-pcppll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "pcppll"; + reg = <0x0 0x17000100 0x0 0x1000>; + clock-output-names = "pcppll"; + type = <0>; + }; + + socpll: socpll at 17000120 { + compatible = "apm,xgene-socpll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "socpll"; + reg = <0x0 0x17000120 0x0 0x1000>; + clock-output-names = "socpll"; + type = <1>; + }; + + socplldiv2: socplldiv2 { + compatible = "fixed-factor-clock"; + #clock-cells = <1>; + clocks = <&socpll 0>; + clock-names = "socplldiv2"; + clock-mult = <1>; + clock-div = <2>; + clock-output-names = "socplldiv2"; + }; + + qmlclk: qmlclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "qmlclk"; + reg = <0x0 0x1703C000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "qmlclk"; + }; + + ethclk: ethclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "ethclk"; + reg = <0x0 0x17000000 0x0 0x1000>; + reg-names = "div-reg"; + divider-offset = <0x238>; + divider-width = <0x9>; + divider-shift = <0x0>; + clock-output-names = "ethclk"; + }; + + eth8clk: eth8clk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <ðclk 0>; + clock-names = "eth8clk"; + reg = <0x0 0x1702C000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "eth8clk"; + }; + }; + serial0: serial at 1c020000 { device_type = "serial"; compatible = "ns16550";
Signature · 1 line
1.5.5
PATCH v5 3/3 Documentation: Add documentation for APM X-Gene clock binding
Documentation: Add documentation for APM X-Gene clock binding with PLL and device clocks.
Signed-off-by Loc Ho <[email protected]>
Signed-off-by Kumar Sankaran <[email protected]>
Signed-off-by Vinayak Kale <[email protected]>
Signed-off-by Feng Kan <[email protected]>
--- Documentation/devicetree/bindings/clock/xgene.txt | 111 +++++++++++++++++++++ 1 files changed, 111 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/xgene.txt
Documentation/devicetree/bindings/clock/xgene.txt new file +111 -0
@@ -0,0 +1,111 @@ +Device Tree Clock bindings for APM X-Gene + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock + "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock + "apm,xgene-device-clock" - for a X-Gene device clock + +Required properties for SoC or PCP PLL clocks: +- reg : shall be the physical PLL register address for the pll clock. +- clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. +- #clock-cells : shall be set to 1. +- clock-output-names : shall be the name of the PLL referenced by derive + clock. +Optional properties for PLL clocks: +- clock-names : shall be the name of the PLL. If missing, use the device name. + +Required properties for device clocks: +- reg : shall be a list of address and length pairs describing the CSR + reset and/or the divider. Either may be omitted, but at least + one must be present. + - reg-names : shall be a string list describing the reg resource. This + may include "csr-reg" and/or "div-reg". If this property + is not present, the reg property is assumed to describe + only "csr-reg". +- clocks : shall be the input parent clock phandle for the clock. +- #clock-cells : shall be set to 1. +- clock-output-names : shall be the name of the device referenced. +Optional properties for device clocks: +- clock-names : shall be the name of the device clock. If missing, use the + device name. +- csr-offset : Offset to the CSR reset register from the reset address base. + Default is 0. +- csr-mask : CSR reset mask bit. Default is 0xF. +- enable-offset : Offset to the enable register from the reset address base. + Default is 0x8. +- enable-mask : CSR enable mask bit. Default is 0xF. +- divider-offset : Offset to the divider CSR register from the divider base. + Default is 0x0. +- divider-width : Width of the divider register. Default is 0. +- divider-shift : Bit shift of the divider register. Default is 0. + +For example: + + pcppll: pcppll at 17000100 { + compatible = "apm,xgene-pcppll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "pcppll"; + reg = <0x0 0x17000100 0x0 0x1000>; + clock-output-names = "pcppll"; + type = <0>; + }; + + socpll: socpll at 17000120 { + compatible = "apm,xgene-socpll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "socpll"; + reg = <0x0 0x17000120 0x0 0x1000>; + clock-output-names = "socpll"; + type = <1>; + }; + + qmlclk: qmlclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "qmlclk"; + reg = <0x0 0x1703C000 0x0 0x1000>; + reg-name = "csr-reg"; + clock-output-names = "qmlclk"; + }; + + ethclk: ethclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "ethclk"; + reg = <0x0 0x17000000 0x0 0x1000>; + reg-names = "div-reg"; + divider-offset = <0x238>; + divider-width = <0x9>; + divider-shift = <0x0>; + clock-output-names = "ethclk"; + }; + + apbclk: apbclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&ahbclk 0>; + clock-names = "apbclk"; + reg = <0x0 0x1F2AC000 0x0 0x1000 + 0x0 0x1F2AC000 0x0 0x1000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x200>; + enable-offset = <0x8>; + enable-mask = <0x200>; + divider-offset = <0x10>; + divider-width = <0x2>; + divider-shift = <0x0>; + flags = <0x8>; + clock-output-names = "apbclk"; + }; +
Signature · 1 line
1.5.5
PATCH v5 3/3 Documentation: Add documentation for APM X-Gene clock binding
Quoting Loc Ho (2013-06-26 10:56:11)
Quoted 38 lines
Documentation: Add documentation for APM X-Gene clock binding with PLL and device clocks.
Signed-off-by Loc Ho <[email protected]>Signed-off-by Kumar Sankaran <[email protected]>Signed-off-by Vinayak Kale <[email protected]>Signed-off-by Feng Kan <[email protected]>--- Documentation/devicetree/bindings/clock/xgene.txt | 111 +++++++++++++++++++++ 1 files changed, 111 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/xgene.txtDocumentation/devicetree/bindings/clock/xgene.txt new file +20
-0@@ -0,0 +1,111 @@ +Device Tree Clock bindings for APM X-Gene + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock + "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock + "apm,xgene-device-clock" - for a X-Gene device clock + +Required properties for SoC or PCP PLL clocks: +- reg : shall be the physical PLL register address for the pll clock. +- clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. +- #clock-cells : shall be set to 1. +- clock-output-names : shall be the name of the PLL referenced by derive + clock. +Optional properties for PLL clocks:
Documentation/devicetree/bindings/clock/xgene.txt line 30
Quoted 10 lines
Documentation/devicetree/bindings/clock/xgene.txt new file +10
-0+- clock-names : shall be the name of the PLL. If missing, use the device name. + +Required properties for device clocks: +- reg : shall be a list of address and length pairs describing the CSR + reset and/or the divider. Either may be omitted, but at least + one must be present. + - reg-names : shall be a string list describing the reg resource. This + may include "csr-reg" and/or "div-reg". If this property + is not present, the reg property is assumed to describe + only "csr-reg".
Where is reg-names used? I see it used in your DTS but I don't see clk-xgene.c doing anything with it.
Quoted 6 lines
Documentation/devicetree/bindings/clock/xgene.txt new file +6
-0+- clocks : shall be the input parent clock phandle for the clock. +- #clock-cells : shall be set to 1. +- clock-output-names : shall be the name of the device referenced. +Optional properties for device clocks: +- clock-names : shall be the name of the device clock. If missing, use the + device name.
Documentation/devicetree/bindings/clock/xgene.txt line 46
Quoted 10 lines
Documentation/devicetree/bindings/clock/xgene.txt new file +10
-0+- csr-offset : Offset to the CSR reset register from the reset address base. + Default is 0. +- csr-mask : CSR reset mask bit. Default is 0xF. +- enable-offset : Offset to the enable register from the reset address base. + Default is 0x8. +- enable-mask : CSR enable mask bit. Default is 0xF. +- divider-offset : Offset to the divider CSR register from the divider base. + Default is 0x0. +- divider-width : Width of the divider register. Default is 0. +- divider-shift : Bit shift of the divider register. Default is 0.
There is a general push to not have register-level details in DT. How many clocks do you think you'll end up defining in the future? If you have a lot then this binding could grow fairly large.
Regards,
Mike
Quoted 67 lines
Documentation/devicetree/bindings/clock/xgene.txt new file +65
-0+ +For example: + + pcppll: pcppll at 17000100 { + compatible = "apm,xgene-pcppll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "pcppll"; + reg = <0x0 0x17000100 0x0 0x1000>; + clock-output-names = "pcppll"; + type = <0>; + }; + + socpll: socpll at 17000120 { + compatible = "apm,xgene-socpll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "socpll"; + reg = <0x0 0x17000120 0x0 0x1000>; + clock-output-names = "socpll"; + type = <1>; + }; + + qmlclk: qmlclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "qmlclk"; + reg = <0x0 0x1703C000 0x0 0x1000>; + reg-name = "csr-reg"; + clock-output-names = "qmlclk"; + }; + + ethclk: ethclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "ethclk"; + reg = <0x0 0x17000000 0x0 0x1000>; + reg-names = "div-reg"; + divider-offset = <0x238>; + divider-width = <0x9>; + divider-shift = <0x0>; + clock-output-names = "ethclk"; + }; + + apbclk: apbclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&ahbclk 0>; + clock-names = "apbclk"; + reg = <0x0 0x1F2AC000 0x0 0x1000 + 0x0 0x1F2AC000 0x0 0x1000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x200>; + enable-offset = <0x8>; + enable-mask = <0x200>; + divider-offset = <0x10>; + divider-width = <0x2>; + divider-shift = <0x0>; + flags = <0x8>; + clock-output-names = "apbclk"; + }; +Signature · 1 line
1.5.5
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PATCH v5 3/3 Documentation: Add documentation for APM X-Gene clock binding
Quoting Loc Ho (2013-07-31 11:49:07)
Quoted 3 lines
With the latest version, this is used to determine whether it is divider register or csr register. In the file
clk-xgene.c, grep for "div-reg". It is around line 521.
Thanks for the rework, I've taken this for 3.13.
Regards,
Mike