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drm/radeon: fix 32-bit compile after dpm merge

PATCH New Dave Airlie 1 participant 1 message Jun 27, 2013

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Dave Airlie

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PATCH 1/1 drm/radeon: fix 32-bit compile after dpm merge

From: Dave Airlie <[email protected]>

feel free to split this back up and merge it into the individual commits.

should probably also confirm its doing sane things.

Signed-off-by Dave Airlie <[email protected]>
---
 drivers/gpu/drm/radeon/ni_dpm.c    |   10 +++++-----
 drivers/gpu/drm/radeon/rv730_dpm.c |    6 +++---
 drivers/gpu/drm/radeon/rv740_dpm.c |    6 +++---
 drivers/gpu/drm/radeon/rv770_dpm.c |    6 +++---
 drivers/gpu/drm/radeon/si_dpm.c    |   11 ++++++-----
 5 files changed, 20 insertions(+), 19 deletions(-)
drivers/gpu/drm/radeon/ni_dpm.c +5 -5
index ee82495..d547c42 100644
@@ -1376,8 +1376,8 @@ static u32 ni_calculate_power_boost_limit(struct radeon_device *rdev,
 		if (ret)
 			return 0;
 
-		tmp = ((u64)near_tdp_limit * ((u64)std_vddc_med * (u64)std_vddc_med) * 90) /
-			((u64)std_vddc_high * (u64)std_vddc_high * 100);
+		tmp = ((u64)near_tdp_limit * ((u64)std_vddc_med * (u64)std_vddc_med) * 90);
+		do_div(tmp, ((u64)std_vddc_high * (u64)std_vddc_high * 100));
 		if (tmp >> 32)
 			return 0;
 		power_boost_limit = (u32)tmp;

@@ -1978,9 +1978,9 @@ static int ni_calculate_sclk_params(struct radeon_device *rdev,
 
 	reference_divider = 1 + dividers.ref_div;
 
-	tmp = (u64) engine_clock * reference_divider * dividers.post_div;
-
-	fbdiv = (u32) ((16384 * tmp) / reference_clock);
+	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
+	do_div(tmp, reference_clock);
+	fbdiv = (u32) tmp;
 
 	spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
drivers/gpu/drm/radeon/rv730_dpm.c +3 -3
index b23be71..3f5e1cf 100644
@@ -67,9 +67,9 @@ int rv730_populate_sclk_value(struct radeon_device *rdev,
 	else
 		post_divider = 1;
 
-	tmp = (u64) engine_clock * reference_divider * post_divider;
-
-	fbdiv = (u32) ((16384 * tmp) / reference_clock);
+	tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
+	do_div(tmp, reference_clock);
+	fbdiv = (u32) tmp;
 
 	/* set up registers */
 	if (dividers.enable_post_div)
drivers/gpu/drm/radeon/rv740_dpm.c +3 -3
index 7aa1608..c4c8da5 100644
@@ -141,9 +141,9 @@ int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
 
 	reference_divider = 1 + dividers.ref_div;
 
-	tmp = (u64) engine_clock * reference_divider * dividers.post_div;
-
-	fbdiv = (u32) ((16384 * tmp) / reference_clock);
+	tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
+	do_div(tmp, reference_clock);
+	fbdiv = (u32) tmp;
 
 	spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
drivers/gpu/drm/radeon/rv770_dpm.c +3 -3
index 038c013..e58f8b6 100644
@@ -511,9 +511,9 @@ static int rv770_populate_sclk_value(struct radeon_device *rdev,
 	else
 		post_divider = 1;
 
-	tmp = (u64) engine_clock * reference_divider * post_divider;
-
-	fbdiv = (u32) ((16384 * tmp) / reference_clock);
+	tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
+	do_div(tmp, reference_clock);
+	fbdiv = (u32) tmp;
 
 	if (dividers.enable_post_div)
 		spll_func_cntl |= SPLL_DIVEN;
drivers/gpu/drm/radeon/si_dpm.c +6 -5
index 4c5b258..98450d8 100644
@@ -2243,8 +2243,9 @@ static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
 	if ((prev_vddc == 0) || (curr_vddc == 0))
 		return 0;
 
-	pwr_efficiency_ratio = ((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin) /
-				(u64)1000) / (prev_vddc * prev_vddc);
+	pwr_efficiency_ratio = (u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin);
+	do_div(pwr_efficiency_ratio, 1000);
+	do_div(pwr_efficiency_ratio, (prev_vddc * prev_vddc));
 
 	if (pwr_efficiency_ratio > (u64)0xFFFF)
 		return 0;

@@ -4532,9 +4533,9 @@ static int si_calculate_sclk_params(struct radeon_device *rdev,
 
 	reference_divider = 1 + dividers.ref_div;
 
-	tmp = (uint64_t) engine_clock * reference_divider * dividers.post_div;
-
-	fbdiv = (u32) ((16384 * tmp) / reference_clock);
+	tmp = engine_clock * reference_divider * dividers.post_div * 16384;
+	do_div(tmp, reference_clock);
+	fbdiv = (u32) tmp;
 
 	spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
 	spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
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