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socfpga: Adding configuration for development kit

PATCH Superseded Chin Liang See 2 participants 2 messages Jul 1, 2013 – Jul 2, 2013

v4 of 6 Superseded Latest is v6 →

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Chin Liang See

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#0 lore raw

PATCH v4 1/1 socfpga: Adding configuration for development kit

socfpga: Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit

Signed-off-by Chin Liang See <[email protected]>

---
Changes for v2:
- Fixed the word wrap issue within patch
Changes for v3:
- Fixed the long subject of the patch
Changes for v4:
- Added change log for each revision change

 include/configs/socfpga_cyclone5.h |   28 +++++++++++++++++++++-------
 1 file changed, 21 insertions(+), 7 deletions(-)
(quoted diff) +0 -0

b/include/configs/socfpga_cyclone5.h
index 5633d2a..be3799b 100644

include/configs/socfpga_cyclone5.h +8 -6
@@ -22,6 +22,8 @@
 /*
  * High level configuration
  */
+/* Virtual target or real hardware */
+#define CONFIG_SOCFPGA_VIRTUAL_TARGET
 
 #define CONFIG_ARMV7
 #define CONFIG_L2_OFF

@@ -32,11 +34,12 @@
 #define CONFIG_SINGLE_BOOTLOADER
 #define CONFIG_SOCFPGA
 
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE		0x08000040
-#define V_NS16550_CLK			1000000
-#define CONFIG_BAUDRATE			57600
-#define CONFIG_SYS_HZ			1000
-#define CONFIG_TIMER_CLOCK_KHZ		2400
+#else
+#define CONFIG_SYS_TEXT_BASE		0x01000040
+#endif
 #define CONFIG_SYS_LOAD_ADDR		0x7fc0
 
 /* Console I/O Buffer Size */

@@ -165,7 +168,7 @@
 /* SDRAM Bank #1 */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 /* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE		0x80000000
+#define PHYS_SDRAM_1_SIZE		0x40000000
 
 #define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_START	0x00000000

@@ -181,8 +184,13 @@
 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
 #define CONFIG_CONS_INDEX               1
 #define CONFIG_SYS_NS16550_COM1		UART0_BASE
-
 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,

115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK 1000000
+#else
+#define V_NS16550_CLK 100000000
+#endif
+#define CONFIG_BAUDRATE 115200

/*
* FLASH
@@ -195,9 +203,15 @@
/* This timer use eosc1 where the clock frequency is fixed
* throughout any condition */
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-
/* reload value when timer count to zero */
#define TIMER_LOAD_VAL 0xFFFFFFFF
+/* Timer info */
+#define CONFIG_SYS_HZ 1000
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_TIMER_CLOCK_KHZ 25000
+#endif

#define CONFIG_ENV_IS_NOWHERE

Signature · 1 line
1.7.9.5
#1 lore raw

PATCH v4 1/1 socfpga: Adding configuration for development kit

Quoted 4 lines · Chin Liang See

socfpga: Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit

Signed-off-by Chin Liang See <[email protected]>

Looks good.

Reviewed-by Pavel Machek <[email protected]>

Thanks,
Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html