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powerpc/85xx: Add C29x SoC support

PATCH Superseded Po Liu 2 participants 4 messages Jul 2, 2013 – Jul 4, 2013 PowerPC

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Po Liu

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PATCH v3 1/2 powerpc/85xx: Add C29x SoC support

From: Mingkai Hu <[email protected]>

The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features:

- 512K L2 Cache/SRAM and 512 KB platform SRAM
- DDR3/DDR3L 32bit DDR controller
- One PCI express (x1, x2, x4) Gen 2.0 Controller
- Trust Architecture 2.0
- SEC6.0 engine

Signed-off-by Mingkai Hu <[email protected]>
Signed-off-by Po Liu <[email protected]>

---
Changes for v2:
- Remove define CONFIG_C291/CONFIG_C292/CONFIG_C293, replace with CONFIG_C29X
Changes for v3:
- Replace CONFIG_C29X with CONFIG_PPC_C29X

 arch/powerpc/cpu/mpc85xx/Makefile         |  2 +
 arch/powerpc/cpu/mpc85xx/c29x_serdes.c    | 65 +++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc8xxx/cpu.c            |  3 ++
 arch/powerpc/include/asm/config_mpc85xx.h | 12 ++++++
 arch/powerpc/include/asm/fsl_law.h        |  1 +
 arch/powerpc/include/asm/immap_85xx.h     | 23 +++++++++++
 arch/powerpc/include/asm/processor.h      |  3 ++
 7 files changed, 109 insertions(+)
 create mode 100644 arch/powerpc/cpu/mpc85xx/c29x_serdes.c
arch/powerpc/cpu/mpc85xx/Makefile +2 -0
index 4669883..3cb2a78 100644
@@ -62,6 +62,7 @@ COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
 COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
 
 # supports ddr1/2/3
+COBJS-$(CONFIG_PPC_C29X)	+= ddr-gen3.o
 COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
 COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
 COBJS-$(CONFIG_MPC8569)	+= ddr-gen3.o

@@ -116,6 +117,7 @@ COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
 COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 
 # SoC specific SERDES support
+COBJS-$(CONFIG_PPC_C29X)	+= c29x_serdes.o
 COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
 COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o
 COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
arch/powerpc/cpu/mpc85xx/c29x_serdes.c new file +65 -0

65 lines not on this page · raw message

arch/powerpc/cpu/mpc8xxx/cpu.c +3 -0
index bc26855..2eed872 100644
@@ -95,6 +95,9 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 	CPU_TYPE_ENTRY(BSC9132, 9132, 2),
 	CPU_TYPE_ENTRY(BSC9232, 9232, 2),
+	CPU_TYPE_ENTRY(C291, C291, 1),
+	CPU_TYPE_ENTRY(C292, C292, 1),
+	CPU_TYPE_ENTRY(C293, C293, 1),
 #elif defined(CONFIG_MPC86xx)
 	CPU_TYPE_ENTRY(8610, 8610, 1),
 	CPU_TYPE_ENTRY(8641, 8641, 2),
arch/powerpc/include/asm/config_mpc85xx.h +12 -0
index 1d46b14..3f48802 100644
@@ -626,6 +626,18 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
+#elif defined(CONFIG_PPC_C29X)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB	3
+#define CONFIG_TSECV2_1
+#define CONFIG_SYS_FSL_SEC_COMPAT	6
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+
 #else
 #error Processor type not defined for this platform
 #endif
arch/powerpc/include/asm/fsl_law.h +1 -0
index bea1636..9eb3e13 100644
@@ -92,6 +92,7 @@ enum law_trgt_if {
 	LAW_TRGT_IF_LBC = 0x04,
 	LAW_TRGT_IF_CCSR = 0x08,
 	LAW_TRGT_IF_DSP_CCSR = 0x09,
+	LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
 	LAW_TRGT_IF_DDR_INTRLV = 0x0b,
 	LAW_TRGT_IF_RIO = 0x0c,
 	LAW_TRGT_IF_RIO_2 = 0x0d,
arch/powerpc/include/asm/immap_85xx.h +23 -0
index db70d04..af3853a 100644
@@ -2147,6 +2147,11 @@ typedef struct ccsr_gur {
 #ifdef CONFIG_MPC8536
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x3e000000
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	25
+#elif defined(CONFIG_PPC_C29X)
+#define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	(9 - ((gur->pordevsr2 \
+					& MPC85xx_PORDEVSR2_DDR_SPD_0) \
+					>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
 #else
 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00

@@ -2194,6 +2199,9 @@ typedef struct ccsr_gur {
 #elif defined(CONFIG_BSC9132)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00FE0000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	17
+#elif defined(CONFIG_PPC_C29X)
+#define MPC85xx_PORDEVSR_IO_SEL		0x00e00000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
 #else
 #define MPC85xx_PORDEVSR_IO_SEL		0x00780000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	19

@@ -2209,6 +2217,10 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
 	u32	pordbgmsr;	/* POR debug mode status */
 	u32	pordevsr2;	/* POR I/O device status 2 */
+#if defined(CONFIG_PPC_C29X)
+#define MPC85xx_PORDEVSR2_DDR_SPD_0	0x00000008
+#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT	3
+#endif
 /* The 8544 RM says this is bit 26, but it's really bit 24 */
 #define MPC85xx_PORDEVSR2_SEC_CFG	0x00000080
 	u8	res1[8];

@@ -2355,6 +2367,11 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR0_SIM_SEL_MASK	0x0003b000
 #define MPC85xx_PMUXCR0_SIM_SEL		0x00014000
 #endif
+#if defined(CONFIG_PPC_C29X)
+#define MPC85xx_PMUXCR_SPI_MASK			0x00000300
+#define MPC85xx_PMUXCR_SPI			0x00000000
+#define MPC85xx_PMUXCR_SPI_GPIO			0x00000100
+#endif
 	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
 #define MPC85xx_PMUXCR2_UART_GPIO		0x40000000

@@ -3024,12 +3041,18 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x23000
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET			0xB0000
+#elif defined(CONFIG_TSECV2_1)
+#define CONFIG_SYS_TSEC1_OFFSET			0x10000
 #else
 #define CONFIG_SYS_TSEC1_OFFSET			0x24000
 #endif
 #define CONFIG_SYS_MDIO1_OFFSET			0x24000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
+#if defined(CONFIG_PPC_C29X)
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x80000
+#else
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x30000
+#endif
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
 #define CONFIG_SYS_SNVS_OFFSET			0xE6000
arch/powerpc/include/asm/processor.h +3 -0
index 56b22d8..64a6f9c 100644
@@ -1119,6 +1119,9 @@
 #define SVR_T4240	0x824000
 #define SVR_T4120	0x824001
 #define SVR_T4160	0x824100
+#define SVR_C291	0x850000
+#define SVR_C292	0x850020
+#define SVR_C293	0x850030
 #define SVR_B4860	0X868000
 #define SVR_G4860	0x868001
 #define SVR_G4060	0x868003
Signature · 1 line
1.8.0
author
#1 lore raw

PATCH v3 2/2 powerpc/c29xpcie: add support for C29XPCIE board

From: Mingkai Hu <[email protected]>

C29XPCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. It includes C293PCIE board, C293PCIE board and C291PCIE board.

- 512KB platform SRAM in addition to 512K L2 Cache/SRAM
- 512MB soldered DDR3 32bit memory
- CPLD System Logic
- 64MB x16 NOR flash and 4GB x8 NAND flash
- 16MB SPI flash

Signed-off-by Mingkai Hu <[email protected]>
Singed-off-by Po Liu <[email protected]>

---
Changes for v2:
- Remove define CONFIG_C291/CONFIG_C292/CONFIG_C293, replace with CONFIG_C29X
- Adjust the TLB config mode
- Add SEC node removal method by check the CPU SVR
- Clean up the C29XPCIE.h file
Changes for v3:
- Replace CONFIG_C29X with CONFIG_PPC_C29X

 board/freescale/c29xpcie/Makefile   |  34 +++
 board/freescale/c29xpcie/c29xpcie.c | 150 +++++++++++
 board/freescale/c29xpcie/cpld.c     | 155 ++++++++++++
 board/freescale/c29xpcie/cpld.h     |  53 ++++
 board/freescale/c29xpcie/ddr.c      |  89 +++++++
 board/freescale/c29xpcie/law.c      |  22 ++
 board/freescale/c29xpcie/tlb.c      |  89 +++++++
 boards.cfg                          |   2 +
 include/configs/C29XPCIE.h          | 490 ++++++++++++++++++++++++++++++++++++
 9 files changed, 1084 insertions(+)
 create mode 100644 board/freescale/c29xpcie/Makefile
 create mode 100644 board/freescale/c29xpcie/c29xpcie.c
 create mode 100644 board/freescale/c29xpcie/cpld.c
 create mode 100644 board/freescale/c29xpcie/cpld.h
 create mode 100644 board/freescale/c29xpcie/ddr.c
 create mode 100644 board/freescale/c29xpcie/law.c
 create mode 100644 board/freescale/c29xpcie/tlb.c
 create mode 100644 include/configs/C29XPCIE.h
board/freescale/c29xpcie/Makefile new file +34 -0
new file mode 100644
index 0000000..15bef9a
@@ -0,0 +1,34 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= cpld.o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
board/freescale/c29xpcie/c29xpcie.c new file +150 -0

150 lines not on this page · raw message

board/freescale/c29xpcie/cpld.c new file +155 -0

155 lines not on this page · raw message

board/freescale/c29xpcie/cpld.h new file +53 -0

53 lines not on this page · raw message

board/freescale/c29xpcie/ddr.c new file +89 -0

89 lines not on this page · raw message

board/freescale/c29xpcie/law.c new file +22 -0
new file mode 100644
index 0000000..064fa71
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
+					LAW_TRGT_IF_PLATFORM_SRAM),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
board/freescale/c29xpcie/tlb.c new file +89 -0

89 lines not on this page · raw message

boards.cfg +2 -0
index c0c4282..4c68e9f 100644
@@ -771,6 +771,8 @@ MPC8569MDS_NAND              powerpc     mpc85xx     mpc8569mds          freesca
 MPC8572DS                    powerpc     mpc85xx     mpc8572ds           freescale      -           MPC8572DS
 MPC8572DS_36BIT              powerpc     mpc85xx     mpc8572ds           freescale      -           MPC8572DS:36BIT
 MPC8572DS_NAND               powerpc     mpc85xx     mpc8572ds           freescale      -           MPC8572DS:NAND
+C29XPCIE                     powerpc     mpc85xx     c29xpcie            freescale      -           C29XPCIE:C29XPCIE,36BIT
+C29XPCIE_SPIFLASH            powerpc     mpc85xx     c29xpcie            freescale      -           C29XPCIE:C29XPCIE,36BIT,SPIFLASH
 P1010RDB_36BIT_NAND          powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB,36BIT,NAND
 P1010RDB_36BIT_NAND_SECBOOT  powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT
 P1010RDB_36BIT_NOR           powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB,36BIT
include/configs/C29XPCIE.h new file +490 -0

490 lines not on this page · raw message

Signature · 1 line
1.8.0
#2 lore raw

PATCH v3 2/2 powerpc/c29xpcie: add support for C29XPCIE board

Quoted 10 lines · Po Liu
board/freescale/c29xpcie/c29xpcie.c new file +10 -0
+int board_early_init_r(void)
+{
+	const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+

board/freescale/c29xpcie/c29xpcie.c line 70

Quoted 10 lines
board/freescale/c29xpcie/c29xpcie.c new file +10 -0
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_64M, 1);

Don't set MAS3_SX on I/O regions.

Quoted 9 lines
board/freescale/c29xpcie/c29xpcie.c new file +6 -0
+#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_del_sec(void *blob, int offset)
+{
+	int nodeoff = 0;
+
+	while ((nodeoff = fdt_node_offset_by_compat_reg(blob,

"fsl,sec-v6.0",

(quoted diff) +1 -0
+			CONFIG_SYS_CCSRBAR_PHYS +

CONFIG_SYS_FSL_SEC_OFFSET

board/freescale/c29xpcie/c29xpcie.c line 125

Quoted 5 lines
board/freescale/c29xpcie/c29xpcie.c new file +5 -0
+			+ offset * 0x20000)) >= 0) {
+			fdt_del_node(blob, nodeoff);
+			offset++;
+		}
+}

Whitespace

Quoted 9 lines
board/freescale/c29xpcie/cpld.c new file +8 -0
+static u8 __cpld_read(unsigned int reg)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	return in_8(p + reg);
+}
+
+u8 cpld_read(unsigned int reg) __attribute__((weak,

alias("__cpld_read")));

board/freescale/c29xpcie/cpld.c line 44

Quoted 10 lines
board/freescale/c29xpcie/cpld.c new file +10 -0
+
+static void __cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	out_8(p + reg, value);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+	__attribute__((weak, alias("__cpld_write")));

Why does this need to be weak? Where do you expect to call cpld_read/write that isn't specific to this board? What sort of behavior could a non-board-specific caller possibly expect?

Quoted 14 lines
board/freescale/c29xpcie/cpld.c new file +14 -0
+/**
+ * Set the boot bank to the alternate bank
+ */
+void __cpld_set_altbank(u8 banksel)
+{
+	u8 reg11 = CPLD_READ(flhcsr);
+
+	switch (banksel) {
+	case 1:
+		CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
+		break;
+	case 2:
+		CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK)

board/freescale/c29xpcie/cpld.c line 69

Quoted 10 lines
board/freescale/c29xpcie/cpld.c new file +10 -0
+			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
+		break;
+	case 3:
+		CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
+		break;
+	case 4:
+		CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+			| CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
+		break;

So there's a __cpld_write, a cpld_write, *and* a CPLD_WRITE?

board/freescale/c29xpcie/cpld.h line 53

Quoted 4 lines
(quoted diff) +2 -0
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value) cpld_write(offsetof(struct cpld_data,

reg), \

board/freescale/c29xpcie/cpld.h new file +1 -0
+						value)

Ugh. Why not just initialize a pointer to CONFIG_SYS_CPLD_BASE, and use normal I/O accessors on that, just like every other driver that isn't the
p2041rdb CPLD code you copied this from?

Quoted 7 lines
(quoted diff) +2 -0
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M,

LAW_TRGT_IF_IFC),

(quoted diff) +1 -0
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K,

LAW_TRGT_IF_IFC),

(quoted diff) +1 -0
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M,

LAW_TRGT_IF_IFC),

The NAND SRAM window is 16K. There is no reason to make the LAW 1M.

board/freescale/c29xpcie/tlb.c line 35

Quoted 5 lines
board/freescale/c29xpcie/tlb.c new file +5 -0
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_4K, 1),

Comment says *I*** but code says *I*G*.

Do we still use this mapping at all?

board/freescale/c29xpcie/tlb.c line 44

Quoted 9 lines
board/freescale/c29xpcie/tlb.c new file +6 -0
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 1, BOOKE_PAGESZ_1M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE,

CONFIG_SYS_FLASH_BASE_PHYS,

board/freescale/c29xpcie/tlb.c new file +2 -0
+			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+			0, 2, BOOKE_PAGESZ_64M, 1),

Why do most of these entries have a comment but some (like this flash entry) don't? Be consistent. Probably better to remove all of these comments since they don't say anything that isn't clear from the code, and are often wrong.

Review

Quoted 4 lines
(quoted diff) +1 -0
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE,

CONFIG_SYS_NAND_BASE_PHYS,

(quoted diff) +2 -0
+			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 6, BOOKE_PAGESZ_1M, 1),

Again, this can be 16K.

board/freescale/c29xpcie/tlb.c line 75

Quoted 9 lines
board/freescale/c29xpcie/tlb.c new file +9 -0
+	/* *I*G - platform SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
+			CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 7, BOOKE_PAGESZ_256K, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
+			CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 8, BOOKE_PAGESZ_256K, 1),

Comment says *I*G but it isn't.

include/configs/C29XPCIE.h line 310

Quoted 5 lines
include/configs/C29XPCIE.h new file +5 -0
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif

Again, "Please go through this file and only retain things which actually continue to make
sense."

This is a pointless ifdef, and a pointless define of CONFIG_SYS_PROMPT_HUSH_PS2 since that's the same as the default.

Quoted 8 lines
include/configs/C29XPCIE.h new file +6 -0
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On:

Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */

Sigh.

-Scott

author
#3 lore raw

PATCH v5 1/2 powerpc/85xx: Add C29x SoC support

In reply to Po Liu

From: Mingkai Hu <[email protected]>

The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features:

- 512K L2 Cache/SRAM and 512 KB platform SRAM
- DDR3/DDR3L 32bit DDR controller
- One PCI express (x1, x2, x4) Gen 2.0 Controller
- Trust Architecture 2.0
- SEC6.0 engine

Signed-off-by Mingkai Hu <[email protected]>
Signed-off-by Po Liu <[email protected]>

---
Changes for v2:
- Remove define CONFIG_C291/CONFIG_C292/CONFIG_C293, replace with CONFIG_C29X
Changes for v3:
- Replace CONFIG_C29X with CONFIG_PPC_C29X
Changes for v4:
- None
Changes for v5:
- None

 arch/powerpc/cpu/mpc85xx/Makefile         |  2 +
 arch/powerpc/cpu/mpc85xx/c29x_serdes.c    | 65 +++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc8xxx/cpu.c            |  3 ++
 arch/powerpc/include/asm/config_mpc85xx.h | 12 ++++++
 arch/powerpc/include/asm/fsl_law.h        |  1 +
 arch/powerpc/include/asm/immap_85xx.h     | 23 +++++++++++
 arch/powerpc/include/asm/processor.h      |  3 ++
 7 files changed, 109 insertions(+)
 create mode 100644 arch/powerpc/cpu/mpc85xx/c29x_serdes.c
arch/powerpc/cpu/mpc85xx/Makefile +2 -0
index 4669883..3cb2a78 100644
@@ -62,6 +62,7 @@ COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
 COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
 
 # supports ddr1/2/3
+COBJS-$(CONFIG_PPC_C29X)	+= ddr-gen3.o
 COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
 COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
 COBJS-$(CONFIG_MPC8569)	+= ddr-gen3.o

@@ -116,6 +117,7 @@ COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
 COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 
 # SoC specific SERDES support
+COBJS-$(CONFIG_PPC_C29X)	+= c29x_serdes.o
 COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
 COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o
 COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
arch/powerpc/cpu/mpc85xx/c29x_serdes.c new file +65 -0

65 lines not on this page · raw message

arch/powerpc/cpu/mpc8xxx/cpu.c +3 -0
index bc26855..2eed872 100644
@@ -95,6 +95,9 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 	CPU_TYPE_ENTRY(BSC9132, 9132, 2),
 	CPU_TYPE_ENTRY(BSC9232, 9232, 2),
+	CPU_TYPE_ENTRY(C291, C291, 1),
+	CPU_TYPE_ENTRY(C292, C292, 1),
+	CPU_TYPE_ENTRY(C293, C293, 1),
 #elif defined(CONFIG_MPC86xx)
 	CPU_TYPE_ENTRY(8610, 8610, 1),
 	CPU_TYPE_ENTRY(8641, 8641, 2),
arch/powerpc/include/asm/config_mpc85xx.h +12 -0
index 1d46b14..3f48802 100644
@@ -626,6 +626,18 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
+#elif defined(CONFIG_PPC_C29X)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB	3
+#define CONFIG_TSECV2_1
+#define CONFIG_SYS_FSL_SEC_COMPAT	6
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+
 #else
 #error Processor type not defined for this platform
 #endif
arch/powerpc/include/asm/fsl_law.h +1 -0
index bea1636..9eb3e13 100644
@@ -92,6 +92,7 @@ enum law_trgt_if {
 	LAW_TRGT_IF_LBC = 0x04,
 	LAW_TRGT_IF_CCSR = 0x08,
 	LAW_TRGT_IF_DSP_CCSR = 0x09,
+	LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
 	LAW_TRGT_IF_DDR_INTRLV = 0x0b,
 	LAW_TRGT_IF_RIO = 0x0c,
 	LAW_TRGT_IF_RIO_2 = 0x0d,
arch/powerpc/include/asm/immap_85xx.h +23 -0
index db70d04..af3853a 100644
@@ -2147,6 +2147,11 @@ typedef struct ccsr_gur {
 #ifdef CONFIG_MPC8536
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x3e000000
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	25
+#elif defined(CONFIG_PPC_C29X)
+#define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	(9 - ((gur->pordevsr2 \
+					& MPC85xx_PORDEVSR2_DDR_SPD_0) \
+					>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
 #else
 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00

@@ -2194,6 +2199,9 @@ typedef struct ccsr_gur {
 #elif defined(CONFIG_BSC9132)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00FE0000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	17
+#elif defined(CONFIG_PPC_C29X)
+#define MPC85xx_PORDEVSR_IO_SEL		0x00e00000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
 #else
 #define MPC85xx_PORDEVSR_IO_SEL		0x00780000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	19

@@ -2209,6 +2217,10 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
 	u32	pordbgmsr;	/* POR debug mode status */
 	u32	pordevsr2;	/* POR I/O device status 2 */
+#if defined(CONFIG_PPC_C29X)
+#define MPC85xx_PORDEVSR2_DDR_SPD_0	0x00000008
+#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT	3
+#endif
 /* The 8544 RM says this is bit 26, but it's really bit 24 */
 #define MPC85xx_PORDEVSR2_SEC_CFG	0x00000080
 	u8	res1[8];

@@ -2355,6 +2367,11 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR0_SIM_SEL_MASK	0x0003b000
 #define MPC85xx_PMUXCR0_SIM_SEL		0x00014000
 #endif
+#if defined(CONFIG_PPC_C29X)
+#define MPC85xx_PMUXCR_SPI_MASK			0x00000300
+#define MPC85xx_PMUXCR_SPI			0x00000000
+#define MPC85xx_PMUXCR_SPI_GPIO			0x00000100
+#endif
 	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
 #define MPC85xx_PMUXCR2_UART_GPIO		0x40000000

@@ -3024,12 +3041,18 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x23000
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET			0xB0000
+#elif defined(CONFIG_TSECV2_1)
+#define CONFIG_SYS_TSEC1_OFFSET			0x10000
 #else
 #define CONFIG_SYS_TSEC1_OFFSET			0x24000
 #endif
 #define CONFIG_SYS_MDIO1_OFFSET			0x24000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
+#if defined(CONFIG_PPC_C29X)
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x80000
+#else
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x30000
+#endif
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
 #define CONFIG_SYS_SNVS_OFFSET			0xE6000
arch/powerpc/include/asm/processor.h +3 -0
index 56b22d8..64a6f9c 100644
@@ -1119,6 +1119,9 @@
 #define SVR_T4240	0x824000
 #define SVR_T4120	0x824001
 #define SVR_T4160	0x824100
+#define SVR_C291	0x850000
+#define SVR_C292	0x850020
+#define SVR_C293	0x850030
 #define SVR_B4860	0X868000
 #define SVR_G4860	0x868001
 #define SVR_G4060	0x868003
Signature · 1 line
1.8.0