arm: add Faraday A36x SoC platform support

From: Kuo-Jung Su <[email protected]>

To: u-boot at lists.denx.de
CC: Albert Aribaud <[email protected]>

These patches introduce Faraday A36x SoC platform support.

Here are some public documents for your reference.

http://www.faraday-tech.com/html/documentation/index.html

There is also a A369 QEMU emulator available at my github account:

    https://github.com/dantesu1218/qemu.git

Here is quick start for QEMU:

1. Download the QEMU source tree

    $ git clone -b qemu-1.3.0 https://github.com/dantesu1218/qemu.git

2. Build & Install the QEMU:

    $ ./configure --target-list=arm-softmmu
    $ make
    $ make install

3. Launch u-boot with QEMU:

    $ qemu-system-arm -M a369 -m 512M -nographic -kernel ~/u-boot-devel/u-boot

Changes for v3:
- Coding Style cleanup.
There is still one warnning reported by checkpatch.pl, however it's too deep for me to fix it.
Here is the shapshot for it:
-----------------------------------------------------
WARNING: do not add new typedefs
#9735: FILE: include/lcd.h:258:
+typedef struct vidinfo {
-----------------------------------------------------
- Drop bit fields from c struct.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Replace all the infinite wait loop with a timeout.
- Add '__iomem' to all the declaration of HW register pointers.
- cmd_boot.c: Make it a separate stand-alone patch.
- ftspi020: Make it a separate stand-alone patch.
- dma-mapping.h: Have the global data ptr declared outside functions.
- dma-mapping.h: Add #if...#else...#endif to dma_free_coherent().
- MMU/D-Cache: Drop static non-cached region, now we use map_physmem()/unmap_physmem() for dynamic mappings.
- ftmac110: Make a correction to multi-line comment style

- ftmac110: Use random MAC address while having trouble to get one from environment variables.
- ftmac110: Add comments to timing control registers.
- ftnandc021: Re-write this driver with ECC enabled and correct column address handling for OOB read/write, and fixing issused addressed by Scott.
- a36x_config: No more static global network configurations.
- a36x_config: Add a common file for the redundant configurations.

Quoted 54 lines

From: Kuo-Jung Su <[email protected]>

To: u-boot at lists.denx.de
CC: Albert Aribaud <[email protected]>

These patches introduce Faraday A36x SoC platform support.

Here are some public documents for your reference.

http://www.faraday-tech.com/html/documentation/index.html

There is also a A369 QEMU emulator available at my github account:

    https://github.com/dantesu1218/qemu.git

Here is quick start for QEMU:

1. Download the QEMU source tree

    $ git clone -b qemu-1.3.0 https://github.com/dantesu1218/qemu.git

2. Build & Install the QEMU:

    $ ./configure --target-list=arm-softmmu
    $ make
    $ make install

3. Launch u-boot with QEMU:

    $ qemu-system-arm -M a369 -m 512M -nographic -kernel ~/u-boot-devel/u-boot

Changes for v3:
- Coding Style cleanup.
There is still one warnning reported by checkpatch.pl, however it's too deep for me to fix it.
Here is the shapshot for it:
-----------------------------------------------------
WARNING: do not add new typedefs
#9735: FILE: include/lcd.h:258:
+typedef struct vidinfo {
-----------------------------------------------------
- Drop bit fields from c struct.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Replace all the infinite wait loop with a timeout.
- Add '__iomem' to all the declaration of HW register pointers.
- cmd_boot.c: Make it a separate stand-alone patch.
- ftspi020: Make it a separate stand-alone patch.
- dma-mapping.h: Have the global data ptr declared outside functions.
- dma-mapping.h: Add #if...#else...#endif to dma_free_coherent().
- MMU/D-Cache: Drop static non-cached region, now we use map_physmem()/unmap_physmem() for dynamic mappings.
- ftmac110: Make a correction to multi-line comment style

Quoted 8 lines

- ftmac110: Use random MAC address while having trouble to get one from environment variables.
- ftmac110: Add comments to timing control registers.
- ftnandc021: Re-write this driver with ECC enabled and correct column address handling for OOB read/write, and fixing issused addressed by Scott.
- a36x_config: No more static global network configurations.
- a36x_config: Add a common file for the redundant configurations.

I see a few:
/* --------------------
* Comment
*/

in various places, and I pointed it out in the net changes, but I also saw in the SPI block '100' being used as a timeout, rather than defined. Please give everything a check for magic numbers and direct numbers used as timeout, rather than a #define.

--
Tom

drivers/net/ftmac110.c new file +7 -0

+/*******************************************************************/
+/*               FTMAC110 DMA design issue                         */
+/*                                             Dante Su 2010.02.03 */
+/*                                                                 */
+/* The DMA engine has a weird restriction that its Rx DMA engine   */
+/* accepts only 16-bits aligned address, 32-bits aligned is not    */
+/* acceptable. However this restriction does not apply to Tx DMA.  */

+static char ftmac110_mac_addr[] = { 0x00, 0x41, 0x71, 0x00, 0x00, 0x52 };

drivers/net/ftmac110.h new file +15 -0

+struct ftmac110_rxd {
+	/* RXDES0 */
+#ifdef __ARMEB__
+	uint32_t owner:1; /* BIT: 31 - 1:Hardware, 0: Software */
+	uint32_t rsvd3:1;
+	uint32_t frs:1;
+	uint32_t lrs:1;
+	uint32_t rsvd2:5;
+	uint32_t error:5;
+	uint32_t bcast:1;
+	uint32_t mcast:1;
+	uint32_t rsvd1:5;
+	uint32_t len:11;
+#else
+	uint32_t len:11;

Dear Kuo-Jung Su,

Quoted 12 lines · In message <[email protected]> you wrote:

drivers/net/ftmac110.c new file +11 -0

+/*******************************************************************/
+/*               FTMAC110 DMA design issue                         */
+/*                                             Dante Su 2010.02.03 */
+/*                                                                 */
+/* The DMA engine has a weird restriction that its Rx DMA engine   */
+/* accepts only 16-bits aligned address, 32-bits aligned is not    */
+/* acceptable. However this restriction does not apply to Tx DMA.  */
+/* Conclusion:                                                     */
+/* (1) Tx DMA Buffer Address:                                      */
+/*     1 bytes aligned: Invalid                                    */
+/*     2 bytes aligned: O.K                                        */

drivers/net/ftmac110.c line 44

Quoted 6 lines

drivers/net/ftmac110.c new file +6 -0

+/*     4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)       */
+/* (2) Rx DMA Buffer Address:                                      */
+/*     1 bytes aligned: Invalid                                    */
+/*     2 bytes aligned: O.K                                        */
+/*     4 bytes aligned: Invalid                                    */
+/*******************************************************************/

Incorrect multi-line comment style. Please fix globally.

drivers/net/ftmac110.c line 64

Quoted 3 lines

drivers/net/ftmac110.c new file +3 -0

+/* Register access macros */
+#define MAC_READ(r)                  le32_to_cpu(readl(r))
+#define MAC_WRITE(v, r)              writel(cpu_to_le32(v), r)

Please drop these and use the real functions instead.

Quoted 1 line

+static char ftmac110_mac_addr[] = { 0x00, 0x41, 0x71, 0x00, 0x00, 0x52 };

NAK. We do not allow static configuration of MAC addresses.

drivers/net/ftmac110.c line 115

Quoted 3 lines

drivers/net/ftmac110.c new file +3 -0

+     ulong ts;
+     uint32_t maccr;
+     uint16_t pa, tmp;

Are you sure using uint16_t gives more efficient code than a plain int?

drivers/net/ftmac110.c line 128

Quoted 2 lines

drivers/net/ftmac110.c new file +2 -0

+     if (pa >= 32) {
+             puts("ftmac110: phy device not found!\n");

make this a debug() ?

...

drivers/net/ftmac110.c line 227

Quoted 4 lines

drivers/net/ftmac110.c new file +4 -0

+     MAC_WRITE(0x00001010, &regs->itc);
+     MAC_WRITE(0x00000001, &regs->aptc);
+     MAC_WRITE(0x00000390, &regs->dblac);
+     MAC_WRITE(0x000003FF, &regs->isr);

What do these magic numbers mean?

Quoted 20 lines

drivers/net/ftmac110.h new file +20 -0

+struct ftmac110_rxd {
+     /* RXDES0 */
+#ifdef __ARMEB__
+     uint32_t owner:1; /* BIT: 31 - 1:Hardware, 0: Software */
+     uint32_t rsvd3:1;
+     uint32_t frs:1;
+     uint32_t lrs:1;
+     uint32_t rsvd2:5;
+     uint32_t error:5;
+     uint32_t bcast:1;
+     uint32_t mcast:1;
+     uint32_t rsvd1:5;
+     uint32_t len:11;
+#else
+     uint32_t len:11;
+     uint32_t rsvd1:5;
+     uint32_t mcast:1;
+     uint32_t bcast:1;
+     uint32_t error:5;
+     uint32_t rsvd2:5;

drivers/net/ftmac110.h line 101

Quoted 5 lines

drivers/net/ftmac110.h new file +5 -0

+     uint32_t lrs:1;
+     uint32_t frs:1;
+     uint32_t rsvd3:1;
+     uint32_t owner:1; /* BIT: 31 - 1:Hardware, 0: Software */
+#endif

NAK. Please do NOT use bit fields. They are non-portable and dangerous.

Best regards,

Wolfgang Denk

--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de A year spent in artificial intelligence is enough to make one believe in God.

Dear Kuo-Jung Su,

In message <[email protected]> you wrote:
...

drivers/i2c/fti2c010.c line 27

Quoted 2 lines

drivers/i2c/fti2c010.c new file +2 -0

+#define I2C_READ(r)          le32_to_cpu(readl(r))
+#define I2C_WRITE(v, r)      writel(cpu_to_le32(v), r)

Please drop these macros and use the real functions instead.

Best regards,

Wolfgang Denk

--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Little known fact about Middle Earth: The Hobbits had a very sophi-
sticated computer network! It was a Tolkien Ring...

Dear Kuo-Jung Su,

In message <[email protected]> you wrote:
...

drivers/spi/ftssp010_spi.c line 55

Quoted 5 lines

drivers/spi/ftssp010_spi.c new file +5 -0

+/* Register access macros */
+#define SPI_READ(r)                  le32_to_cpu(readl(r))
+#define SPI_WRITE(v, r)              writel(cpu_to_le32(v), r)
+#define SPI_SETBITS(m, r)    setbits_le32(r, m)
+#define SPI_CLRBITS(m, r)    clrbits_le32(r, m)

Ad before: drop these.

Quoted 5 lines

drivers/spi/ftssp010_spi.c new file +5 -0

+#ifdef CONFIG_FTSSP010_GPIO_BASE
+#define SPI_GPIO_READ(p, r)  \
+     le32_to_cpu(readl((p)->gpio.iobase + (r)))
+#define SPI_GPIO_WRITE(p, v, r)      \
+     writel(cpu_to_le32(v), (p)->gpio.iobase + (r))

drivers/spi/ftssp010_spi.c line 66

Quoted 5 lines

drivers/spi/ftssp010_spi.c new file +5 -0

+#define SPI_GPIO_SETBITS(p, m, r)    \
+     setbits_le32((p)->gpio.iobase + (r), m)
+#define SPI_GPIO_CLRBITS(p, m, r)    \
+     clrbits_le32((p)->gpio.iobase + (r), m)
+#endif /* #ifdef CONFIG_FTSSP010_GPIO_BASE */

We do not allos I/O accesses throug base addrss plus offset. Please use proper C structs instead.

Best regards,

Wolfgang Denk

--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Sorry, but my karma just ran over your dogma.

From: Kuo-Jung Su <[email protected]>

The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF.
This patch simpily implements the SPI mode only. BTW the DMA and CS/Clock control logic has been altered since revision 1.19.0. So this patch would 1st detects the revision id of the underlying chip, and then switch to the corresponding control routines.

Signed-off-by Kuo-Jung Su <[email protected]>

---
 drivers/spi/Makefile       |    1 +
 drivers/spi/ftssp010_spi.c |  337 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/spi/ftssp010_spi.h |   86 +++++++++++
 3 files changed, 424 insertions(+)
 create mode 100644 drivers/spi/ftssp010_spi.c
 create mode 100644 drivers/spi/ftssp010_spi.h

drivers/spi/Makefile +1 -0

index d08609e..947d60e 100644
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
 COBJS-$(CONFIG_CF_SPI) += cf_spi.o
 COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
 COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
 COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 COBJS-$(CONFIG_ICH_SPI) +=  ich.o
 COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o

drivers/spi/ftssp010_spi.c new file +337 -0

new file mode 100644
index 0000000..4247c8c
@@ -0,0 +1,337 @@
+/*
+ * Faraday Multi-function Controller - SPI Mode
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <[email protected]>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <malloc.h>
+
+#include "ftssp010_spi.h"
+
+struct ftssp010_chip {
+       void    *iobase;
+       uint32_t fifo;
+       uint32_t rev;
+       uint32_t div;
+       uint32_t mode;
+
+       struct {
+               uint32_t iobase;
+               uint32_t pin;
+       } gpio;
+};
+
+static struct ftssp010_chip chip_list[] = {
+#if defined(CONFIG_FTSSP010_BASE) || defined(CONFIG_FTSSP010_BASE0)
+       {
+               .iobase = (void *)CONFIG_FTSSP010_BASE,
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+               .gpio = { CONFIG_FTSSP010_GPIO_BASE, CONFIG_FTSSP010_GPIO_PIN },
+#endif
+       },
+#endif
+#ifdef CONFIG_FTSSP010_BASE1
+       { .iobase = (void *)CONFIG_FTSSP010_BASE1, },
+#endif
+#ifdef CONFIG_FTSSP010_BASE2
+       { .iobase = (void *)CONFIG_FTSSP010_BASE2, },
+#endif
+#ifdef CONFIG_FTSSP010_BASE3
+       { .iobase = (void *)CONFIG_FTSSP010_BASE3, },
+#endif
+};
+
+/* Register access macros */
+#define SPI_READ(r)                    le32_to_cpu(readl(r))
+#define SPI_WRITE(v, r)                writel(cpu_to_le32(v), r)
+#define SPI_SETBITS(m, r)      setbits_le32(r, m)
+#define SPI_CLRBITS(m, r)      clrbits_le32(r, m)
+
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+#define SPI_GPIO_READ(p, r)    \
+       le32_to_cpu(readl((p)->gpio.iobase + (r)))
+#define SPI_GPIO_WRITE(p, v, r)        \
+       writel(cpu_to_le32(v), (p)->gpio.iobase + (r))
+#define SPI_GPIO_SETBITS(p, m, r)      \
+       setbits_le32((p)->gpio.iobase + (r), m)
+#define SPI_GPIO_CLRBITS(p, m, r)      \
+       clrbits_le32((p)->gpio.iobase + (r), m)
+#endif /* #ifdef CONFIG_FTSSP010_GPIO_BASE */
+
+static int ftssp010_spi_work_transfer_v1_19(struct ftssp010_chip *chip,
+       const void *tx_buf, void *rx_buf, int len, uint flags)
+{
+       struct ftssp010_regs *regs = chip->iobase;
+       const uint8_t *txb = tx_buf;
+       uint8_t       *rxb = rx_buf;
+
+       while (len > 0) {
+               int i, depth = min(chip->fifo >> 2, len);
+               uint32_t xmsk = 0;
+
+               if (tx_buf) {
+                       for (i = 0; i < depth; ++i) {
+                               while (!(SPI_READ(&regs->sr) & SR_TFNF))
+                                       ;
+                               SPI_WRITE(*txb++, &regs->dr);
+                       }
+                       xmsk |= CR2_TXEN | CR2_TXDOE;
+                       if ((SPI_READ(&regs->cr[2]) & xmsk) != xmsk)
+                               SPI_SETBITS(xmsk, &regs->cr[2]);
+               }
+               if (rx_buf) {
+                       xmsk |= CR2_RXEN;
+                       if ((SPI_READ(&regs->cr[2]) & xmsk) != xmsk)
+                               SPI_SETBITS(xmsk, &regs->cr[2]);
+                       for (i = 0; i < depth; ++i) {
+                               while (!SR_RFVE(SPI_READ(&regs->sr)))
+                                       ;
+                               *rxb++ = (uint8_t)SPI_READ(&regs->dr);
+                       }
+               }
+
+               len -= depth;
+       }
+
+       return 0;
+}
+
+static int ftssp010_spi_work_transfer(struct ftssp010_chip *chip,
+       const void *tx_buf, void *rx_buf, int len, uint flags)
+{
+       struct ftssp010_regs *regs = chip->iobase;
+       const uint8_t *txb = tx_buf;
+       uint8_t       *rxb = rx_buf;
+
+       while (len > 0) {
+               int i, depth = min(chip->fifo >> 2, len);
+               uint32_t tmp;
+
+               for (i = 0; i < depth; ++i) {
+                       while (!(SPI_READ(&regs->sr) & SR_TFNF))
+                               ;
+                       SPI_WRITE(txb ? (*txb++) : 0, &regs->dr);
+               }
+               for (i = 0; i < depth; ++i) {
+                       while (!SR_RFVE(SPI_READ(&regs->sr)))
+                               ;
+                       tmp = SPI_READ(&regs->dr);
+                       if (rxb)
+                               *rxb++ = (uint8_t)tmp;
+               }
+
+               len -= depth;
+       }
+
+       return 0;
+}
+
+/*=====================================================================*/
+/*                         Public Functions                            */
+/*=====================================================================*/
+
+/*-----------------------------------------------------------------------
+ * Determine if a SPI chipselect is valid.
+ * This function is provided by the board if the low-level SPI driver
+ * needs it to determine if a given chipselect is actually valid.
+ *
+ * Returns: 1 if bus:cs identifies a valid chip on this board, 0
+ * otherwise.
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       struct ftssp010_chip *chip;
+       struct ftssp010_regs *regs;
+       uint32_t txfifo, rxfifo;
+
+       if (bus >= ARRAY_SIZE(chip_list))
+               return 0;
+
+       chip = chip_list + bus;
+       regs = chip->iobase;
+       chip->rev = SPI_READ(&regs->revr);
+       txfifo = FEAR_TXFIFO(SPI_READ(&regs->fear));
+       rxfifo = FEAR_RXFIFO(SPI_READ(&regs->fear));
+       chip->fifo = min(txfifo, rxfifo);
+
+       printf("ftssp010: rev.=0x%08X, fifo=%d\n", chip->rev, chip->fifo);
+
+       if (chip->rev >= 0x00011900) {
+               if (cs > 3)
+                       return 0;
+       } else {
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+               if (cs > 0)
+                       return 0;
+               /* setup gpio pin as an output pin */
+               SPI_GPIO_SETBITS(chip, 1 << chip->gpio.pin, 0x08);
+#else
+               return 0;
+#endif
+       }
+
+       return 1;
+}
+
+/*-----------------------------------------------------------------------
+ * Activate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should activate the chip select
+ * to the device identified by "slave".
+ */
+void spi_cs_activate(struct spi_slave *slave)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       struct ftssp010_regs *regs = chip->iobase;
+
+       /* cs pull low */
+       if (chip->rev >= 0x00011900) {
+               SPI_WRITE((slave->cs << 10) | CR2_SSPEN | CR2_TXFCLR
+                       | CR2_RXFCLR, &regs->cr[2]);
+       } else {
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+               SPI_GPIO_SETBITS(chip, 1 << chip->gpio.pin, 0x14);
+#endif
+       }
+       udelay_masked(1);
+}
+
+/*-----------------------------------------------------------------------
+ * Deactivate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should deactivate the chip
+ * select to the device identified by "slave".
+ */
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       struct ftssp010_regs *regs = chip->iobase;
+
+       /* wait until device idle */
+       while (SPI_READ(&regs->sr) & SR_BUSY)
+               ;
+
+       /* cs pull high */
+       if (chip->rev >= 0x00011900) {
+               SPI_WRITE((slave->cs << 10) | CR2_FS, &regs->cr[2]);
+       } else {
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+               SPI_GPIO_SETBITS(chip, 1 << chip->gpio.pin, 0x10);
+#endif
+       }
+       udelay_masked(1);
+}
+
+void spi_init(void)
+{
+}
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+       uint32_t clk, div;
+       struct spi_slave *ss;
+       struct ftssp010_chip *chip;
+
+       if (!spi_cs_is_valid(bus, cs))
+               return NULL;
+
+       if (mode != SPI_MODE_0) {
+               printf("ftssp010: MODE%d is not supported\n", mode);
+               return NULL;
+       }
+
+       ss = malloc(sizeof(struct spi_slave));
+       if (!ss)
+               return NULL;
+
+       ss->bus = bus;
+       ss->cs  = cs;
+
+#ifdef CONFIG_FTSSP010_SCLK
+       clk = CONFIG_FTSSP010_SCLK;
+#else
+       clk = clk_get_rate("SSP");
+#endif
+       if (max_hz > 0) {
+               for (div = 0; div < 0xFFFF; ++div) {
+                       if ((clk / (2 * (div + 1))) <= max_hz)
+                               break;
+               }
+       } else {
+               div = 7;
+       }
+
+       chip = chip_list + bus;
+       chip->div  = div;
+       chip->mode = mode;
+
+       printf("ftssp010: bus=%d, hz=%u\n", bus, (clk / (2 * (div + 1))));
+
+       return ss;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+       free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       struct ftssp010_regs *regs = chip->iobase;
+
+       SPI_WRITE(CR1_SDL(8) | CR1_CLKDIV(chip->div), &regs->cr[1]);
+
+       if (chip->rev >= 0x00011900) {
+               SPI_WRITE(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH,
+                       &regs->cr[0]);
+               SPI_WRITE(CR2_TXFCLR | CR2_RXFCLR,
+                       &regs->cr[2]);
+       } else {
+               SPI_WRITE(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO,
+                       &regs->cr[0]);
+               SPI_WRITE(CR2_TXFCLR | CR2_RXFCLR | CR2_SSPEN | CR2_TXDOE,
+                       &regs->cr[2]);
+       }
+
+       spi_cs_deactivate(slave);
+
+       return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       struct ftssp010_regs *regs = chip->iobase;
+
+       SPI_WRITE(0, &regs->cr[2]);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+                        const void *dout, void *din, unsigned long flags)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       uint32_t len = bitlen >> 3;
+
+       if (flags & SPI_XFER_BEGIN)
+               spi_cs_activate(slave);
+
+       if (chip->rev >= 0x00011900)
+               ftssp010_spi_work_transfer_v1_19(chip, dout, din, len, flags);
+       else
+               ftssp010_spi_work_transfer(chip, dout, din, len, flags);
+
+       if (flags & SPI_XFER_END)
+               spi_cs_deactivate(slave);
+
+       return 0;
+}

drivers/spi/ftssp010_spi.h new file +86 -1

new file mode 100644
index 0000000..5ad7c47
@@ -0,0 +1,86 @@
+/*
+ * Faraday Multi-function Controller - SPI Mode
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <[email protected]>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef _FTSSP010_H
+#define _FTSSP010_H
+
+/* FTSSP010 HW Registers */
+struct ftssp010_regs {
+       uint32_t cr[3];/* control register */
+       uint32_t sr;   /* status register */
+       uint32_t icr;  /* interrupt control register */
+       uint32_t isr;  /* interrupt status register */
+       uint32_t dr;   /* data register */
+       uint32_t rsvd[17];
+       uint32_t revr; /* revision register */
+       uint32_t fear; /* feature register */
+};
+
+/* Control register 0  */
+#define CR0_FFMT_MASK       (7 << 12)
+#define CR0_FFMT_SSP        (0 << 12)
+#define CR0_FFMT_SPI        (1 << 12)
+#define CR0_FFMT_MICROWIRE  (2 << 12)
+#define CR0_FFMT_I2S        (3 << 12)
+#define CR0_FFMT_AC97       (4 << 12)
+#define CR0_FLASH           (1 << 11)
+#define CR0_FSDIST(x)       (((x) & 0x03) << 8)
+#define CR0_LBM             (1 << 7)  /* Loopback mode */
+#define CR0_LSB             (1 << 6)  /* LSB first */
+#define CR0_FSPO            (1 << 5)  /* Frame sync atcive low */
+#define CR0_FSJUSTIFY       (1 << 4)
+#define CR0_OPM_SLAVE       (0 << 2)
+#define CR0_OPM_MASTER      (3 << 2)
+#define CR0_OPM_I2S_MSST    (3 << 2)  /* Master stereo mode */
+#define CR0_OPM_I2S_MSMO    (2 << 2)  /* Master mono mode */
+#define CR0_OPM_I2S_SLST    (1 << 2)  /* Slave stereo mode */
+#define CR0_OPM_I2S_SLMO    (0 << 2)  /* Slave mono mode */
+#define CR0_SCLKPO          (1 << 1)  /* SCLK Remain HIGH */
+#define CR0_SCLKPH          (1 << 0)  /* Half CLK cycle */
+
+/* Control Register 1 */
+
+#define CR1_PDL(x)          (((x) & 0xff) << 24) /* padding length */
+#define CR1_SDL(x)          ((((x) - 1) & 0x1f) << 16) /* data length */
+#define CR1_CLKDIV(x)       ((x) & 0xffff) /*  clk divider */
+
+/* Control Register 2 */
+#define CR2_FSOS(x)         (((x) & 0x03) << 10)       /* FS/CS Select */
+#define CR2_FS              (1 << 9)   /* FS/CS Signal Level */
+#define CR2_TXEN            (1 << 8)   /* Tx Enable */
+#define CR2_RXEN            (1 << 7)   /* Rx Enable */
+#define CR2_SSPRST          (1 << 6)   /* SSP reset */
+#define CR2_TXFCLR          (1 << 3)   /* TX FIFO Clear */
+#define CR2_RXFCLR          (1 << 2)   /* RX FIFO Clear */
+#define CR2_TXDOE           (1 << 1)   /* TX Data Output Enable */
+#define CR2_SSPEN           (1 << 0)   /* SSP Enable */
+
+/*
+ * Status Register
+ */
+#define SR_RFF       (1 << 0) /* receive FIFO full */
+#define SR_TFNF      (1 << 1) /* transmit FIFO not full */
+#define SR_BUSY      (1 << 2) /* bus is busy */
+#define SR_RFVE(reg) (((reg) >> 4) & 0x1f)  /* receive  FIFO valid entries */
+#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* transmit FIFO valid entries */
+
+/*
+ * Feature Register
+ */
+#define FEAR_WIDTH(reg)  ((((reg) >>  0) & 0xff) + 1)
+#define FEAR_RXFIFO(reg) ((((reg) >>  8) & 0xff) + 1)
+#define FEAR_TXFIFO(reg) ((((reg) >> 16) & 0xff) + 1)
+#define FEAR_AC97        (1 << 24)
+#define FEAR_I2S         (1 << 25)
+#define FEAR_SPI_MWR     (1 << 26)
+#define FEAR_SSP         (1 << 27)
+#define FEAR_SPDIF       (1 << 28)
+
+#endif
--

1.7.9.5

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Hi Kuo-Jung Su,

Please fix the comments I sent on v4.
http://patchwork.ozlabs.org/patch/242023/

Feel free to ask for any quires.

Thanks,
Jagan.

Quoted 474 lines · Kuo-Jung Su

From: Kuo-Jung Su <[email protected]>

The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF.
This patch simpily implements the SPI mode only. BTW the DMA and CS/Clock control logic has been altered since revision 1.19.0. So this patch would 1st detects the revision id of the underlying chip, and then switch to the corresponding control routines.

Signed-off-by Kuo-Jung Su <[email protected]>

---
 drivers/spi/Makefile       |    1 +
 drivers/spi/ftssp010_spi.c |  337 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/spi/ftssp010_spi.h |   86 +++++++++++
 3 files changed, 424 insertions(+)
 create mode 100644 drivers/spi/ftssp010_spi.c
 create mode 100644 drivers/spi/ftssp010_spi.h

drivers/spi/Makefile +1 -0

index d08609e..947d60e 100644
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
 COBJS-$(CONFIG_CF_SPI) += cf_spi.o
 COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
 COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
 COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 COBJS-$(CONFIG_ICH_SPI) +=  ich.o
 COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o

drivers/spi/ftssp010_spi.c new file +337 -0

new file mode 100644
index 0000000..4247c8c
@@ -0,0 +1,337 @@
+/*
+ * Faraday Multi-function Controller - SPI Mode
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <[email protected]>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <malloc.h>
+
+#include "ftssp010_spi.h"
+
+struct ftssp010_chip {
+       void    *iobase;
+       uint32_t fifo;
+       uint32_t rev;
+       uint32_t div;
+       uint32_t mode;
+
+       struct {
+               uint32_t iobase;
+               uint32_t pin;
+       } gpio;
+};
+
+static struct ftssp010_chip chip_list[] = {
+#if defined(CONFIG_FTSSP010_BASE) || defined(CONFIG_FTSSP010_BASE0)
+       {
+               .iobase = (void *)CONFIG_FTSSP010_BASE,
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+               .gpio = { CONFIG_FTSSP010_GPIO_BASE, CONFIG_FTSSP010_GPIO_PIN },
+#endif
+       },
+#endif
+#ifdef CONFIG_FTSSP010_BASE1
+       { .iobase = (void *)CONFIG_FTSSP010_BASE1, },
+#endif
+#ifdef CONFIG_FTSSP010_BASE2
+       { .iobase = (void *)CONFIG_FTSSP010_BASE2, },
+#endif
+#ifdef CONFIG_FTSSP010_BASE3
+       { .iobase = (void *)CONFIG_FTSSP010_BASE3, },
+#endif
+};
+
+/* Register access macros */
+#define SPI_READ(r)                    le32_to_cpu(readl(r))
+#define SPI_WRITE(v, r)                writel(cpu_to_le32(v), r)
+#define SPI_SETBITS(m, r)      setbits_le32(r, m)
+#define SPI_CLRBITS(m, r)      clrbits_le32(r, m)
+
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+#define SPI_GPIO_READ(p, r)    \
+       le32_to_cpu(readl((p)->gpio.iobase + (r)))
+#define SPI_GPIO_WRITE(p, v, r)        \
+       writel(cpu_to_le32(v), (p)->gpio.iobase + (r))
+#define SPI_GPIO_SETBITS(p, m, r)      \
+       setbits_le32((p)->gpio.iobase + (r), m)
+#define SPI_GPIO_CLRBITS(p, m, r)      \
+       clrbits_le32((p)->gpio.iobase + (r), m)
+#endif /* #ifdef CONFIG_FTSSP010_GPIO_BASE */
+
+static int ftssp010_spi_work_transfer_v1_19(struct ftssp010_chip *chip,
+       const void *tx_buf, void *rx_buf, int len, uint flags)
+{
+       struct ftssp010_regs *regs = chip->iobase;
+       const uint8_t *txb = tx_buf;
+       uint8_t       *rxb = rx_buf;
+
+       while (len > 0) {
+               int i, depth = min(chip->fifo >> 2, len);
+               uint32_t xmsk = 0;
+
+               if (tx_buf) {
+                       for (i = 0; i < depth; ++i) {
+                               while (!(SPI_READ(&regs->sr) & SR_TFNF))
+                                       ;
+                               SPI_WRITE(*txb++, &regs->dr);
+                       }
+                       xmsk |= CR2_TXEN | CR2_TXDOE;
+                       if ((SPI_READ(&regs->cr[2]) & xmsk) != xmsk)
+                               SPI_SETBITS(xmsk, &regs->cr[2]);
+               }
+               if (rx_buf) {
+                       xmsk |= CR2_RXEN;
+                       if ((SPI_READ(&regs->cr[2]) & xmsk) != xmsk)
+                               SPI_SETBITS(xmsk, &regs->cr[2]);
+                       for (i = 0; i < depth; ++i) {
+                               while (!SR_RFVE(SPI_READ(&regs->sr)))
+                                       ;
+                               *rxb++ = (uint8_t)SPI_READ(&regs->dr);
+                       }
+               }
+
+               len -= depth;
+       }
+
+       return 0;
+}
+
+static int ftssp010_spi_work_transfer(struct ftssp010_chip *chip,
+       const void *tx_buf, void *rx_buf, int len, uint flags)
+{
+       struct ftssp010_regs *regs = chip->iobase;
+       const uint8_t *txb = tx_buf;
+       uint8_t       *rxb = rx_buf;
+
+       while (len > 0) {
+               int i, depth = min(chip->fifo >> 2, len);
+               uint32_t tmp;
+
+               for (i = 0; i < depth; ++i) {
+                       while (!(SPI_READ(&regs->sr) & SR_TFNF))
+                               ;
+                       SPI_WRITE(txb ? (*txb++) : 0, &regs->dr);
+               }
+               for (i = 0; i < depth; ++i) {
+                       while (!SR_RFVE(SPI_READ(&regs->sr)))
+                               ;
+                       tmp = SPI_READ(&regs->dr);
+                       if (rxb)
+                               *rxb++ = (uint8_t)tmp;
+               }
+
+               len -= depth;
+       }
+
+       return 0;
+}
+
+/*=====================================================================*/
+/*                         Public Functions                            */
+/*=====================================================================*/
+
+/*-----------------------------------------------------------------------
+ * Determine if a SPI chipselect is valid.
+ * This function is provided by the board if the low-level SPI driver
+ * needs it to determine if a given chipselect is actually valid.
+ *
+ * Returns: 1 if bus:cs identifies a valid chip on this board, 0
+ * otherwise.
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       struct ftssp010_chip *chip;
+       struct ftssp010_regs *regs;
+       uint32_t txfifo, rxfifo;
+
+       if (bus >= ARRAY_SIZE(chip_list))
+               return 0;
+
+       chip = chip_list + bus;
+       regs = chip->iobase;
+       chip->rev = SPI_READ(&regs->revr);
+       txfifo = FEAR_TXFIFO(SPI_READ(&regs->fear));
+       rxfifo = FEAR_RXFIFO(SPI_READ(&regs->fear));
+       chip->fifo = min(txfifo, rxfifo);
+
+       printf("ftssp010: rev.=0x%08X, fifo=%d\n", chip->rev, chip->fifo);
+
+       if (chip->rev >= 0x00011900) {
+               if (cs > 3)
+                       return 0;
+       } else {
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+               if (cs > 0)
+                       return 0;
+               /* setup gpio pin as an output pin */
+               SPI_GPIO_SETBITS(chip, 1 << chip->gpio.pin, 0x08);
+#else
+               return 0;
+#endif
+       }
+
+       return 1;
+}
+
+/*-----------------------------------------------------------------------
+ * Activate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should activate the chip select
+ * to the device identified by "slave".
+ */
+void spi_cs_activate(struct spi_slave *slave)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       struct ftssp010_regs *regs = chip->iobase;
+
+       /* cs pull low */
+       if (chip->rev >= 0x00011900) {
+               SPI_WRITE((slave->cs << 10) | CR2_SSPEN | CR2_TXFCLR
+                       | CR2_RXFCLR, &regs->cr[2]);
+       } else {
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+               SPI_GPIO_SETBITS(chip, 1 << chip->gpio.pin, 0x14);
+#endif
+       }
+       udelay_masked(1);
+}
+
+/*-----------------------------------------------------------------------
+ * Deactivate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should deactivate the chip
+ * select to the device identified by "slave".
+ */
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       struct ftssp010_regs *regs = chip->iobase;
+
+       /* wait until device idle */
+       while (SPI_READ(&regs->sr) & SR_BUSY)
+               ;
+
+       /* cs pull high */
+       if (chip->rev >= 0x00011900) {
+               SPI_WRITE((slave->cs << 10) | CR2_FS, &regs->cr[2]);
+       } else {
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+               SPI_GPIO_SETBITS(chip, 1 << chip->gpio.pin, 0x10);
+#endif
+       }
+       udelay_masked(1);
+}
+
+void spi_init(void)
+{
+}
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+       uint32_t clk, div;
+       struct spi_slave *ss;
+       struct ftssp010_chip *chip;
+
+       if (!spi_cs_is_valid(bus, cs))
+               return NULL;
+
+       if (mode != SPI_MODE_0) {
+               printf("ftssp010: MODE%d is not supported\n", mode);
+               return NULL;
+       }
+
+       ss = malloc(sizeof(struct spi_slave));
+       if (!ss)
+               return NULL;
+
+       ss->bus = bus;
+       ss->cs  = cs;
+
+#ifdef CONFIG_FTSSP010_SCLK
+       clk = CONFIG_FTSSP010_SCLK;
+#else
+       clk = clk_get_rate("SSP");
+#endif
+       if (max_hz > 0) {
+               for (div = 0; div < 0xFFFF; ++div) {
+                       if ((clk / (2 * (div + 1))) <= max_hz)
+                               break;
+               }
+       } else {
+               div = 7;
+       }
+
+       chip = chip_list + bus;
+       chip->div  = div;
+       chip->mode = mode;
+
+       printf("ftssp010: bus=%d, hz=%u\n", bus, (clk / (2 * (div + 1))));
+
+       return ss;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+       free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       struct ftssp010_regs *regs = chip->iobase;
+
+       SPI_WRITE(CR1_SDL(8) | CR1_CLKDIV(chip->div), &regs->cr[1]);
+
+       if (chip->rev >= 0x00011900) {
+               SPI_WRITE(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH,
+                       &regs->cr[0]);
+               SPI_WRITE(CR2_TXFCLR | CR2_RXFCLR,
+                       &regs->cr[2]);
+       } else {
+               SPI_WRITE(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO,
+                       &regs->cr[0]);
+               SPI_WRITE(CR2_TXFCLR | CR2_RXFCLR | CR2_SSPEN | CR2_TXDOE,
+                       &regs->cr[2]);
+       }
+
+       spi_cs_deactivate(slave);
+
+       return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       struct ftssp010_regs *regs = chip->iobase;
+
+       SPI_WRITE(0, &regs->cr[2]);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+                        const void *dout, void *din, unsigned long flags)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       uint32_t len = bitlen >> 3;
+
+       if (flags & SPI_XFER_BEGIN)
+               spi_cs_activate(slave);
+
+       if (chip->rev >= 0x00011900)
+               ftssp010_spi_work_transfer_v1_19(chip, dout, din, len, flags);
+       else
+               ftssp010_spi_work_transfer(chip, dout, din, len, flags);
+
+       if (flags & SPI_XFER_END)
+               spi_cs_deactivate(slave);
+
+       return 0;
+}

drivers/spi/ftssp010_spi.h new file +86 -1

new file mode 100644
index 0000000..5ad7c47
@@ -0,0 +1,86 @@
+/*
+ * Faraday Multi-function Controller - SPI Mode
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <[email protected]>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef _FTSSP010_H
+#define _FTSSP010_H
+
+/* FTSSP010 HW Registers */
+struct ftssp010_regs {
+       uint32_t cr[3];/* control register */
+       uint32_t sr;   /* status register */
+       uint32_t icr;  /* interrupt control register */
+       uint32_t isr;  /* interrupt status register */
+       uint32_t dr;   /* data register */
+       uint32_t rsvd[17];
+       uint32_t revr; /* revision register */
+       uint32_t fear; /* feature register */
+};
+
+/* Control register 0  */
+#define CR0_FFMT_MASK       (7 << 12)
+#define CR0_FFMT_SSP        (0 << 12)
+#define CR0_FFMT_SPI        (1 << 12)
+#define CR0_FFMT_MICROWIRE  (2 << 12)
+#define CR0_FFMT_I2S        (3 << 12)
+#define CR0_FFMT_AC97       (4 << 12)
+#define CR0_FLASH           (1 << 11)
+#define CR0_FSDIST(x)       (((x) & 0x03) << 8)
+#define CR0_LBM             (1 << 7)  /* Loopback mode */
+#define CR0_LSB             (1 << 6)  /* LSB first */
+#define CR0_FSPO            (1 << 5)  /* Frame sync atcive low */
+#define CR0_FSJUSTIFY       (1 << 4)
+#define CR0_OPM_SLAVE       (0 << 2)
+#define CR0_OPM_MASTER      (3 << 2)
+#define CR0_OPM_I2S_MSST    (3 << 2)  /* Master stereo mode */
+#define CR0_OPM_I2S_MSMO    (2 << 2)  /* Master mono mode */
+#define CR0_OPM_I2S_SLST    (1 << 2)  /* Slave stereo mode */
+#define CR0_OPM_I2S_SLMO    (0 << 2)  /* Slave mono mode */
+#define CR0_SCLKPO          (1 << 1)  /* SCLK Remain HIGH */
+#define CR0_SCLKPH          (1 << 0)  /* Half CLK cycle */
+
+/* Control Register 1 */
+
+#define CR1_PDL(x)          (((x) & 0xff) << 24) /* padding length */
+#define CR1_SDL(x)          ((((x) - 1) & 0x1f) << 16) /* data length */
+#define CR1_CLKDIV(x)       ((x) & 0xffff) /*  clk divider */
+
+/* Control Register 2 */
+#define CR2_FSOS(x)         (((x) & 0x03) << 10)       /* FS/CS Select */
+#define CR2_FS              (1 << 9)   /* FS/CS Signal Level */
+#define CR2_TXEN            (1 << 8)   /* Tx Enable */
+#define CR2_RXEN            (1 << 7)   /* Rx Enable */
+#define CR2_SSPRST          (1 << 6)   /* SSP reset */
+#define CR2_TXFCLR          (1 << 3)   /* TX FIFO Clear */
+#define CR2_RXFCLR          (1 << 2)   /* RX FIFO Clear */
+#define CR2_TXDOE           (1 << 1)   /* TX Data Output Enable */
+#define CR2_SSPEN           (1 << 0)   /* SSP Enable */
+
+/*
+ * Status Register
+ */
+#define SR_RFF       (1 << 0) /* receive FIFO full */
+#define SR_TFNF      (1 << 1) /* transmit FIFO not full */
+#define SR_BUSY      (1 << 2) /* bus is busy */
+#define SR_RFVE(reg) (((reg) >> 4) & 0x1f)  /* receive  FIFO valid entries */
+#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* transmit FIFO valid entries */
+
+/*
+ * Feature Register
+ */
+#define FEAR_WIDTH(reg)  ((((reg) >>  0) & 0xff) + 1)
+#define FEAR_RXFIFO(reg) ((((reg) >>  8) & 0xff) + 1)
+#define FEAR_TXFIFO(reg) ((((reg) >> 16) & 0xff) + 1)
+#define FEAR_AC97        (1 << 24)
+#define FEAR_I2S         (1 << 25)
+#define FEAR_SPI_MWR     (1 << 26)
+#define FEAR_SSP         (1 << 27)
+#define FEAR_SPDIF       (1 << 28)
+
+#endif
--

1.7.9.5

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Hi Jagan:

Thanks for the comments, but the [spi bus controller: ftssp010]

has been scheduled after the [Faraday A36x platform support] get approved.

In this way, the entire patch itself looks much better & clean.

Best Wishes

Dante Su

2013/8/8 Jagan Teki <[email protected]>:

Quoted 481 lines

Hi Kuo-Jung Su,

Please fix the comments I sent on v4.
http://patchwork.ozlabs.org/patch/242023/

Feel free to ask for any quires.

Thanks,
Jagan.

Quoted 470 lines · Kuo-Jung Su

From: Kuo-Jung Su <[email protected]>

The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF.
This patch simpily implements the SPI mode only. BTW the DMA and CS/Clock control logic has been altered since revision 1.19.0. So this patch would 1st detects the revision id of the underlying chip, and then switch to the corresponding control routines.

Signed-off-by Kuo-Jung Su <[email protected]>

---
 drivers/spi/Makefile       |    1 +
 drivers/spi/ftssp010_spi.c |  337 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/spi/ftssp010_spi.h |   86 +++++++++++
 3 files changed, 424 insertions(+)
 create mode 100644 drivers/spi/ftssp010_spi.c
 create mode 100644 drivers/spi/ftssp010_spi.h

drivers/spi/Makefile +1 -0

index d08609e..947d60e 100644
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
 COBJS-$(CONFIG_CF_SPI) += cf_spi.o
 COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
 COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
 COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 COBJS-$(CONFIG_ICH_SPI) +=  ich.o
 COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o

drivers/spi/ftssp010_spi.c new file +337 -0

new file mode 100644
index 0000000..4247c8c
@@ -0,0 +1,337 @@
+/*
+ * Faraday Multi-function Controller - SPI Mode
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <[email protected]>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <malloc.h>
+
+#include "ftssp010_spi.h"
+
+struct ftssp010_chip {
+       void    *iobase;
+       uint32_t fifo;
+       uint32_t rev;
+       uint32_t div;
+       uint32_t mode;
+
+       struct {
+               uint32_t iobase;
+               uint32_t pin;
+       } gpio;
+};
+
+static struct ftssp010_chip chip_list[] = {
+#if defined(CONFIG_FTSSP010_BASE) || defined(CONFIG_FTSSP010_BASE0)
+       {
+               .iobase = (void *)CONFIG_FTSSP010_BASE,
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+               .gpio = { CONFIG_FTSSP010_GPIO_BASE, CONFIG_FTSSP010_GPIO_PIN },
+#endif
+       },
+#endif
+#ifdef CONFIG_FTSSP010_BASE1
+       { .iobase = (void *)CONFIG_FTSSP010_BASE1, },
+#endif
+#ifdef CONFIG_FTSSP010_BASE2
+       { .iobase = (void *)CONFIG_FTSSP010_BASE2, },
+#endif
+#ifdef CONFIG_FTSSP010_BASE3
+       { .iobase = (void *)CONFIG_FTSSP010_BASE3, },
+#endif
+};
+
+/* Register access macros */
+#define SPI_READ(r)                    le32_to_cpu(readl(r))
+#define SPI_WRITE(v, r)                writel(cpu_to_le32(v), r)
+#define SPI_SETBITS(m, r)      setbits_le32(r, m)
+#define SPI_CLRBITS(m, r)      clrbits_le32(r, m)
+
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+#define SPI_GPIO_READ(p, r)    \
+       le32_to_cpu(readl((p)->gpio.iobase + (r)))
+#define SPI_GPIO_WRITE(p, v, r)        \
+       writel(cpu_to_le32(v), (p)->gpio.iobase + (r))
+#define SPI_GPIO_SETBITS(p, m, r)      \
+       setbits_le32((p)->gpio.iobase + (r), m)
+#define SPI_GPIO_CLRBITS(p, m, r)      \
+       clrbits_le32((p)->gpio.iobase + (r), m)
+#endif /* #ifdef CONFIG_FTSSP010_GPIO_BASE */
+
+static int ftssp010_spi_work_transfer_v1_19(struct ftssp010_chip *chip,
+       const void *tx_buf, void *rx_buf, int len, uint flags)
+{
+       struct ftssp010_regs *regs = chip->iobase;
+       const uint8_t *txb = tx_buf;
+       uint8_t       *rxb = rx_buf;
+
+       while (len > 0) {
+               int i, depth = min(chip->fifo >> 2, len);
+               uint32_t xmsk = 0;
+
+               if (tx_buf) {
+                       for (i = 0; i < depth; ++i) {
+                               while (!(SPI_READ(&regs->sr) & SR_TFNF))
+                                       ;
+                               SPI_WRITE(*txb++, &regs->dr);
+                       }
+                       xmsk |= CR2_TXEN | CR2_TXDOE;
+                       if ((SPI_READ(&regs->cr[2]) & xmsk) != xmsk)
+                               SPI_SETBITS(xmsk, &regs->cr[2]);
+               }
+               if (rx_buf) {
+                       xmsk |= CR2_RXEN;
+                       if ((SPI_READ(&regs->cr[2]) & xmsk) != xmsk)
+                               SPI_SETBITS(xmsk, &regs->cr[2]);
+                       for (i = 0; i < depth; ++i) {
+                               while (!SR_RFVE(SPI_READ(&regs->sr)))
+                                       ;
+                               *rxb++ = (uint8_t)SPI_READ(&regs->dr);
+                       }
+               }
+
+               len -= depth;
+       }
+
+       return 0;
+}
+
+static int ftssp010_spi_work_transfer(struct ftssp010_chip *chip,
+       const void *tx_buf, void *rx_buf, int len, uint flags)
+{
+       struct ftssp010_regs *regs = chip->iobase;
+       const uint8_t *txb = tx_buf;
+       uint8_t       *rxb = rx_buf;
+
+       while (len > 0) {
+               int i, depth = min(chip->fifo >> 2, len);
+               uint32_t tmp;
+
+               for (i = 0; i < depth; ++i) {
+                       while (!(SPI_READ(&regs->sr) & SR_TFNF))
+                               ;
+                       SPI_WRITE(txb ? (*txb++) : 0, &regs->dr);
+               }
+               for (i = 0; i < depth; ++i) {
+                       while (!SR_RFVE(SPI_READ(&regs->sr)))
+                               ;
+                       tmp = SPI_READ(&regs->dr);
+                       if (rxb)
+                               *rxb++ = (uint8_t)tmp;
+               }
+
+               len -= depth;
+       }
+
+       return 0;
+}
+
+/*=====================================================================*/
+/*                         Public Functions                            */
+/*=====================================================================*/
+
+/*-----------------------------------------------------------------------
+ * Determine if a SPI chipselect is valid.
+ * This function is provided by the board if the low-level SPI driver
+ * needs it to determine if a given chipselect is actually valid.
+ *
+ * Returns: 1 if bus:cs identifies a valid chip on this board, 0
+ * otherwise.
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       struct ftssp010_chip *chip;
+       struct ftssp010_regs *regs;
+       uint32_t txfifo, rxfifo;
+
+       if (bus >= ARRAY_SIZE(chip_list))
+               return 0;
+
+       chip = chip_list + bus;
+       regs = chip->iobase;
+       chip->rev = SPI_READ(&regs->revr);
+       txfifo = FEAR_TXFIFO(SPI_READ(&regs->fear));
+       rxfifo = FEAR_RXFIFO(SPI_READ(&regs->fear));
+       chip->fifo = min(txfifo, rxfifo);
+
+       printf("ftssp010: rev.=0x%08X, fifo=%d\n", chip->rev, chip->fifo);
+
+       if (chip->rev >= 0x00011900) {
+               if (cs > 3)
+                       return 0;
+       } else {
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+               if (cs > 0)
+                       return 0;
+               /* setup gpio pin as an output pin */
+               SPI_GPIO_SETBITS(chip, 1 << chip->gpio.pin, 0x08);
+#else
+               return 0;
+#endif
+       }
+
+       return 1;
+}
+
+/*-----------------------------------------------------------------------
+ * Activate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should activate the chip select
+ * to the device identified by "slave".
+ */
+void spi_cs_activate(struct spi_slave *slave)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       struct ftssp010_regs *regs = chip->iobase;
+
+       /* cs pull low */
+       if (chip->rev >= 0x00011900) {
+               SPI_WRITE((slave->cs << 10) | CR2_SSPEN | CR2_TXFCLR
+                       | CR2_RXFCLR, &regs->cr[2]);
+       } else {
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+               SPI_GPIO_SETBITS(chip, 1 << chip->gpio.pin, 0x14);
+#endif
+       }
+       udelay_masked(1);
+}
+
+/*-----------------------------------------------------------------------
+ * Deactivate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should deactivate the chip
+ * select to the device identified by "slave".
+ */
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       struct ftssp010_regs *regs = chip->iobase;
+
+       /* wait until device idle */
+       while (SPI_READ(&regs->sr) & SR_BUSY)
+               ;
+
+       /* cs pull high */
+       if (chip->rev >= 0x00011900) {
+               SPI_WRITE((slave->cs << 10) | CR2_FS, &regs->cr[2]);
+       } else {
+#ifdef CONFIG_FTSSP010_GPIO_BASE
+               SPI_GPIO_SETBITS(chip, 1 << chip->gpio.pin, 0x10);
+#endif
+       }
+       udelay_masked(1);
+}
+
+void spi_init(void)
+{
+}
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+       uint32_t clk, div;
+       struct spi_slave *ss;
+       struct ftssp010_chip *chip;
+
+       if (!spi_cs_is_valid(bus, cs))
+               return NULL;
+
+       if (mode != SPI_MODE_0) {
+               printf("ftssp010: MODE%d is not supported\n", mode);
+               return NULL;
+       }
+
+       ss = malloc(sizeof(struct spi_slave));
+       if (!ss)
+               return NULL;
+
+       ss->bus = bus;
+       ss->cs  = cs;
+
+#ifdef CONFIG_FTSSP010_SCLK
+       clk = CONFIG_FTSSP010_SCLK;
+#else
+       clk = clk_get_rate("SSP");
+#endif
+       if (max_hz > 0) {
+               for (div = 0; div < 0xFFFF; ++div) {
+                       if ((clk / (2 * (div + 1))) <= max_hz)
+                               break;
+               }
+       } else {
+               div = 7;
+       }
+
+       chip = chip_list + bus;
+       chip->div  = div;
+       chip->mode = mode;
+
+       printf("ftssp010: bus=%d, hz=%u\n", bus, (clk / (2 * (div + 1))));
+
+       return ss;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+       free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       struct ftssp010_regs *regs = chip->iobase;
+
+       SPI_WRITE(CR1_SDL(8) | CR1_CLKDIV(chip->div), &regs->cr[1]);
+
+       if (chip->rev >= 0x00011900) {
+               SPI_WRITE(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH,
+                       &regs->cr[0]);
+               SPI_WRITE(CR2_TXFCLR | CR2_RXFCLR,
+                       &regs->cr[2]);
+       } else {
+               SPI_WRITE(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO,
+                       &regs->cr[0]);
+               SPI_WRITE(CR2_TXFCLR | CR2_RXFCLR | CR2_SSPEN | CR2_TXDOE,
+                       &regs->cr[2]);
+       }
+
+       spi_cs_deactivate(slave);
+
+       return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       struct ftssp010_regs *regs = chip->iobase;
+
+       SPI_WRITE(0, &regs->cr[2]);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+                        const void *dout, void *din, unsigned long flags)
+{
+       struct ftssp010_chip *chip = chip_list + slave->bus;
+       uint32_t len = bitlen >> 3;
+
+       if (flags & SPI_XFER_BEGIN)
+               spi_cs_activate(slave);
+
+       if (chip->rev >= 0x00011900)
+               ftssp010_spi_work_transfer_v1_19(chip, dout, din, len, flags);
+       else
+               ftssp010_spi_work_transfer(chip, dout, din, len, flags);
+
+       if (flags & SPI_XFER_END)
+               spi_cs_deactivate(slave);
+
+       return 0;
+}

drivers/spi/ftssp010_spi.h new file +86 -1

new file mode 100644
index 0000000..5ad7c47
@@ -0,0 +1,86 @@
+/*
+ * Faraday Multi-function Controller - SPI Mode
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <[email protected]>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef _FTSSP010_H
+#define _FTSSP010_H
+
+/* FTSSP010 HW Registers */
+struct ftssp010_regs {
+       uint32_t cr[3];/* control register */
+       uint32_t sr;   /* status register */
+       uint32_t icr;  /* interrupt control register */
+       uint32_t isr;  /* interrupt status register */
+       uint32_t dr;   /* data register */
+       uint32_t rsvd[17];
+       uint32_t revr; /* revision register */
+       uint32_t fear; /* feature register */
+};
+
+/* Control register 0  */
+#define CR0_FFMT_MASK       (7 << 12)
+#define CR0_FFMT_SSP        (0 << 12)
+#define CR0_FFMT_SPI        (1 << 12)
+#define CR0_FFMT_MICROWIRE  (2 << 12)
+#define CR0_FFMT_I2S        (3 << 12)
+#define CR0_FFMT_AC97       (4 << 12)
+#define CR0_FLASH           (1 << 11)
+#define CR0_FSDIST(x)       (((x) & 0x03) << 8)
+#define CR0_LBM             (1 << 7)  /* Loopback mode */
+#define CR0_LSB             (1 << 6)  /* LSB first */
+#define CR0_FSPO            (1 << 5)  /* Frame sync atcive low */
+#define CR0_FSJUSTIFY       (1 << 4)
+#define CR0_OPM_SLAVE       (0 << 2)
+#define CR0_OPM_MASTER      (3 << 2)
+#define CR0_OPM_I2S_MSST    (3 << 2)  /* Master stereo mode */
+#define CR0_OPM_I2S_MSMO    (2 << 2)  /* Master mono mode */
+#define CR0_OPM_I2S_SLST    (1 << 2)  /* Slave stereo mode */
+#define CR0_OPM_I2S_SLMO    (0 << 2)  /* Slave mono mode */
+#define CR0_SCLKPO          (1 << 1)  /* SCLK Remain HIGH */
+#define CR0_SCLKPH          (1 << 0)  /* Half CLK cycle */
+
+/* Control Register 1 */
+
+#define CR1_PDL(x)          (((x) & 0xff) << 24) /* padding length */
+#define CR1_SDL(x)          ((((x) - 1) & 0x1f) << 16) /* data length */
+#define CR1_CLKDIV(x)       ((x) & 0xffff) /*  clk divider */
+
+/* Control Register 2 */
+#define CR2_FSOS(x)         (((x) & 0x03) << 10)       /* FS/CS Select */
+#define CR2_FS              (1 << 9)   /* FS/CS Signal Level */
+#define CR2_TXEN            (1 << 8)   /* Tx Enable */
+#define CR2_RXEN            (1 << 7)   /* Rx Enable */
+#define CR2_SSPRST          (1 << 6)   /* SSP reset */
+#define CR2_TXFCLR          (1 << 3)   /* TX FIFO Clear */
+#define CR2_RXFCLR          (1 << 2)   /* RX FIFO Clear */
+#define CR2_TXDOE           (1 << 1)   /* TX Data Output Enable */
+#define CR2_SSPEN           (1 << 0)   /* SSP Enable */
+
+/*
+ * Status Register
+ */
+#define SR_RFF       (1 << 0) /* receive FIFO full */
+#define SR_TFNF      (1 << 1) /* transmit FIFO not full */
+#define SR_BUSY      (1 << 2) /* bus is busy */
+#define SR_RFVE(reg) (((reg) >> 4) & 0x1f)  /* receive  FIFO valid entries */
+#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* transmit FIFO valid entries */
+
+/*
+ * Feature Register
+ */
+#define FEAR_WIDTH(reg)  ((((reg) >>  0) & 0xff) + 1)
+#define FEAR_RXFIFO(reg) ((((reg) >>  8) & 0xff) + 1)
+#define FEAR_TXFIFO(reg) ((((reg) >> 16) & 0xff) + 1)
+#define FEAR_AC97        (1 << 24)
+#define FEAR_I2S         (1 << 25)
+#define FEAR_SPI_MWR     (1 << 26)
+#define FEAR_SSP         (1 << 27)
+#define FEAR_SPDIF       (1 << 28)
+
+#endif
--

1.7.9.5

Quoted 4 lines

Quoted 4 lines

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Please see the comments on below patch
http://patchwork.ozlabs.org/patch/265683/

--

Quoted 5 lines

Please see the comments on below patch
http://patchwork.ozlabs.org/patch/265683/

--

Got it, thanks

--
Best wishes,
Kuo-Jung Su

From: Kuo-Jung Su <[email protected]>

Faraday FTSDC010 is a MMC/SD host controller. Although there is already a driver in current u-boot release, which is modified from eSHDC and contributed by Andes Tech. Its performance is too terrible on Faraday A36x SoC platforms, so I turn to implement this new version of driver which is 10+ times faster than the old one.

If the hardware platform is avaiable, you may modify the 'include/configs/a369_defaults.h' for performance evaluation.

Dear Kuo-Jung Su,

Quoted 9 lines · In message <[email protected]> you wrote:

From: Kuo-Jung Su <[email protected]>

Faraday FTSDC010 is a MMC/SD host controller. Although there is already a driver in current u-boot release, which is modified from eSHDC and contributed by Andes Tech. Its performance is too terrible on Faraday A36x SoC platforms, so I turn to implement this new version of driver which is 10+ times faster than the old one.

Quoted 2 lines

If the hardware platform is avaiable, you may modify the 'include/configs/a369_defaults.h' for performance evaluation.

NAK. Instead of adding another driver, please fix the problems of the original one, or replace the old one with your new, better one. We do not want to have several drivers for the same piece of hardware.

Best regards,

Wolfgang Denk

--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de "The greatest warriors are the ones who fight for peace."
- Holly Near

drivers/mtd/nand/ftnandc021.c new file +4 -0

+	switch (priv->bksz / priv->pgsz) {
+	case 16:
+		bk = 0;
+		break;

Dear Kuo-Jung Su,

In message <[email protected]> you wrote:
...

drivers/mtd/nand/ftnandc021.c line 42

Quoted 5 lines

drivers/mtd/nand/ftnandc021.c new file +5 -0

+/* Register access macros */
+#define NAND_READ(r)         le32_to_cpu(readl(r))
+#define NAND_WRITE(v, r)     writel(cpu_to_le32(v), r)
+#define NAND_SETBITS(m, r)   setbits_le32(r, m)
+#define NAND_CLRBITS(m, r)   clrbits_le32(r, m)

As before: drop these.

drivers/mtd/nand/ftnandc021.c line 91

Quoted 3 lines

drivers/mtd/nand/ftnandc021.c new file +3 -0

+     /* wait until chip ready */
+     while (NAND_READ(&regs->srr) & SRR_CHIP_RESET)
+             ;

Please add a timeout (and fix similar locations in the rest of the code if there are such).

Quoted 4 lines

drivers/mtd/nand/ftnandc021.c new file +4 -0

+     switch (priv->bksz / priv->pgsz) {
+     case 16:
+             bk = 0;
+             break;

drivers/mtd/nand/ftnandc021.c line 106

Quoted 10 lines

drivers/mtd/nand/ftnandc021.c new file +10 -0

+     case 32:
+             bk = 1;
+             break;
+     case 64:
+             bk = 2;
+             break;
+     case 128:
+             bk = 3;
+             break;
+     }

        bk = ffs(priv->bksz / priv->pgsz) - 4;

?

drivers/mtd/nand/ftnandc021.c line 130

Quoted 11 lines

drivers/mtd/nand/ftnandc021.c new file +11 -0

+     switch (priv->adrc) {
+     case 3:
+             ac = 0;
+             break;
+     case 4:
+             ac = 1;
+             break;
+     case 5:
+             ac = 2;
+             break;
+     }

        ac = priv->adrc - 3;

?

Best regards,

Wolfgang Denk

--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de "You're just jealous." "What, of an overgrown puppy with a single-
figure IQ?" - Terry Pratchett, _Moving Pictures_

drivers/mtd/nand/ftnandc021.c new file +7 -0

new file mode 100644
index 0000000..58863dc
@@ -0,0 +1,544 @@
+/*
+ * Faraday NAND Flash Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <[email protected]>
+ *
+ * This file is released under the terms of GPL v2 and any later  

version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */

drivers/mtd/nand/ftnandc021.c new file +6 -0

+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/unaligned.h>
+#include <nand.h>
+#include <malloc.h>

drivers/mtd/nand/ftnandc021.c new file +7 -0

+	uint32_t cmd;
+
+	uint32_t pgidx;
+
+	uint32_t off;
+	uint8_t  buf[256];
+

drivers/mtd/nand/ftnandc021.c new file +4 -0

+static struct nand_ecclayout ftnandc021_oob_2k = {
+	.eccbytes = 24,
+	.eccpos = {
+		40, 41, 42, 43, 44, 45, 46, 47,

drivers/mtd/nand/ftnandc021.c new file +8 -0

+	NAND_WRITE(0, &regs->ier);
+	NAND_WRITE(0, &regs->pir);
+	NAND_WRITE(0xff, &regs->bbiwr);
+	NAND_WRITE(0xffffffff, &regs->lsnwr);
+	NAND_WRITE(0xffffffff, &regs->crcwr);
+
+	if (chip->options & NAND_BUSWIDTH_16)
+		NAND_WRITE(FCR_SWCRC | FCR_IGNCRC | FCR_16BIT,  

&regs->fcr);

drivers/mtd/nand/ftnandc021.c new file +7 -0

+static inline int
+ftnandc021_ckst(struct ftnandc021_chip *priv)
+{
+	struct ftnandc021_regs *regs = priv->iobase;
+	uint32_t st = NAND_READ(&regs->idr[1]);
+
+	if (st & NAND_IOSTATUS_ERROR)

drivers/mtd/nand/ftnandc021.c new file +7 -0

+static uint8_t
+ftnandc021_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct ftnandc021_chip *priv = chip->priv;
+	struct ftnandc021_regs *regs = priv->iobase;
+	uint8_t ret = 0xff;

drivers/mtd/nand/ftnandc021.c new file +9 -0

+/**
+ * Read data from NAND controller into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ */
+static void
+ftnandc021_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{

drivers/mtd/nand/ftnandc021.c new file +2 -0

+static void
+ftnandc021_cmdfunc(struct mtd_info *mtd, unsigned cmd, int column,  

int pgidx)

drivers/mtd/nand/ftnandc021.c new file +10 -0

+{
+	struct nand_chip *chip = mtd->priv;
+	struct ftnandc021_chip *priv = chip->priv;
+	struct ftnandc021_regs *regs = priv->iobase;
+
+	priv->cmd   = cmd;
+	priv->pgidx = pgidx;
+
+	switch (cmd) {
+	case NAND_CMD_READID:	/* 0x90 */

drivers/mtd/nand/ftnandc021.c new file +13 -0

+/**
+ * hardware specific access to control-lines
+ * @mtd: MTD device structure
+ * @cmd: command to device
+ * @ctrl:
+ * NAND_NCE: bit 0 -> don't care
+ * NAND_CLE: bit 1 -> Command Latch
+ * NAND_ALE: bit 2 -> Address Latch
+ *
+ * NOTE: boards may use different bits for these!!
+ */
+static void
+ftnandc021_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int  

ctrl)

include/faraday/nand.h new file +7 -0

new file mode 100644
index 0000000..6d8efb2
@@ -0,0 +1,16 @@
+/*
+ * Faraday NAND Flash Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <[email protected]>
+ *
+ * This file is released under the terms of GPL v2 and any later  

version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */

Quoted 28 lines

drivers/mtd/nand/ftnandc021.c new file +8 -0

new file mode 100644
index 0000000..58863dc
@@ -0,0 +1,544 @@
+/*
+ * Faraday NAND Flash Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <[email protected]>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for

details.
+ */

drivers/mtd/nand/ftnandc021.c new file +11 -0

+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/unaligned.h>
+#include <nand.h>
+#include <malloc.h>
+
+#include "ftnandc021.h"
+
+/* common bitmask of nand flash status register */
+#define NAND_IOSTATUS_ERROR            BIT_MASK(0)

drivers/mtd/nand/ftnandc021.c line 25

Quoted 5 lines

drivers/mtd/nand/ftnandc021.c new file +5 -0

+#define NAND_IOSTATUS_READY            BIT_MASK(6)
+#define NAND_IOSTATUS_UNPROTCT BIT_MASK(7)
+
+struct ftnandc021_chip {
+       void    *iobase;

struct ftnandc021_regs __iomem *iobase;

Quoted 7 lines

drivers/mtd/nand/ftnandc021.c new file +7 -0

+       uint32_t cmd;
+
+       uint32_t pgidx;
+
+       uint32_t off;
+       uint8_t  buf[256];
+

drivers/mtd/nand/ftnandc021.c line 42

Quoted 10 lines

drivers/mtd/nand/ftnandc021.c new file +10 -0

+       uint32_t adrc;  /* address cycle */
+       uint32_t pgsz;  /* page size */
+       uint32_t bksz;  /* block size */
+};
+
+/* Register access macros */
+#define NAND_READ(r)           le32_to_cpu(readl(r))
+#define NAND_WRITE(v, r)       writel(cpu_to_le32(v), r)
+#define NAND_SETBITS(m, r)     setbits_le32(r, m)
+#define NAND_CLRBITS(m, r)     clrbits_le32(r, m)

Do we really need these wrappers? At least use inline functions (with lowercase names) rather than ALLCAPS MACROS, but I don't see the point once you get rid of the byteswapping, which is broken. readl() reads a little-endian register and returns a CPU-ordered value, and then you pass that CPU ordered value to a function that wants to take a little endian value and swap it again. Likewise with writel, in reverse.

Quoted 11 lines

drivers/mtd/nand/ftnandc021.c new file +11 -0

+static struct nand_ecclayout ftnandc021_oob_2k = {
+       .eccbytes = 24,
+       .eccpos = {
+               40, 41, 42, 43, 44, 45, 46, 47,
+               48, 49, 50, 51, 52, 53, 54, 55,
+               56, 57, 58, 59, 60, 61, 62, 63
+       },
+       .oobfree = {
+               {
+                       .offset = 9,
+                       .length = 3

drivers/mtd/nand/ftnandc021.c line 57

Quoted 3 lines

drivers/mtd/nand/ftnandc021.c new file +3 -0

+               }
+       }
+};

This layout doesn't seem to match what the code does. The code says there is no ECC, and only writes to specific fixed bytes of the OOB (which doesn't match 3 bytes at offset 9).

drivers/mtd/nand/ftnandc021.c line 60

Quoted 2 lines

drivers/mtd/nand/ftnandc021.c new file +2 -0

+static int
+ftnandc021_reset(struct nand_chip *chip)

We don't generally do the "function name starts in column 0" thing in U-Boot.

drivers/mtd/nand/ftnandc021.c line 63

Quoted 3 lines

drivers/mtd/nand/ftnandc021.c new file +3 -0

+{
+       struct ftnandc021_chip *priv = chip->priv;
+       struct ftnandc021_regs *regs = priv->iobase;

struct ftnandc021_regs __iomem *regs

Here and elsewhere, for "sparse" checking.

drivers/mtd/nand/ftnandc021.c line 66

Quoted 3 lines

drivers/mtd/nand/ftnandc021.c new file +3 -0

+       uint32_t bk = 2;        /* 64 pages */
+       uint32_t pg = 1;        /* 2k */
+       uint32_t ac = 2;        /* 5 */

When do you actually use these default values, other than when one of the switch statements fail to match -- which seems like it would be an error condition; even if you don't explicitly check for the error it doesn't seem good to paper over it by providing common values that might work.

drivers/mtd/nand/ftnandc021.c line 73

Quoted 6 lines

drivers/mtd/nand/ftnandc021.c new file +6 -0

+#ifdef CONFIG_FTNANDC021_ACTIMING_1
+       NAND_WRITE(CONFIG_FTNANDC021_ACTIMING_1, &regs->atr[0]);
+#endif
+#ifdef CONFIG_FTNANDC021_ACTIMING_2
+       NAND_WRITE(CONFIG_FTNANDC021_ACTIMING_2, &regs->atr[1]);
+#endif

Use CONFIG_SYS_ for things which describe hardware rather than user preference. Document all CONFIG symbols (including CONFIG_SYS symbols) in the README.

Quoted 13 lines

drivers/mtd/nand/ftnandc021.c new file +8 -0

+       NAND_WRITE(0, &regs->ier);
+       NAND_WRITE(0, &regs->pir);
+       NAND_WRITE(0xff, &regs->bbiwr);
+       NAND_WRITE(0xffffffff, &regs->lsnwr);
+       NAND_WRITE(0xffffffff, &regs->crcwr);
+
+       if (chip->options & NAND_BUSWIDTH_16)
+               NAND_WRITE(FCR_SWCRC | FCR_IGNCRC | FCR_16BIT,

&regs->fcr);

drivers/mtd/nand/ftnandc021.c new file +4 -0

+       else
+               NAND_WRITE(FCR_SWCRC | FCR_IGNCRC, &regs->fcr);
+
+       /* chip reset */

drivers/mtd/nand/ftnandc021.c line 91

Quoted 5 lines

drivers/mtd/nand/ftnandc021.c new file +5 -0

+       NAND_WRITE(SRR_CHIP_RESET, &regs->srr);
+
+       /* wait until chip ready */
+       while (NAND_READ(&regs->srr) & SRR_CHIP_RESET)
+               ;

Timeout?

drivers/mtd/nand/ftnandc021.c line 130

Quoted 11 lines

drivers/mtd/nand/ftnandc021.c new file +11 -0

+       switch (priv->adrc) {
+       case 3:
+               ac = 0;
+               break;
+       case 4:
+               ac = 1;
+               break;
+       case 5:
+               ac = 2;
+               break;
+       }

ac = priv->adrc - 3;

Quoted 14 lines

drivers/mtd/nand/ftnandc021.c new file +14 -0

+static inline int
+ftnandc021_ckst(struct ftnandc021_chip *priv)
+{
+       struct ftnandc021_regs *regs = priv->iobase;
+       uint32_t st = NAND_READ(&regs->idr[1]);
+
+       if (st & NAND_IOSTATUS_ERROR)
+               return -NAND_IOSTATUS_ERROR;
+
+       if (!(st & NAND_IOSTATUS_READY))
+               return -NAND_IOSTATUS_READY;
+
+       if (!(st & NAND_IOSTATUS_UNPROTCT))
+               return -NAND_IOSTATUS_UNPROTCT;

drivers/mtd/nand/ftnandc021.c line 139

Quoted 3 lines

drivers/mtd/nand/ftnandc021.c new file +3 -0

+
+       return 0;
+}

Why the negation of NAND_IOSTATUS_*? These aren't standard error codes... you don't even use the return value at all that I see, other than checking zero or not-zero.

Quoted 12 lines

drivers/mtd/nand/ftnandc021.c new file +12 -0

+static uint8_t
+ftnandc021_read_byte(struct mtd_info *mtd)
+{
+       struct nand_chip *chip = mtd->priv;
+       struct ftnandc021_chip *priv = chip->priv;
+       struct ftnandc021_regs *regs = priv->iobase;
+       uint8_t ret = 0xff;
+
+       switch (priv->cmd) {
+       case NAND_CMD_READID:
+       case NAND_CMD_READOOB:
+               ret = priv->buf[priv->off % 256];

drivers/mtd/nand/ftnandc021.c line 296

Quoted 5 lines

drivers/mtd/nand/ftnandc021.c new file +5 -0

+               priv->off += 1;
+               break;
+       case NAND_CMD_STATUS:
+               ret = (uint8_t)(NAND_READ(&regs->idr[1]) & 0xff);
+               break;

Why "% 256" in one case but "& 0xff" in the other?

drivers/mtd/nand/ftnandc021.c line 299

Quoted 3 lines

drivers/mtd/nand/ftnandc021.c new file +3 -0

+       default:
+               debug("ftnandc021_read_byte: unknown cmd(0x%02X)\n",
+                       priv->cmd);

This is an error, not just debug info. Use printf.

Quoted 9 lines

drivers/mtd/nand/ftnandc021.c new file +9 -0

+/**
+ * Read data from NAND controller into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ */
+static void
+ftnandc021_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{

drivers/mtd/nand/ftnandc021.c line 336

Quoted 10 lines

drivers/mtd/nand/ftnandc021.c new file +10 -0

+       struct nand_chip *chip = mtd->priv;
+       struct ftnandc021_chip *priv = chip->priv;
+       struct ftnandc021_regs *regs = priv->iobase;
+       ulong off;
+
+       /* oob read */
+       if (len <= mtd->oobsize) {
+               ftnandc021_read_oob(mtd, buf, len);
+               return;
+       }

Are you sure that a length smaller than the oobsize always means that it's an oob read?

Sorry, it's my bad, I forget to clean it up.
In my private base, it's possible to turn-on ECC support to FTNADC021 with the following issues:

1. When ECC is enabled, FTNANDC021 would always do ECC on every data block,
including the blank block(all 0xff).
What I mean is 'With ECC enabled, we'll have ECC errors on non-ecc
proected data blocks or even the blank block'.

2. FTNANDC021 would stop upon ECC errors, a chip reset is required to make it work again.

3. There are only 4 bytes data + 1 byte Bad Block Info available to software,
and because of the ECC issues above.
I'll have to use 1 byte of data to tag if this block is 'not

blank',
to make it possible to cancel the operation on these blocks to prevent the chip to be stopped. (It means that I don't have to
reset chip)
And thus if the ECC is enabled, there are only 3 data bytes
available to software,
which makes it not possible to support BBT. (BBT requres 4 data
bytes in OOB)