Skip to contentSkip to conversation

ARM: imx: Select CACHE_L2X0

PATCH In review Fabio Estevam 4 participants 10 messages Jul 8, 2013 – Jul 10, 2013

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape
lore
Share & tools
lore

Fabio Estevam

author reviewer
#0 lore raw

PATCH 1/3 ARM: imx: Select CACHE_L2X0

From: Fabio Estevam <[email protected]>

Select CACHE_L2X0 for mx31/35/51/53/6q/6sl.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/mach-imx/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)
arch/arm/mach-imx/Kconfig +5 -0
index f546560..f864af2 100644
@@ -122,6 +122,7 @@ config SOC_IMX27
 
 config SOC_IMX31
 	bool
+	select CACHE_L2X0
 	select COMMON_CLK
 	select CPU_V6
 	select IMX_HAVE_PLATFORM_MXC_RNGA

@@ -131,6 +132,7 @@ config SOC_IMX31
 config SOC_IMX35
 	bool
 	select ARCH_MXC_IOMUX_V3
+	select CACHE_L2X0
 	select COMMON_CLK
 	select CPU_V6K
 	select HAVE_EPIT

@@ -142,6 +144,7 @@ config SOC_IMX5
 	select ARCH_HAS_CPUFREQ
 	select ARCH_HAS_OPP
 	select ARCH_MXC_IOMUX_V3
+	select CACHE_L2X0
 	select COMMON_CLK
 	select CPU_V7
 	select MXC_TZIC

@@ -785,6 +788,7 @@ config SOC_IMX6Q
 	bool "i.MX6 Quad/DualLite support"
 	select ARCH_HAS_CPUFREQ
 	select ARCH_HAS_OPP
+	select CACHE_L2X0
 	select ARM_CPU_SUSPEND if PM
 	select ARM_ERRATA_754322
 	select ARM_ERRATA_764369 if SMP

@@ -815,6 +819,7 @@ config SOC_IMX6SL
 	select ARM_ERRATA_754322
 	select ARM_ERRATA_775420
 	select ARM_GIC
+	select CACHE_L2X0
 	select CPU_V7
 	select HAVE_IMX_ANATOP
 	select HAVE_IMX_GPC
Signature · 1 line
1.8.1.2
author reviewer
#1 lore raw

PATCH 2/3 ARM: mx3: Select ARM_ERRATA_411920

From: Fabio Estevam <[email protected]>

ARM_ERRATA_411920 affects mx31 and mx35, so let's enable it:

ARM_ERRATA_411920:
Invalidation of the Instruction Cache operation can fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. It does not affect the MPCore. This option enables the ARM Ltd. recommended workaround.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/mach-imx/Kconfig | 2 ++
 1 file changed, 2 insertions(+)
arch/arm/mach-imx/Kconfig +2 -0
index f864af2..a0a89c4 100644
@@ -122,6 +122,7 @@ config SOC_IMX27
 
 config SOC_IMX31
 	bool
+	select ARM_ERRATA_411920
 	select CACHE_L2X0
 	select COMMON_CLK
 	select CPU_V6

@@ -132,6 +133,7 @@ config SOC_IMX31
 config SOC_IMX35
 	bool
 	select ARCH_MXC_IOMUX_V3
+	select ARM_ERRATA_411920
 	select CACHE_L2X0
 	select COMMON_CLK
 	select CPU_V6K
Signature · 1 line
1.8.1.2
#2 lore raw

Re: [PATCH 2/3] ARM: mx3: Select ARM_ERRATA_411920

Quoted 9 lines

From: Fabio Estevam <[email protected]>

ARM_ERRATA_411920 affects mx31 and mx35, so let's enable it:

ARM_ERRATA_411920:
Invalidation of the Instruction Cache operation can fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. It does not affect the MPCore. This option enables the ARM Ltd. recommended workaround.

IMHO, enabling any errata for multiplatform kernel is not a good idea.

---

author reviewer
#3 lore raw

PATCH 3/3 ARM: imx: mm-imx3: Free l2x0_base

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

After l2x0_base has been used, we should free it.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/mach-imx/mm-imx3.c | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-imx/mm-imx3.c +1 -0
index 0884ca9..3143f5e 100644
@@ -113,6 +113,7 @@ static void __init imx3_init_l2x0(void)
 	}
 
 	l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+	iounmap(l2x0_base);
 #endif
 }
Signature · 1 line
1.8.1.2
#4 lore raw

PATCH 3/3 ARM: imx: mm-imx3: Free l2x0_base

Quoted 14 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

After l2x0_base has been used, we should free it.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/mach-imx/mm-imx3.c | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-imx/mm-imx3.c +0 -0
index 0884ca9..3143f5e 100644

arch/arm/mach-imx/mm-imx3.c static void __init imx3_init_l2x0(void) · line 116

Quoted 4 lines
arch/arm/mach-imx/mm-imx3.c +1 -0
@@ -113,6 +113,7 @@ static void __init imx3_init_l2x0(void)
 	}
 
 	l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+	iounmap(l2x0_base);

Are you sure? I think cache-l2x0 driver still needs the mapping after that.

Shawn

Quoted 6 lines
arch/arm/mach-imx/mm-imx3.c +0 -0
 #endif
 }
Signature · 1 line
1.8.1.2
author reviewer
#5 lore raw

PATCH 3/3 ARM: imx: mm-imx3: Free l2x0_base

Quoted 17 lines · Shawn Guo
Quoted 16 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

After l2x0_base has been used, we should free it.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/mach-imx/mm-imx3.c | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-imx/mm-imx3.c +0 -0
index 0884ca9..3143f5e 100644
@@ -113,6 +113,7 @@ static void __init imx3_init_l2x0(void)
      }
Quoted 5 lines

arch/arm/mach-imx/mm-imx3.c static void __init imx3_init_l2x0(void) · line 116

Quoted 2 lines
arch/arm/mach-imx/mm-imx3.c +1 -0
      l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+     iounmap(l2x0_base);

Are you sure? I think cache-l2x0 driver still needs the mapping after that.

l2x0_base is a local variable of the static imx3_init_l2x0() function, so we should iounmap it.

maintainer
#6 lore raw

PATCH 3/3 ARM: imx: mm-imx3: Free l2x0_base

Quoted 18 lines · Fabio Estevam
Quoted 17 lines · Shawn Guo
Quoted 16 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

After l2x0_base has been used, we should free it.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/mach-imx/mm-imx3.c | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-imx/mm-imx3.c +0 -0
index 0884ca9..3143f5e 100644
@@ -113,6 +113,7 @@ static void __init imx3_init_l2x0(void)
      }
Quoted 8 lines
Quoted 5 lines

arch/arm/mach-imx/mm-imx3.c static void __init imx3_init_l2x0(void) · line 116

Quoted 2 lines
arch/arm/mach-imx/mm-imx3.c +1 -0
      l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+     iounmap(l2x0_base);

Are you sure? I think cache-l2x0 driver still needs the mapping after that.

l2x0_base is a local variable of the static imx3_init_l2x0() function, so we should iounmap it.

l2x0_base is passed to l2x0_init which uses it for the outer cache maintenance operations. I wonder this doesn't crash your kernel.

Sascha

Signature · 4 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
author reviewer
#7 lore raw

PATCH 3/3 ARM: imx: mm-imx3: Free l2x0_base

Hi Sascha,

Quoted 2 lines · Sascha Hauer

l2x0_base is passed to l2x0_init which uses it for the outer cache maintenance operations. I wonder this doesn't crash your kernel.

l2x0_init() is called from arch/arm/mach-imx/mm-imx3.c first and then from arch/arm/mm/cache-l2x0.c
later.

Why do we need to call it twice?

Can't we just do:

arch/arm/mach-imx/mm-imx3.c +0 -0
index 0884ca9..94f3b4f 100644
@@ -85,7 +85,6 @@ static void __iomem *imx3_ioremap_caller(phys_addr_t

phys_addr, size_t size,
static void __init imx3_init_l2x0(void)
{
#ifdef CONFIG_CACHE_L2X0
- void __iomem *l2x0_base;
void __iomem *clkctl_base;

/*
@@ -105,14 +104,6 @@ static void __init imx3_init_l2x0(void)
} else {
pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
}
-
- l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
- if (!l2x0_base) {
- printk(KERN_ERR "remapping L2 cache area failed\n");
- return;
- }
-
- l2x0_init(l2x0_base, 0x00030024, 0x00000000);
#endif
}

author reviewer
#8 lore raw

PATCH 3/3 ARM: imx: mm-imx3: Free l2x0_base

Quoted 4 lines · Fabio Estevam

Hi Sascha,

On Tue, Jul 9, 2013 at 3:20 PM, Sascha Hauer <[email protected]> wrote:

Quoted 8 lines
Quoted 2 lines

l2x0_base is passed to l2x0_init which uses it for the outer cache maintenance operations. I wonder this doesn't crash your kernel.

l2x0_init() is called from arch/arm/mach-imx/mm-imx3.c first and then from arch/arm/mm/cache-l2x0.c
later.

Why do we need to call it twice?

Understood now, actually l2x0_init() is only called in arch/arm/mm/cache-l2x0.c for the dt case.

So all is fine with the current code.

#9 lore raw

PATCH 1/3 ARM: imx: Select CACHE_L2X0

In reply to Fabio Estevam
Quoted 4 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

Select CACHE_L2X0 for mx31/35/51/53/6q/6sl.

We should select the option from defconfig, so that the support can be disabled for whatever purpose, e.g. debugging, from menuconfig.

Shawn

Quoted 52 lines
Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/mach-imx/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)
arch/arm/mach-imx/Kconfig +5 -0
index f546560..f864af2 100644
@@ -122,6 +122,7 @@ config SOC_IMX27
 
 config SOC_IMX31
 	bool
+	select CACHE_L2X0
 	select COMMON_CLK
 	select CPU_V6
 	select IMX_HAVE_PLATFORM_MXC_RNGA

@@ -131,6 +132,7 @@ config SOC_IMX31
 config SOC_IMX35
 	bool
 	select ARCH_MXC_IOMUX_V3
+	select CACHE_L2X0
 	select COMMON_CLK
 	select CPU_V6K
 	select HAVE_EPIT

@@ -142,6 +144,7 @@ config SOC_IMX5
 	select ARCH_HAS_CPUFREQ
 	select ARCH_HAS_OPP
 	select ARCH_MXC_IOMUX_V3
+	select CACHE_L2X0
 	select COMMON_CLK
 	select CPU_V7
 	select MXC_TZIC

@@ -785,6 +788,7 @@ config SOC_IMX6Q
 	bool "i.MX6 Quad/DualLite support"
 	select ARCH_HAS_CPUFREQ
 	select ARCH_HAS_OPP
+	select CACHE_L2X0
 	select ARM_CPU_SUSPEND if PM
 	select ARM_ERRATA_754322
 	select ARM_ERRATA_764369 if SMP

@@ -815,6 +819,7 @@ config SOC_IMX6SL
 	select ARM_ERRATA_754322
 	select ARM_ERRATA_775420
 	select ARM_GIC
+	select CACHE_L2X0
 	select CPU_V7
 	select HAVE_IMX_ANATOP
 	select HAVE_IMX_GPC
Signature · 1 line
1.8.1.2