ARM: tegra114: cpuidle: add power down state
Subsystems (3)
v4 cover ARM: tegra114: cpuidle: add power down state
This series introduce CPU core power down state for CPU idle. When CPU go into this state, it saves it's context and needs a proper configuration in flow controller to power gate the CPU when CPU runs into WFI instruction. And the CPU also needs to set the IRQ as CPU power down idle wake up event in flow controller.
To prevent race conditions and ensure proper interrupt routing on Cortex-A15 CPUs when they are power-gated, add a CPU PM notifier call-back to reprogram the GIC CPU interface on PM entry. The GIC CPU interface will be reset back to its normal state by the common GIC CPU PM exit callback when the CPU wakes up.
And the Tegra114 support CPU0 hotplug function in HW physically, but it needs other software to make it work normally after we add CPU idle power down mode support. But we don't support that yet, removing them for now.
V4:
* remove the CPU0 hot plug support due to miss of SW support
* postpone to use CPUIDLE_FLAG_TIMER_STOP flag, because it still has some issues
V3:
* use CPUIDLE_FLAG_TIMER_STOP flag
V2:
* clean up the CPUidle driver to make it more generic
Joseph Lo (4):
Revert "ARM: tegra: add cpu_disable for hotplug"
ARM: tegra114: Reprogram GIC CPU interface to bypass IRQ on CPU PM
entry
ARM: tegra114: add low level support for CPU idle powered-down mode
ARM: tegra114: cpuidle: add powered-down state
arch/arm/mach-tegra/common.h | 1 - arch/arm/mach-tegra/cpuidle-tegra114.c | 51 +++++++++++++++++++++++++++++++++- arch/arm/mach-tegra/flowctrl.h | 2 ++ arch/arm/mach-tegra/hotplug.c | 11 -------- arch/arm/mach-tegra/irq.c | 40 ++++++++++++++++++++++++++ arch/arm/mach-tegra/platsmp.c | 1 - arch/arm/mach-tegra/sleep-tegra30.S | 2 ++ 7 files changed, 94 insertions(+), 14 deletions(-)
Signature · 1 line
1.8.3.2
PATCH v4 1/4 Revert "ARM: tegra: add cpu_disable for hotplug"
This reverts commit 510bb595de26f90e5bb7c4a1e2a584e38398cf00.
The Tegra114 support CPU0 hotplug function in HW physically, but it needs other software to make it work normally after we add CPU idle power down mode support. So remove them for now.
---
V4:
* remove the CPU0 hot plug support due to miss of SW support
--- arch/arm/mach-tegra/common.h | 1 - arch/arm/mach-tegra/hotplug.c | 11 ----------- arch/arm/mach-tegra/platsmp.c | 1 - 3 files changed, 13 deletions(-)
arch/arm/mach-tegra/common.h +0 -1
@@ -2,4 +2,3 @@ extern struct smp_operations tegra_smp_ops;extern int tegra_cpu_kill (unsigned int cpu);extern void tegra_cpu_die (unsigned int cpu); -extern int tegra_cpu_disable (unsigned int cpu);
arch/arm/mach-tegra/hotplug.c +0 -11
@@ -46,17 +46,6 @@ void __ref tegra_cpu_die(unsigned int cpu)BUG (); } -int tegra_cpu_disable (unsigned int cpu) -{ -switch (tegra_chip_id) { -case TEGRA20 : -case TEGRA30 : -return cpu ==0 ? -EPERM :0 ; -default : -return 0 ; - } -} -void __init tegra_hotplug_init (void ) {if (!IS_ENABLED (CONFIG_HOTPLUG_CPU ))
arch/arm/mach-tegra/platsmp.c +0 -1
@@ -196,6 +196,5 @@ struct smp_operations tegra_smp_ops __initdata = {#ifdef CONFIG_HOTPLUG_CPU .cpu_kill = tegra_cpu_kill, .cpu_die = tegra_cpu_die, - .cpu_disable = tegra_cpu_disable,#endif };
Signature · 1 line
1.8.3.2
PATCH v4 2/4 ARM: tegra114: Reprogram GIC CPU interface to bypass IRQ on CPU PM entry
In reply to Joseph LoThere is a difference between GICv1 and v2 when CPU in power management mode (aka CPU power down on Tegra). For GICv1, IRQ/FIQ interrupt lines going to CPU are same lines which are also used for wake-interrupt. Therefore, we cannot disable the GIC CPU interface if we need to use same interrupts for CPU wake purpose. This creates a race condition for CPU power off entry. Also, in GICv1, disabling GICv1 CPU interface puts GICv1 into bypass mode such that incoming legacy IRQ/FIQ are sent to CPU, which means disabling GIC CPU interface doesn't really disable IRQ/FIQ to CPU.
GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not disabled by GIC CPU interface. This is done by adding a bypass override capability when the interrupts are disabled at the CPU interface. To support this, there are four bits about IRQ/FIQ BypassDisable in CPU interface Control Register. When the IRQ/FIQ not being driver by the CPU interface, each interrupt output signal can be deasserted rather than being driven by the legacy interrupt input.
So the wake-event can be used as wakeup signals to SoC (system power controller).
To prevent race conditions and ensure proper interrupt routing on Cortex-A15 CPUs when they are power-gated, add a CPU PM notifier call-back to reprogram the GIC CPU interface on PM entry. The GIC CPU interface will be reset back to its normal state by the common GIC CPU PM exit callback when the CPU wakes up.
Based on the work by: Scott Williams <[email protected]>
---
V4:
* no change
V3:
* no change
V2:
* no change
--- arch/arm/mach-tegra/irq.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)
arch/arm/mach-tegra/irq.c +40 -0
@@ -18,10 +18,12 @@*/ #include <linux/kernel.h> +#include <linux/cpu_pm.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> #include <linux/of.h> +#include <linux/of_address.h> #include <linux/irqchip/arm-gic.h> #include <linux/syscore_ops.h>
@@ -65,6 +67,7 @@ static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS ];static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS ]; +static void __iomem *tegra_gic_cpu_base;#endif bool tegra_pending_sgi (void )
@@ -213,8 +216,43 @@ int tegra_legacy_irq_syscore_init(void)return 0 ; } + +static int tegra_gic_notifier (struct notifier_block *self, +unsigned long cmd,void *v) +{ +switch (cmd) { +case CPU_PM_ENTER : +writel_relaxed (0x1E0 , tegra_gic_cpu_base +GIC_CPU_CTRL ); +break ; + } + +return NOTIFY_OK ; +} + +static struct notifier_block tegra_gic_notifier_block = { + .notifier_call = tegra_gic_notifier, +}; + +static const struct of_device_id tegra114_dt_gic_match[]__initconst = { + { .compatible ="arm,cortex-a15-gic" }, + { } +}; + +static void tegra114_gic_cpu_pm_registration (void ) +{ +struct device_node *dn; + + dn =of_find_matching_node (NULL , tegra114_dt_gic_match); +if (!dn) +return ; + + tegra_gic_cpu_base =of_iomap (dn,1 ); + +cpu_pm_register_notifier (&tegra_gic_notifier_block); +}#else #define tegra_set_wake NULL +static void tegra114_gic_cpu_pm_registration (void ) { }#endif void __init tegra_init_irq (void )
@@ -252,4 +290,6 @@ void __init tegra_init_irq(void)if (!of_have_populated_dt ())gic_init (0 ,29 , distbase,IO_ADDRESS (TEGRA_ARM_PERIF_BASE +0x100 )); + +tegra114_gic_cpu_pm_registration (); }
Signature · 1 line
1.8.3.2
PATCH v4 2/4 ARM: tegra114: Reprogram GIC CPU interface to bypass IRQ on CPU PM entry
Quoted 26 lines · Joseph Lo
There is a difference between GICv1 and v2 when CPU in power management mode (aka CPU power down on Tegra). For GICv1, IRQ/FIQ interrupt lines going to CPU are same lines which are also used for wake-interrupt. Therefore, we cannot disable the GIC CPU interface if we need to use same interrupts for CPU wake purpose. This creates a race condition for CPU power off entry. Also, in GICv1, disabling GICv1 CPU interface puts GICv1 into bypass mode such that incoming legacy IRQ/FIQ are sent to CPU, which means disabling GIC CPU interface doesn't really disable IRQ/FIQ to CPU.
GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not disabled by GIC CPU interface. This is done by adding a bypass override capability when the interrupts are disabled at the CPU interface. To support this, there are four bits about IRQ/FIQ BypassDisable in CPU interface Control Register. When the IRQ/FIQ not being driver by the CPU interface, each interrupt output signal can be deasserted rather than being driven by the legacy interrupt input.
So the wake-event can be used as wakeup signals to SoC (system power controller).
To prevent race conditions and ensure proper interrupt routing on Cortex-A15 CPUs when they are power-gated, add a CPU PM notifier call-back to reprogram the GIC CPU interface on PM entry. The GIC CPU interface will be reset back to its normal state by the common GIC CPU PM exit callback when the CPU wakes up.
Quoted 3 lines
Based on the work by: Scott Williams <[email protected]>
Signed-off-by Joseph Lo <[email protected]>
Hi Joseph,
We've had a rather long-standing issue with PCIe and MSI related to LP2 on Tegra20. I wonder if that's somehow related to this. Given that this is marked as Tegra114 patch explicitly I suppose not, but it certainly sounds very similar to the description above.
Thierry
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PATCH v4 2/4 ARM: tegra114: Reprogram GIC CPU interface to bypass IRQ on CPU PM entry
Quoted 31 lines · Thierry Reding
* PGP Signed by an unknown key
Quoted 28 lines · Joseph Lo
There is a difference between GICv1 and v2 when CPU in power management mode (aka CPU power down on Tegra). For GICv1, IRQ/FIQ interrupt lines going to CPU are same lines which are also used for wake-interrupt. Therefore, we cannot disable the GIC CPU interface if we need to use same interrupts for CPU wake purpose. This creates a race condition for CPU power off entry. Also, in GICv1, disabling GICv1 CPU interface puts GICv1 into bypass mode such that incoming legacy IRQ/FIQ are sent to CPU, which means disabling GIC CPU interface doesn't really disable IRQ/FIQ to CPU.
GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not disabled by GIC CPU interface. This is done by adding a bypass override capability when the interrupts are disabled at the CPU interface. To support this, there are four bits about IRQ/FIQ BypassDisable in CPU interface Control Register. When the IRQ/FIQ not being driver by the CPU interface, each interrupt output signal can be deasserted rather than being driven by the legacy interrupt input.
So the wake-event can be used as wakeup signals to SoC (system power controller).
To prevent race conditions and ensure proper interrupt routing on Cortex-A15 CPUs when they are power-gated, add a CPU PM notifier call-back to reprogram the GIC CPU interface on PM entry. The GIC CPU interface will be reset back to its normal state by the common GIC CPU PM exit callback when the CPU wakes up.
Based on the work by: Scott Williams <[email protected]>
Quoted 9 lines
Quoted 1 line
Signed-off-by Joseph Lo <[email protected]>Hi Joseph,
We've had a rather long-standing issue with PCIe and MSI related to LP2 on Tegra20. I wonder if that's somehow related to this. Given that this is marked as Tegra114 patch explicitly I suppose not, but it certainly sounds very similar to the description above.
For LP2 + PCIe + MSI, I believe it need some other SW support if the HW really support MSI and runtime power down CPU domain that include SCU and BIU. According to TRM, the PCIe pass data through the unit to memory. I have no idea does the HW really support this function. I also need more information about this.
PATCH v4 2/4 ARM: tegra114: Reprogram GIC CPU interface to bypass IRQ on CPU PM entry
Quoted 41 lines · Joseph Lo
Quoted 31 lines · Thierry Reding
* PGP Signed by an unknown key
Quoted 28 lines · Joseph Lo
There is a difference between GICv1 and v2 when CPU in power management mode (aka CPU power down on Tegra). For GICv1, IRQ/FIQ interrupt lines going to CPU are same lines which are also used for wake-interrupt. Therefore, we cannot disable the GIC CPU interface if we need to use same interrupts for CPU wake purpose. This creates a race condition for CPU power off entry. Also, in GICv1, disabling GICv1 CPU interface puts GICv1 into bypass mode such that incoming legacy IRQ/FIQ are sent to CPU, which means disabling GIC CPU interface doesn't really disable IRQ/FIQ to CPU.
GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not disabled by GIC CPU interface. This is done by adding a bypass override capability when the interrupts are disabled at the CPU interface. To support this, there are four bits about IRQ/FIQ BypassDisable in CPU interface Control Register. When the IRQ/FIQ not being driver by the CPU interface, each interrupt output signal can be deasserted rather than being driven by the legacy interrupt input.
So the wake-event can be used as wakeup signals to SoC (system power controller).
To prevent race conditions and ensure proper interrupt routing on Cortex-A15 CPUs when they are power-gated, add a CPU PM notifier call-back to reprogram the GIC CPU interface on PM entry. The GIC CPU interface will be reset back to its normal state by the common GIC CPU PM exit callback when the CPU wakes up.
Based on the work by: Scott Williams <[email protected]>
Quoted 9 lines
Quoted 1 line
Signed-off-by Joseph Lo <[email protected]>Hi Joseph,
We've had a rather long-standing issue with PCIe and MSI related to LP2 on Tegra20. I wonder if that's somehow related to this. Given that this is marked as Tegra114 patch explicitly I suppose not, but it certainly sounds very similar to the description above.
Quoted 5 lines
For LP2 + PCIe + MSI, I believe it need some other SW support if the HW really support MSI and runtime power down CPU domain that include SCU and BIU. According to TRM, the PCIe pass data through the unit to memory. I have no idea does the HW really support this function. I also need more information about this.
Joseph, this is NVIDIA bug 1268311. Let's continue any discussion on this topic internally (i.e. debug the problem) in that bug, until we have something useful to report back upstream?
PATCH v4 3/4 ARM: tegra114: add low level support for CPU idle powered-down mode
In reply to Joseph LoThe flow controller would take care the power sequence when CPU idle in powered-down mode. It powered gate the CPU when CPU runs into WFI instruction. And wake up the CPU when event be triggered.
The sequence is below.
* setting wfi bitmap for the CPU as the halt event in the FLOW_CTRL_CPU_HALT_REG to monitor the CPU running into WFI,then power gate it
* setting IRQ and FIQ as wake up event to wake up CPU when event triggered
---
V4:
* no change
V3:
* no change
V2:
* no change
--- arch/arm/mach-tegra/flowctrl.h | 2 ++ arch/arm/mach-tegra/sleep-tegra30.S | 2 ++ 2 files changed, 4 insertions(+)
arch/arm/mach-tegra/flowctrl.h +2 -0
@@ -28,6 +28,8 @@#define FLOW_CTRL_SCLK_RESUME (1 << 27)#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) +#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) +#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8)#define FLOW_CTRL_CPU0_CSR 0x8#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
arch/arm/mach-tegra/sleep-tegra30.S +2 -0
@@ -99,6 +99,8 @@ flow_ctrl_setting_for_lp2: cmp r10, #TEGRA30 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2 movne r3, #FLOW_CTRL_WAITEVENT + orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ + orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ flow_ctrl_done: cmp r10, #TEGRA30 str r3, [r2]
Signature · 1 line
1.8.3.2
PATCH v4 4/4 ARM: tegra114: cpuidle: add powered-down state
In reply to Joseph LoThis supports CPU core power down on each CPU when CPU idle. When CPU go into this state, it saves it's context and needs a proper configuration in flow controller to power gate the CPU when CPU runs into WFI instruction. And the CPU also needs to set the IRQ as CPU power down idle wake up event in flow controller.
---
V4:
* postpone to use CPUIDLE_FLAG_TIMER_STOP flag, because it still has some issues
V3:
* use CPUIDLE_FLAG_TIMER_STOP flag
V2:
* remove some redundant code of memory barrier
* remove the function declaration by rearranging the coding sequence
--- arch/arm/mach-tegra/cpuidle-tegra114.c | 51 +++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-)
arch/arm/mach-tegra/cpuidle-tegra114.c +50 -1
@@ -17,15 +17,64 @@#include <linux/kernel.h> #include <linux/module.h> #include <linux/cpuidle.h> +#include <linux/cpu_pm.h> +#include <linux/clockchips.h> #include <asm/cpuidle.h> +#include <asm/suspend.h> +#include <asm/smp_plat.h> + +#include "pm.h" +#include "sleep.h" + +#ifdef CONFIG_PM_SLEEP +#define TEGRA114_MAX_STATES 2 +#else +#define TEGRA114_MAX_STATES 1 +#endif + +#ifdef CONFIG_PM_SLEEP +static int tegra114_idle_power_down (struct cpuidle_device *dev, +struct cpuidle_driver *drv, +int index) +{ +local_fiq_disable (); + +tegra_set_cpu_in_lp2 (); +cpu_pm_enter (); + +clockevents_notify (CLOCK_EVT_NOTIFY_BROADCAST_ENTER , &dev->cpu); + +cpu_suspend (0 , tegra30_sleep_cpu_secondary_finish); + +clockevents_notify (CLOCK_EVT_NOTIFY_BROADCAST_EXIT , &dev->cpu); + +cpu_pm_exit (); +tegra_clear_cpu_in_lp2 (); + +local_fiq_enable (); + +return index; +} +#endif static struct cpuidle_driver tegra_idle_driver = { .name ="tegra_idle" , .owner =THIS_MODULE , - .state_count =1 , + .state_count =TEGRA114_MAX_STATES , .states = { [0 ] =ARM_CPUIDLE_WFI_STATE_PWR (600 ), +#ifdef CONFIG_PM_SLEEP + [1] = { + .enter = tegra114_idle_power_down, + .exit_latency =500 , + .target_residency =1000 , + .power_usage =0 , + .flags =CPUIDLE_FLAG_TIME_VALID , + .name ="powered-down" , + .desc ="CPU power gated" , + }, +#endif }, };
Signature · 1 line
1.8.3.2
v4 cover ARM: tegra114: cpuidle: add power down state
In reply to Joseph LoQuoted 12 lines · Joseph Lo
This series introduce CPU core power down state for CPU idle. When CPU go into this state, it saves it's context and needs a proper configuration in flow controller to power gate the CPU when CPU runs into WFI instruction. And the CPU also needs to set the IRQ as CPU power down idle wake up event in flow controller.
To prevent race conditions and ensure proper interrupt routing on Cortex-A15 CPUs when they are power-gated, add a CPU PM notifier call-back to reprogram the GIC CPU interface on PM entry. The GIC CPU interface will be reset back to its normal state by the common GIC CPU PM exit callback when the CPU wakes up.
Quoted 3 lines
And the Tegra114 support CPU0 hotplug function in HW physically, but it needs other software to make it work normally after we add CPU idle power down mode support. But we don't support that yet, removing them for now.
OK, this version works fine, so I have applied it to Tegra's for-3.12/soc. I hope we can resolve the issues with CPUIDLE_FLAG_TIMER_STOP and CPU0 hot plug soon though.