OMAP5 uEVM USB eHCI patch set v4

index ea83e6c..f741d6f 100644
@@ -16,7 +16,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 const struct omap_sysinfo sysinfo = {
-	"Board: OMAP5430 EVM\n"
+	"Board: OMAP5432 uEVM\n"
 };
 
 /**

index 3adfc09..9a2166c 100644
@@ -149,6 +149,23 @@
 /* CM_L3INIT_USBPHY_CLKCTRL */
 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
 
+/* CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OPTFCLKEN_FUNC48M_CLK			(1 << 15)
+#define OPTFCLKEN_HSIC480M_P2_CLK		(1 << 14)
+#define OPTFCLKEN_HSIC480M_P1_CLK		(1 << 13)
+#define OPTFCLKEN_HSIC60M_P2_CLK		(1 << 12)
+#define OPTFCLKEN_HSIC60M_P1_CLK		(1 << 11)
+#define OPTFCLKEN_UTMI_P3_CLK			(1 << 10)
+#define OPTFCLKEN_UTMI_P2_CLK			(1 << 9)
+#define OPTFCLKEN_UTMI_P1_CLK			(1 << 8)
+#define OPTFCLKEN_HSIC480M_P3_CLK		(1 << 7)
+#define OPTFCLKEN_HSIC60M_P3_CLK		(1 << 6)
+
+/* CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OPTFCLKEN_USB_CH0_CLK_ENABLE	(1 << 8)
+#define OPTFCLKEN_USB_CH1_CLK_ENABLE	(1 << 9)
+#define OPTFCLKEN_USB_CH2_CLK_ENABLE	(1 << 10)
+
 /* CM_MPU_MPU_CLKCTRL */
 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(3 << 24)

43 lines not on this page · raw message

index 77e8170..ac83a53 100644
@@ -42,6 +42,7 @@ enum usbhs_omap_port_mode {
 /* Values of UHH_REVISION - Note: these are not given in the TRM */
 #define OMAP_USBHS_REV1					0x00000010 /* OMAP3 */
 #define OMAP_USBHS_REV2					0x50700100 /* OMAP4 */
+#define OMAP_USBHS_REV2_1				0x50700101 /* OMAP5 */
 
 /* UHH Register Set */
 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN		(1 << 2)

@@ -60,6 +61,7 @@ enum usbhs_omap_port_mode {
 #define OMAP_P2_MODE_CLEAR				(3 << 18)
 #define OMAP_P2_MODE_TLL				(1 << 18)
 #define OMAP_P2_MODE_HSIC				(3 << 18)
+#define OMAP_P3_MODE_CLEAR				(3 << 20)
 #define OMAP_P3_MODE_HSIC				(3 << 20)
 
 /* EHCI Register Set */

index a47e078..1ab8edc 100644
@@ -93,7 +93,8 @@ inline int __board_usb_init(void)
 int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
 
 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
-	defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
+	defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
+	defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
 /* controls PHY(s) reset signal(s) */
 static inline void omap_ehci_phy_reset(int on, int delay)
 {

@@ -112,6 +113,10 @@ static inline void omap_ehci_phy_reset(int on, int delay)
 	gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
 	gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
 #endif
+#ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
+	gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
+	gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
+#endif
 
 	/* Hold the PHY in RESET for enough time till DIR is high */
 	/* Refer: ISSUE1 */

@@ -195,10 +200,27 @@ int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
 		else
 			setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
 	} else if (rev == OMAP_USBHS_REV2) {
+
 		clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
 					OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
 
-		/* Clear port mode fields for PHY mode*/
+		/* Clear port mode fields for PHY mode */
+
+		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
+			setbits_le32(&reg, OMAP_P1_MODE_HSIC);
+
+		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
+			setbits_le32(&reg, OMAP_P2_MODE_HSIC);
+
+	} else if (rev == OMAP_USBHS_REV2_1) {
+
+		clrsetbits_le32(&reg,
+				(OMAP_P1_MODE_CLEAR |
+				 OMAP_P2_MODE_CLEAR |
+				 OMAP_P3_MODE_CLEAR),
+				OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
+
+		/* Clear port mode fields for PHY mode */
 
 		if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
 			setbits_le32(&reg, OMAP_P1_MODE_HSIC);

index 1ab8edc..7dc4ff6 100644
@@ -76,6 +76,7 @@ static void omap_usbhs_hsic_init(int port)
 	writel(reg, &usbtll->channel_conf + port);
 }
 
+#ifdef CONFIG_USB_ULPI
 static void omap_ehci_soft_phy_reset(int port)
 {
 	struct ulpi_viewport ulpi_vp;

@@ -85,6 +86,12 @@ static void omap_ehci_soft_phy_reset(int port)
 
 	ulpi_reset(&ulpi_vp);
 }
+#else
+static void omap_ehci_soft_phy_reset(int port)
+{
+	return;
+}
+#endif
 
 inline int __board_usb_init(void)
 {

index f741d6f..6219770 100644
@@ -13,6 +13,13 @@
 
 #include "mux_data.h"
 
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ehci.h>
+#include <asm/ehci-omap.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 const struct omap_sysinfo sysinfo = {

@@ -87,3 +94,56 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_USB_EHCI
+static struct omap_usbhs_board_data usbhs_bdata = {
+	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+	.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
+	.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
+};
+
+static void enable_host_clocks(void)
+{
+	int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
+				OPTFCLKEN_HSIC480M_P3_CLK |
+				OPTFCLKEN_HSIC60M_P2_CLK |
+				OPTFCLKEN_HSIC480M_P2_CLK |
+				OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
+
+	/* Enable port 2 and 3 clocks*/
+	setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
+
+	/* Enable port 2 and 3 usb host ports tll clocks*/
+	setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
+			(OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
+}
+
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+	int ret;
+	int auxclk;
+
+	enable_host_clocks();
+
+	auxclk = readl((*prcm)->scrm_auxclk1);
+	/* Request auxilary clock */
+	auxclk |= AUXCLK_ENABLE_MASK;
+	writel(auxclk, (*prcm)->scrm_auxclk1);
+
+	ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+	if (ret < 0) {
+		puts("Failed to initialize ehci\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+	int ret;
+
+	ret = omap_ehci_hcd_stop();
+	return ret;
+}
+#endif

index 36b723e..00d0fb9 100644
@@ -40,7 +40,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{USBD0_HS_DP, (IEN | M0)},	/*  USBD0_HS_DP */
 	{USBD0_HS_DM, (IEN | M0)},	/*  USBD0_HS_DM */
 	{USBD0_SS_RX, (IEN | M0)},	/*  USBD0_SS_RX */
-
+	{HSI2_ACWAKE, (PTU | M6)},    /*  HSI2_ACWAKE */
+	{HSI2_CAFLAG, (PTU | M6)},    /*  HSI2_CAFLAG */
 };
 
 const struct pad_conf_entry wkup_padconf_array_essential[] = {

@@ -48,6 +49,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = {
 	{SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
 	{SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
 	{SYS_32K, (IEN | M0)}, /*  SYS_32K     */
+	{FREF_CLK1_OUT, (PTD | IEN | M0)},    /*  FREF_CLK1_OUT  */
 
 };
 

index 9c045d3..70b059c 100644
@@ -37,6 +37,28 @@
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
 
+/* USB UHH support options */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
+#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
+
+/* Enabled commands */
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_DHCP		/* DHCP Support			*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#define CONFIG_CMD_NFS		/* NFS support			*/
+
+/* USB Networking options */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
 #define CONFIG_SYS_PROMPT		"OMAP5432 uEVM # "
 
 #define CONSOLEDEV		"ttyO2"

index 6219770..19d6e71 100644
@@ -18,6 +18,10 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/ehci.h>
 #include <asm/ehci-omap.h>
+
+#define DIE_ID_REG_BASE     (OMAP54XX_L4_CORE_BASE + 0x2000)
+#define DIE_ID_REG_OFFSET	0x200
+
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -122,9 +126,28 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	int ret;
 	int auxclk;
+	int reg;
+	uint8_t device_mac[6];
 
 	enable_host_clocks();
 
+	if (!getenv("usbethaddr")) {
+		reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
+
+		/*
+		 * create a fake MAC address from the processor ID code.
+		 * first byte is 0x02 to signify locally administered.
+		 */
+		device_mac[0] = 0x02;
+		device_mac[1] = readl(reg + 0x10) & 0xff;
+		device_mac[2] = readl(reg + 0xC) & 0xff;
+		device_mac[3] = readl(reg + 0x8) & 0xff;
+		device_mac[4] = readl(reg) & 0xff;
+		device_mac[5] = (readl(reg) >> 8) & 0xff;
+
+		eth_setenv_enetaddr("usbethaddr", device_mac);
+	}
+
 	auxclk = readl((*prcm)->scrm_auxclk1);
 	/* Request auxilary clock */
 	auxclk |= AUXCLK_ENABLE_MASK;

index 754d436..da667e8 100644
@@ -44,6 +44,10 @@
 static struct usb_hub_device hub_dev[USB_MAX_HUB];
 static int usb_hub_index;
 
+__weak void usb_hub_reset_devices(int port)
+{
+	return;
+}
 
 static int usb_get_hub_descriptor(struct usb_device *dev, void *data, int size)
 {

@@ -426,6 +430,14 @@ static int usb_hub_configure(struct usb_device *dev)
 	      "" : "no ");
 	usb_hub_power_on(hub);
 
+	/*
+	 * Reset any devices that may be in a bad state when applying
+	 * the power.  This is a __weak function.  Resettig of the devices
+	 * should occur in the board file of the device.
+	 */
+	for (i = 0; i < dev->maxchild; i++)
+		usb_hub_reset_devices(i + 1);
+
 	for (i = 0; i < dev->maxchild; i++) {
 		ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
 		unsigned short portstatus, portchange;

index 19d6e71..aa6846f 100644
@@ -15,6 +15,7 @@
 
 #ifdef CONFIG_USB_EHCI
 #include <usb.h>
+#include <asm/gpio.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/ehci.h>
 #include <asm/ehci-omap.h>

@@ -169,4 +170,14 @@ int ehci_hcd_stop(void)
 	ret = omap_ehci_hcd_stop();
 	return ret;
 }
+
+void usb_hub_reset_devices(int port)
+{
+	/* The LAN9730 needs to be reset after the port power has been set. */
+	if (port == 3) {
+		gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
+		udelay(10);
+		gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
+	}
+}
 #endif