MSI support for Marvell EBU PCIe driver
Subsystems (13)
v6 cover MSI support for Marvell EBU PCIe driver
Hello,
This set of patches introduces Message Signaled Interrupt support in the Marvell EBU PCIe driver. It has been successfully tested on the Armada XP GP platform with an Intel e1000e PCIe network card that supports MSI.
This patch set is intended for merging in 3.12, so the respective maintainers of the different areas are invited to review/ack the patches, see below for the details. Note that several of those patches are also needed for the Tegra PCIe driver.
There are still missing ACKs from Grant Likely (5, 6, 7), Thomas Gleixner (8, 9) and Bjorn Helgaas (2, 12).
The patches do the following:
* Patch 1 reworks how the architecture-specific MSI functions can be overriden by architecture-specific code, by using weak functions. It was suggested by Bjorn Helgaas.
This patch has been acked by Bjorn Helgaas, the PCI maintainter.
* Patch 2 removes the ARCH_SUPPORTS_MSI hidden kconfig boolean which is no longer needed now that we have weak functions for all MSI architecture-specific hooks.
This patch needs the Ack from Bjorn Helgaas, and the relevant architecture maintainers.
* Patch 3 adds a minimal msi_chip infrastructure, that allows a pci_bus to be connected to a msi_chip, and that provides default implementations of the architecture-specific MSI functions to use msi_chip.
This patch has been acked by Bjorn Helgaas, the PCI maintainter.
* Patch 4 adds an IRQ domain function that allows to allocate dynamically a free hwirq number from an IRQ domain, and create a virq mapping to it. It was suggested by Grant Likely in order to remove the hwirq allocation code from the IRQ driver itself.
Patch has been Acked by Grant Likely, irq_domain maintainer.
* Patch 5 refactors the __irq_domain_add() function in the irq_domain code, in preparation for the introduction of MSI support in irq_domain.
This patch needs the ACK of Grant Likely.
* Patch 6 allows to create an irq_domain associated with a msi_chip, thanks to the new irq_domain_add_msi() function.
This patch needs the ACK of Grant Likely.
* Patch 7 adds a new function irq_find_msi_host() to find the MSI-type interrupt controller associated to a given DT node, and adjusts irq_find_host() to not match MSI-type interrupt controllers.
This patch needs the ACK of Grant Likely.
* Patch 8 makes some not very interesting preparation in the Armada 370/XP IRQ controller driver.
This patch needs the Ack from Thomas Gleixner.
* Patch 9 implements the MSI support in the Armada 370/XP IRQ controller driver. It registers an msi_chip using the msi_chip_add() function added in PATCH 3.
This patch needs the Ack from Thomas Gleixner.
* Patch 10 extends the ARM PCI core to expose ->add_bus() and ->remove_bus() hooks to PCI drivers. This was suggested by Bjorn Helgaas to allow the PCI driver to connected the PCI busses with the corresponding MSI chip.
This patch has been Acked by Russell King, the ARM maintainer.
* Patch 11 adjust the Armada 370/XP Device Tree to indicate that the MPIC is not only an interrupt-controller, but also an msi-controller.
This patch needs the Ack from Jason Cooper, Gregory Clement and/or Andrew Lunn, the Marvell maintainers.
* Patch 12 adds MSI support in the Marvell PCIe host controller driver. The work to do here is minimal: get a reference to the msi-parent controller thanks to msi_chip_find_by_of_node(), and link it to the pci_bus structure before the bus gets enumerated.
This patch needs the Ack from Bjorn Helgaas.
* Patch 13 adjusts the Armada 370/XP Device Tree to add the msi-parent properties in the PCIe controller nodes.
This patch needs the Ack from Jason Cooper, Gregory Clement and/or Andrew Lunn, the Marvell Maintainers.
This version 6 follows:
* PATCH version 5 sent on July, 15th 2013
* PATCH version 4 sent on July, 1st 2013
* PATCH version 3 sent on June, 19th 2013
* PATCH version 2 sent on June, 6th 2013
* RFC version 1 sent on March, 26th 2013
Changes since v5:
* Rebased on top of 3.11-rc3.
* Implemented the suggestions of Grant Likely on "irqdomain: add irq_alloc_mapping() function" and added his Acked-by.
* Added Bjorn Helgaas Acked-by on "PCI: use weak functions for MSI arch-specific functions".
* Added Bjorn Helgaas Acked-by on "PCI: Introduce new MSI chip infrastructure".
* Remove the drivers/of global registry of irq_chip, and as suggested by Grant Likely, create an association between an irq_domain and a msi_chip. This required refactoring the __irq_domain_add() function, adding a 'msi_chip' pointer to 'irq_domain', adding an irq_domain_add_msi() function and a irq_find_msi_host() function.
* Added Russell King Acked-by on "ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pci"
Changes since v4:
* Rebased on top of 3.11-rc1.
* Slightly rework the implementation of arch_setup_msi_irq(), arch_teardown_msi_irq and arch_msi_check_device() according to the suggestions of Bjorn Helgaas (PATCH 4)
* Make a few improvements to the msi_chip registry, according to the suggestion of Bjorn Helgaas and Rob Herring: coding style fixes, usage of mutex while traversing the list of msi_chip, usage of of_pci_msi_* prefix instead of just of_msi_*.
Changes since v3:
* Keep only a default_teardown_msi_irqs() function needed for the Xen PCI x86 code, and remove all other default_*() function and put the default behavior directly in the weak functions. Suggested by Thierry Redding and Bjorn Helgaas.
* Misc small improvements the MSI chip registry code: compiled only under CONFIG_PCI_MSI, functions exported to modules, addition of an of_msi_chip_remove() function, renaming of of_msi_chip_find_by_node() to of_find_msi_chip_by_node(), move the test of the "msi-controller" property to the of_msi_chip_add() function, renamed the list_head field from link to list, added dummy functions in the header files when !CONFIG_PCI_MSI && !CONFIG_OF. All suggested by Thierry Redding.
* Add a patch that entirely removes the ARCH_SUPPORTS_MSI, as we now have weak functions, so even if an arch doesn't actually use/support MSI, the code will build properly. Suggested by Thierry Redding.
* Added Device Tree binding documentation updates for the IRQ controller and the PCIe controller.
Changes since v2:
* Add an IRQ domain function that allows to allocate dynamically a free hwirq number from an IRQ domain, and create a virq mapping to it. It was suggested by Grant Likely in order to remove the hwirq allocation code from the IRQ driver itself. (PATCH 1)
* Separate the use of weak functions from the introduction of the msi_chip infrastructure, and use weak functions for all architecture-specific MSI hooks. Suggested by Bjorn Helgaas (PATCH 2).
* Move the msi_chip registry to drivers/of. Suggested by Bjorn Helgaas (PATCH 4).
* Use pcibios_add_bus() and pcibios_remove_bus() to connect the PCI busses to their msi_chip, as suggested by Bjorn Helgaas. Requires some ARM PCI core changes (PATCH 7), and then changes to the PCI driver itself (PATCH 9).
This set of patches applies on top of 3.11-rc3, and is available as a Git branch at
https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-msi-v6.
Thanks,
Thomas
Thierry Reding (1):
PCI: Introduce new MSI chip infrastructure
Thomas Petazzoni (12):
PCI: use weak functions for MSI arch-specific functions
PCI: remove ARCH_SUPPORTS_MSI kconfig option
irqdomain: add irq_alloc_mapping() function
irqdomain: refactor __irq_domain_add()
irqdomain: add support to associate an irq_domain with a msi_chip
irqdomain: add function to find a MSI irq_domain
irqchip: armada-370-xp: properly request resources
irqchip: armada-370-xp: implement MSI support
ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pci
ARM: mvebu: the MPIC now provides MSI controller features
PCI: mvebu: add support for MSI
ARM: mvebu: link PCIe controllers to the MSI controller
.../devicetree/bindings/arm/armada-370-xp-mpic.txt | 3 + .../devicetree/bindings/pci/mvebu-pci.txt | 3 + arch/arm/Kconfig | 1 - arch/arm/boot/dts/armada-370-xp.dtsi | 1 + arch/arm/boot/dts/armada-370.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 1 + arch/arm/include/asm/mach/pci.h | 4 + arch/arm/kernel/bios32.c | 16 +++ arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 2 - arch/mips/include/asm/pci.h | 5 - arch/powerpc/Kconfig | 1 - arch/powerpc/include/asm/pci.h | 5 - arch/s390/Kconfig | 1 - arch/s390/include/asm/pci.h | 4 - arch/sparc/Kconfig | 1 - arch/tile/Kconfig | 1 - arch/x86/Kconfig | 1 - arch/x86/include/asm/pci.h | 28 ---- arch/x86/kernel/x86_init.c | 21 +++ drivers/irqchip/irq-armada-370-xp.c | 153 ++++++++++++++++++++- drivers/pci/Kconfig | 4 - drivers/pci/host/pci-mvebu.c | 31 +++++ drivers/pci/msi.c | 66 +++++---- drivers/pci/probe.c | 1 + include/linux/irqdomain.h | 62 ++++++++- include/linux/msi.h | 18 ++- include/linux/pci.h | 1 + kernel/irq/irqdomain.c | 89 +++++++++--- 31 files changed, 422 insertions(+), 106 deletions(-)
Signature · 1 line
1.8.1.2
PATCH v6 1/13 PCI: use weak functions for MSI arch-specific functions
Until now, the MSI architecture-specific functions could be overloaded using a fairly complex set of #define and compile-time conditionals. In order to prepare for the introduction of the msi_chip infrastructure, it is desirable to switch all those functions to use the 'weak' mechanism. This commit converts all the architectures that were overidding those MSI functions to use the new strategy.
Note that we keep a separate, non-weak, function default_teardown_msi_irqs() for the default behavior of the arch_teardown_msi_irqs(), as the default behavior is needed by the Xen x86 PCI code.
--- arch/mips/include/asm/pci.h | 5 ----- arch/powerpc/include/asm/pci.h | 5 ----- arch/s390/include/asm/pci.h | 4 ---- arch/x86/include/asm/pci.h | 28 -------------------------- arch/x86/kernel/x86_init.c | 21 ++++++++++++++++++++ drivers/pci/msi.c | 45 +++++++++++++++++++----------------------- include/linux/msi.h | 7 ++++++- 7 files changed, 47 insertions(+), 68 deletions(-)
arch/mips/include/asm/pci.h +0 -5
@@ -136,11 +136,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)return channel ?15 :14 ; } -#ifdef CONFIG_CPU_CAVIUM_OCTEON -/* MSI arch hook for OCTEON */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#endif -extern char * (*pcibios_plat_setup)(char *str);#ifdef CONFIG_OF
arch/powerpc/include/asm/pci.h +0 -5
@@ -113,11 +113,6 @@ extern int pci_domain_nr(struct pci_bus *bus);/* Decide whether to display the domain number in /proc */ extern int pci_proc_domain (struct pci_bus *bus); -/* MSI arch hooks */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#define arch_teardown_msi_irqs arch_teardown_msi_irqs -#define arch_msi_check_device arch_msi_check_device -struct vm_area_struct ;/* Map a range of PCI memory or I/O space for a device into user space */ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
arch/s390/include/asm/pci.h +0 -4
@@ -21,10 +21,6 @@ void pci_iounmap(struct pci_dev *, void __iomem *);int pci_domain_nr (struct pci_bus *);int pci_proc_domain (struct pci_bus *); -/* MSI arch hooks */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#define arch_teardown_msi_irqs arch_teardown_msi_irqs -#define ZPCI_BUS_NR 0/* default bus number */ #define ZPCI_DEVFN 0/* default device number */
arch/x86/include/asm/pci.h +0 -28
@@ -100,29 +100,6 @@ static inline void early_quirks(void) { }extern void pci_iommu_alloc (void );#ifdef CONFIG_PCI_MSI -/* MSI arch specific hooks */ -static inline int x86_setup_msi_irqs (struct pci_dev *dev,int nvec,int type) -{ -return x86_msi.setup_msi_irqs (dev, nvec, type); -} - -static inline void x86_teardown_msi_irqs (struct pci_dev *dev) -{ - x86_msi.teardown_msi_irqs (dev); -} - -static inline void x86_teardown_msi_irq (unsigned int irq) -{ - x86_msi.teardown_msi_irq (irq); -} -static inline void x86_restore_msi_irqs (struct pci_dev *dev,int irq) -{ - x86_msi.restore_msi_irqs (dev, irq); -} -#define arch_setup_msi_irqs x86_setup_msi_irqs -#define arch_teardown_msi_irqs x86_teardown_msi_irqs -#define arch_teardown_msi_irq x86_teardown_msi_irq -#define arch_restore_msi_irqs x86_restore_msi_irqs/* implemented in arch/x86/kernel/apic/io_apic. */ struct msi_desc ;int native_setup_msi_irqs (struct pci_dev *dev,int nvec,int type);
@@ -130,11 +107,6 @@ void native_teardown_msi_irq(unsigned int irq);void native_restore_msi_irqs (struct pci_dev *dev,int irq);int setup_msi_irq (struct pci_dev *dev,struct msi_desc *msidesc,unsigned int irq_base,unsigned int irq_offset); -/* default to the implementation in drivers/lib/msi.c */ -#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS -#define HAVE_DEFAULT_MSI_RESTORE_IRQS -void default_teardown_msi_irqs (struct pci_dev *dev); -void default_restore_msi_irqs (struct pci_dev *dev,int irq);#else #define native_setup_msi_irqs NULL#define native_teardown_msi_irq NULL
arch/x86/kernel/x86_init.c +21 -0
@@ -116,6 +116,27 @@ struct x86_msi_ops x86_msi = { .setup_hpet_msi = default_setup_hpet_msi, }; +/* MSI arch specific hooks */ +int arch_setup_msi_irqs (struct pci_dev *dev,int nvec,int type) +{ +return x86_msi.setup_msi_irqs (dev, nvec, type); +} + +void arch_teardown_msi_irqs (struct pci_dev *dev) +{ + x86_msi.teardown_msi_irqs (dev); +} + +void arch_teardown_msi_irq (unsigned int irq) +{ + x86_msi.teardown_msi_irq (irq); +} + +void arch_restore_msi_irqs (struct pci_dev *dev,int irq) +{ + x86_msi.restore_msi_irqs (dev, irq); +} +struct x86_io_apic_ops x86_io_apic_ops = { .init = native_io_apic_init_mappings, .read = native_io_apic_read,
drivers/pci/msi.c +20 -25
76 lines not on this page · raw message
include/linux/msi.h +6 -1
@@ -51,12 +51,17 @@ struct msi_desc { };/* -* The arch hook for setup up msi irqs +* The arch hooks to setup up msi irqs. Those functions are +* implemented as weak symbols so that they /can/ be overriden by +* architecture specific code if needed. */ int arch_setup_msi_irq (struct pci_dev *dev,struct msi_desc *desc);void arch_teardown_msi_irq (unsigned int irq);int arch_setup_msi_irqs (struct pci_dev *dev,int nvec,int type);void arch_teardown_msi_irqs (struct pci_dev *dev);int arch_msi_check_device (struct pci_dev * dev,int nvec,int type); +void arch_restore_msi_irqs (struct pci_dev *dev,int irq); + +void default_teardown_msi_irqs (struct pci_dev *dev);#endif /* LINUX_MSI_H */
Signature · 1 line
1.8.1.2
PATCH v6 2/13 PCI: remove ARCH_SUPPORTS_MSI kconfig option
In reply to Thomas PetazzoniNow that we have weak versions for each of the PCI MSI architecture functions, we can actually build the MSI support for all platforms, regardless of whether they provide or not architecture-specific versions of those functions. For this reason, the ARCH_SUPPORTS_MSI hidden kconfig boolean becomes useless, and this patch gets rid of it.
--- arch/arm/Kconfig | 1 - arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 2 -- arch/powerpc/Kconfig | 1 - arch/s390/Kconfig | 1 - arch/sparc/Kconfig | 1 - arch/tile/Kconfig | 1 - arch/x86/Kconfig | 1 - drivers/pci/Kconfig | 4 ---- 9 files changed, 13 deletions(-)
arch/arm/Kconfig +0 -1
@@ -441,7 +441,6 @@ config ARCH_NETX config ARCH_IOP13XX bool "IOP13xx-based" depends on MMU - select ARCH_SUPPORTS_MSI select CPU_XSC3 select NEED_MACH_MEMORY_H select NEED_RET_TO_USER
arch/ia64/Kconfig +0 -1
@@ -9,7 +9,6 @@ config IA64 select PCI if (!IA64_HP_SIM) select ACPI if (!IA64_HP_SIM) select PM if (!IA64_HP_SIM) - select ARCH_SUPPORTS_MSI select HAVE_UNSTABLE_SCHED_CLOCK select HAVE_IDE select HAVE_OPROFILE
arch/mips/Kconfig +0 -2
@@ -726,7 +726,6 @@ config CAVIUM_OCTEON_SOC select SYS_HAS_CPU_CAVIUM_OCTEON select SWAP_IO_SPACE select HW_HAS_PCI - select ARCH_SUPPORTS_MSI select ZONE_DMA32 select USB_ARCH_HAS_OHCI select USB_ARCH_HAS_EHCI
@@ -762,7 +761,6 @@ config NLM_XLR_BOARD select CEVT_R4K select CSRC_R4K select IRQ_CPU - select ARCH_SUPPORTS_MSI select ZONE_DMA32 if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK
arch/powerpc/Kconfig +0 -1
@@ -727,7 +727,6 @@ config PCI default y if !40x && !CPM2 && !8xx && !PPC_83xx \ && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON default PCI_QSPAN if !4xx && !CPM2 && 8xx - select ARCH_SUPPORTS_MSI select GENERIC_PCI_IOMAP help Find out whether your system includes a PCI bus. PCI is the name of
arch/s390/Kconfig +0 -1
@@ -428,7 +428,6 @@ menuconfig PCI bool "PCI support" default n depends on 64BIT - select ARCH_SUPPORTS_MSI select PCI_MSI help Enable PCI support.
arch/sparc/Kconfig +0 -1
@@ -52,7 +52,6 @@ config SPARC32 config SPARC64 def_bool 64BIT - select ARCH_SUPPORTS_MSI select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FUNCTION_GRAPH_FP_TEST
arch/tile/Kconfig +0 -1
@@ -380,7 +380,6 @@ config PCI select PCI_DOMAINS select GENERIC_PCI_IOMAP select TILE_GXIO_TRIO if TILEGX - select ARCH_SUPPORTS_MSI if TILEGX select PCI_MSI if TILEGX ---help--- Enable PCI root complex support, so PCIe endpoint devices can
arch/x86/Kconfig +0 -1
@@ -2014,7 +2014,6 @@ menu "Bus options (PCI etc.)" config PCI bool "PCI support" default y - select ARCH_SUPPORTS_MSI if (X86_LOCAL_APIC && X86_IO_APIC) ---help--- Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside
drivers/pci/Kconfig +0 -4
@@ -1,13 +1,9 @@ # # PCI configuration # -config ARCH_SUPPORTS_MSI - bool - config PCI_MSI bool "Message Signaled Interrupts (MSI and MSI-X)" depends on PCI - depends on ARCH_SUPPORTS_MSI help This allows device drivers to enable MSI (Message Signaled Interrupts). Message Signaled Interrupts enable a device to
Signature · 1 line
1.8.1.2
Bjorn Helgaas
maintainerPATCH v6 2/13 PCI: remove ARCH_SUPPORTS_MSI kconfig option
Quoted 7 lines · Thomas Petazzoni
Now that we have weak versions for each of the PCI MSI architecture functions, we can actually build the MSI support for all platforms, regardless of whether they provide or not architecture-specific versions of those functions. For this reason, the
ARCH_SUPPORTS_MSIhidden kconfig boolean becomes useless, and this patch gets rid of it.Signed-off-by Thomas Petazzoni <[email protected]>
Quoted 157 lines
Cc Benjamin Herrenschmidt <[email protected]>Cc Paul Mackerras <[email protected]>Cc linuxppc-dev at lists.ozlabs.orgCc Martin Schwidefsky <[email protected]>Cc Heiko Carstens <[email protected]>Cc linux390 at de.ibm.comCc linux-s390 at vger.kernel.orgCc Thomas Gleixner <[email protected]>Cc Ingo Molnar <[email protected]>Cc H. Peter Anvin <[email protected]>Cc x86 at kernel.orgCc Russell King <[email protected]>Cc Tony Luck <[email protected]>Cc Fenghua Yu <[email protected]>Cc linux-ia64 at vger.kernel.orgCc Ralf Baechle <[email protected]>Cc linux-mips at linux-mips.orgCc David S. Miller <[email protected]>Cc sparclinux at vger.kernel.orgCc Chris Metcalf <[email protected]>--- arch/arm/Kconfig | 1 - arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 2 -- arch/powerpc/Kconfig | 1 - arch/s390/Kconfig | 1 - arch/sparc/Kconfig | 1 - arch/tile/Kconfig | 1 - arch/x86/Kconfig | 1 - drivers/pci/Kconfig | 4 ---- 9 files changed, 13 deletions(-)arch/arm/Kconfig +0
-1@@ -441,7 +441,6 @@ config ARCH_NETX config ARCH_IOP13XX bool "IOP13xx-based" depends on MMU - select ARCH_SUPPORTS_MSI select CPU_XSC3 select NEED_MACH_MEMORY_H select NEED_RET_TO_USERarch/ia64/Kconfig +0
-1@@ -9,7 +9,6 @@ config IA64 select PCI if (!IA64_HP_SIM) select ACPI if (!IA64_HP_SIM) select PM if (!IA64_HP_SIM) - select ARCH_SUPPORTS_MSI select HAVE_UNSTABLE_SCHED_CLOCK select HAVE_IDE select HAVE_OPROFILEarch/mips/Kconfig +0
-2@@ -726,7 +726,6 @@ config CAVIUM_OCTEON_SOC select SYS_HAS_CPU_CAVIUM_OCTEON select SWAP_IO_SPACE select HW_HAS_PCI - select ARCH_SUPPORTS_MSI select ZONE_DMA32 select USB_ARCH_HAS_OHCI select USB_ARCH_HAS_EHCI@@ -762,7 +761,6 @@ config NLM_XLR_BOARD select CEVT_R4K select CSRC_R4K select IRQ_CPU - select ARCH_SUPPORTS_MSI select ZONE_DMA32 if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTKarch/powerpc/Kconfig +0
-1@@ -727,7 +727,6 @@ config PCI default y if !40x && !CPM2 && !8xx && !PPC_83xx \ && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON default PCI_QSPAN if !4xx && !CPM2 && 8xx - select ARCH_SUPPORTS_MSI select GENERIC_PCI_IOMAP help Find out whether your system includes a PCI bus. PCI is the name ofarch/s390/Kconfig +0
-1@@ -428,7 +428,6 @@ menuconfig PCI bool "PCI support" default n depends on 64BIT - select ARCH_SUPPORTS_MSI select PCI_MSI help Enable PCI support.arch/sparc/Kconfig +0
-1@@ -52,7 +52,6 @@ config SPARC32 config SPARC64 def_bool 64BIT - select ARCH_SUPPORTS_MSI select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FUNCTION_GRAPH_FP_TESTarch/tile/Kconfig +0
-1@@ -380,7 +380,6 @@ config PCI select PCI_DOMAINS select GENERIC_PCI_IOMAP select TILE_GXIO_TRIO if TILEGX - select ARCH_SUPPORTS_MSI if TILEGX select PCI_MSI if TILEGX ---help--- Enable PCI root complex support, so PCIe endpoint devices canarch/x86/Kconfig +0
-1@@ -2014,7 +2014,6 @@ menu "Bus options (PCI etc.)" config PCI bool "PCI support" default y - select ARCH_SUPPORTS_MSI if (X86_LOCAL_APIC && X86_IO_APIC) ---help--- Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff insidedrivers/pci/Kconfig +0
-5@@ -1,13 +1,9 @@ # # PCI configuration # -config ARCH_SUPPORTS_MSI - bool - config PCI_MSI bool "Message Signaled Interrupts (MSI and MSI-X)" depends on PCI - depends on ARCH_SUPPORTS_MSI help This allows device drivers to enable MSI (Message Signaled Interrupts). Message Signaled Interrupts enable a device to --1.8.1.2
PATCH v6 3/13 PCI: Introduce new MSI chip infrastructure
In reply to Thomas PetazzoniFrom: Thierry Reding <[email protected]>
The new struct msi_chip is used to associated an MSI controller with a PCI bus. It is automatically handed down from the root to its children during bus enumeration.
This patch provides default (weak) implementations for the architecture- specific MSI functions (arch_setup_msi_irq(), arch_teardown_msi_irq() and arch_msi_check_device()) which check if a PCI device's bus has an attached MSI chip and forward the call appropriately.
--- drivers/pci/msi.c | 27 +++++++++++++++++++++++++-- drivers/pci/probe.c | 1 + include/linux/msi.h | 11 +++++++++++ include/linux/pci.h | 1 + 4 files changed, 38 insertions(+), 2 deletions(-)
drivers/pci/msi.c +25 -2
@@ -32,16 +32,39 @@ static int pci_msi_enable = 1;int __weak arch_setup_msi_irq (struct pci_dev *dev,struct msi_desc *desc) { -return -EINVAL ; +struct msi_chip *chip = dev->bus->msi; +int err; + +if (!chip || !chip->setup_irq) +return -EINVAL ; + + err = chip->setup_irq (chip, dev, desc); +if (err <0 ) +return err; + +irq_set_chip_data (desc->irq, chip); + +return 0 ; }void __weak arch_teardown_msi_irq (unsigned int irq) { +struct msi_chip *chip =irq_get_chip_data (irq); + +if (!chip || !chip->teardown_irq) +return ; + + chip->teardown_irq (chip, irq); }int __weak arch_msi_check_device (struct pci_dev *dev,int nvec,int type) { -return 0 ; +struct msi_chip *chip = dev->bus->msi; + +if (!chip || !chip->check_device) +return 0 ; + +return chip->check_device (chip, dev, nvec, type); }int __weak arch_setup_msi_irqs (struct pci_dev *dev,int nvec,int type)
drivers/pci/probe.c +1 -0
@@ -666,6 +666,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, child->parent = parent; child->ops = parent->ops; + child->msi = parent->msi; child->sysdata = parent->sysdata; child->bus_flags = parent->bus_flags;
include/linux/msi.h +11 -0
@@ -64,4 +64,15 @@ void arch_restore_msi_irqs(struct pci_dev *dev, int irq);void default_teardown_msi_irqs (struct pci_dev *dev); +struct msi_chip { +struct module *owner; +struct device *dev; + +int (*setup_irq)(struct msi_chip *chip,struct pci_dev *dev, +struct msi_desc *desc); +void (*teardown_irq)(struct msi_chip *chip,unsigned int irq); +int (*check_device)(struct msi_chip *chip,struct pci_dev *dev, +int nvec,int type); +}; +#endif /* LINUX_MSI_H */
include/linux/pci.h +1 -0
@@ -433,6 +433,7 @@ struct pci_bus {struct resource busn_res;/* bus numbers routed to this bus */ struct pci_ops *ops;/* configuration access functions */ +struct msi_chip *msi;/* MSI controller */ void *sysdata;/* hook for sys-specific extension */ struct proc_dir_entry *procdir;/* directory entry in /proc/bus/pci */
Signature · 1 line
1.8.1.2
PATCH v6 4/13 irqdomain: add irq_alloc_mapping() function
In reply to Thomas PetazzoniThis commit extends the irqdomain subsystem with an irq_alloc_mapping() function which allows to let the irqdomain code find an available hwirq number in the range [ 0 ; domain size ] for the given domain, and create a virq mapping for it.
--- include/linux/irqdomain.h | 2 ++ kernel/irq/irqdomain.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+)
include/linux/irqdomain.h +2 -0
@@ -195,6 +195,8 @@ static inline unsigned int irq_linear_revmap(struct irq_domain *domain,extern unsigned int irq_find_mapping (struct irq_domain *host,irq_hw_number_t hwirq);extern unsigned int irq_create_direct_mapping (struct irq_domain *host); +extern unsigned int irq_alloc_mapping (struct irq_domain *host, +irq_hw_number_t *hwirq);extern int irq_create_strict_mappings (struct irq_domain *domain,unsigned int irq_base,irq_hw_number_t hwirq_base,int count);
kernel/irq/irqdomain.c +36 -0
@@ -375,6 +375,42 @@ unsigned int irq_create_direct_mapping(struct irq_domain *domain)EXPORT_SYMBOL_GPL (irq_create_direct_mapping);/** +* irq_alloc_mapping() - Allocate an irq for mapping +* @domain: domain to allocate the irq for or NULL for default domain +* @hwirq: reference to the returned hwirq +* +* This routine are used for irq controllers which can choose the +* hardware interrupt number from a range [ 0 ; domain size ], such as +* is often the case with PCI MSI controllers. The function will +* returned the allocated hwirq number in the hwirq pointer, and the +* corresponding virq number as the return value. +*/ +unsigned int irq_alloc_mapping (struct irq_domain *domain, +irq_hw_number_t *out_hwirq) +{ +irq_hw_number_t hwirq; +int rc; + +pr_debug ("irq_alloc_mapping(0x%p)\n" , domain); + +for (hwirq =0 ; hwirq < domain->revmap_size; hwirq++) +if (domain->linear_revmap[hwirq] ==0 ) +break ; + +if (hwirq == domain->hwirq_max) { +pr_debug ("-> no available hwirq found\n" ); +return 0 ; + } + + rc =irq_create_mapping (domain, hwirq); +if (rc) + *out_hwirq = hwirq; + +return rc; +} +EXPORT_SYMBOL_GPL (irq_alloc_mapping); + +/** * irq_create_mapping() - Map a hardware interrupt into linux irq space * @domain: domain owning this hardware interrupt or NULL for default domain * @hwirq: hardware irq number in that domain space
Signature · 1 line
1.8.1.2
PATCH v6 5/13 irqdomain: refactor __irq_domain_add()
In reply to Thomas PetazzoniCurrently, the __irq_domain_add() function does both the irq_domain allocation *and* registration. This is a problem for irq_domain_add_*() helpers that need to do something between the allocation and the registration, such as for example setting a d->msi_chip pointer in the irq_domain structure before this structure is made globally visible by being registered.
Moreover, the comment in __irq_domain_add() also suggests that an irq_domain_register() function should exist.
Therefore, this commit:
* Splits __irq_domain_add() into __irq_domain_alloc() (allocation and initialization of the irq_domain) and __irq_domain_register() (registration of the irq_domain to the global list)
* Modifies the existing users of __irq_domain_add() to use those two functions.
A next commit will make another use of it when introducing support for msi_chip in the irqdomain code.
--- include/linux/irqdomain.h | 21 +++++++++++++++++---- kernel/irq/irqdomain.c | 40 +++++++++++++++++++++++++++------------- 2 files changed, 44 insertions(+), 17 deletions(-)
include/linux/irqdomain.h +17 -4
@@ -111,10 +111,11 @@ struct irq_domain { };#ifdef CONFIG_IRQ_DOMAIN -struct irq_domain *__irq_domain_add (struct device_node *of_node,int size, +struct irq_domain *__irq_domain_alloc (struct device_node *of_node,int size,irq_hw_number_t hwirq_max,int direct_max,const struct irq_domain_ops *ops,void *host_data); +void __irq_domain_register (struct irq_domain *domain); struct irq_domain *irq_domain_add_simple(struct device_node *of_node, unsigned int size, unsigned int first_irq,
@@ -141,14 +142,22 @@ static inline struct irq_domain *irq_domain_add_linear(struct device_node *of_noconst struct irq_domain_ops *ops, void *host_data) { - return __irq_domain_add(of_node, size, size, 0, ops, host_data); + struct irq_domain *d; + d =__irq_domain_alloc (of_node, size, size,0 , ops, host_data); +if (d) +__irq_domain_register (d); +return d; }static inline struct irq_domain *irq_domain_add_nomap (struct device_node *of_node,unsigned int max_irq,const struct irq_domain_ops *ops,void *host_data) { -return __irq_domain_add (of_node,0 , max_irq, max_irq, ops, host_data); +struct irq_domain *d; + d =__irq_domain_alloc (of_node,0 , max_irq, max_irq, ops, host_data); +if (d) +__irq_domain_register (d); +return d; } static inline struct irq_domain *irq_domain_add_legacy_isa( struct device_node *of_node,
@@ -162,7 +171,11 @@ static inline struct irq_domain *irq_domain_add_tree(struct device_node *of_nodeconst struct irq_domain_ops *ops, void *host_data) { - return __irq_domain_add(of_node, 0, ~0, 0, ops, host_data); + struct irq_domain *d; + d =__irq_domain_alloc (of_node,0 , ~0 ,0 , ops, host_data); +if (d) +__irq_domain_register (d); +return d; }extern void irq_domain_remove (struct irq_domain *host);
kernel/irq/irqdomain.c +27 -13
@@ -23,7 +23,7 @@ static DEFINE_MUTEX(revmap_trees_mutex);static struct irq_domain *irq_default_domain;/** -* __irq_domain_add() - Allocate a new irq_domain data structure +* __irq_domain_alloc() - Allocate a new irq_domain data structure * @of_node: optional device-tree node of the interrupt controller * @size: Size of linear map; 0 for radix mapping only * @direct_max: Maximum value of direct maps; Use ~0 for no limit; 0 for no
@@ -31,14 +31,15 @@ static struct irq_domain *irq_default_domain;* @ops: map/unmap domain callbacks * @host_data: Controller private data pointer * -* Allocates and initialize and irq_domain structure. Caller is expected to -* register allocated irq_domain with irq_domain_register(). Returns pointer -* to IRQ domain, or NULL on failure. +* Allocates and initializes an irq_domain structure. Caller is +* expected to register the allocated irq_domain with +* __irq_domain_register(). Returns pointer to IRQ domain, or NULL on +* failure. */ -struct irq_domain *__irq_domain_add (struct device_node *of_node,int size, -irq_hw_number_t hwirq_max,int direct_max, -const struct irq_domain_ops *ops, -void *host_data) +struct irq_domain *__irq_domain_alloc (struct device_node *of_node,int size, +irq_hw_number_t hwirq_max,int direct_max, +const struct irq_domain_ops *ops, +void *host_data) {struct irq_domain *domain;
@@ -56,14 +57,24 @@ struct irq_domain *__irq_domain_add(struct device_node *of_node, int size, domain->revmap_size = size; domain->revmap_direct_max_irq = direct_max; +return domain; +} +EXPORT_SYMBOL_GPL (__irq_domain_alloc); + +/** +* __irq_domain_register() - Register a new irq_domain that has been +* previously allocated with __irq_domain_alloc(). +* @domain: irq_domain to registers +*/ +void __irq_domain_register (struct irq_domain *domain) +{mutex_lock (&irq_domain_mutex);list_add (&domain->link, &irq_domain_list);mutex_unlock (&irq_domain_mutex);pr_debug ("Added domain %s\n" , domain->name); -return domain; } -EXPORT_SYMBOL_GPL (__irq_domain_add); +EXPORT_SYMBOL_GPL (__irq_domain_register);/** * irq_domain_remove() - Remove an irq domain.
@@ -127,7 +138,7 @@ struct irq_domain *irq_domain_add_simple(struct device_node *of_node, {struct irq_domain *domain; - domain =__irq_domain_add (of_node, size, size,0 , ops, host_data); + domain =__irq_domain_alloc (of_node, size, size,0 , ops, host_data);if (!domain)return NULL ;
@@ -143,6 +154,8 @@ struct irq_domain *irq_domain_add_simple(struct device_node *of_node,irq_domain_associate_many (domain, first_irq,0 , size); } +__irq_domain_register (domain); +return domain; }EXPORT_SYMBOL_GPL (irq_domain_add_simple);
@@ -171,12 +184,13 @@ struct irq_domain *irq_domain_add_legacy(struct device_node *of_node, {struct irq_domain *domain; - domain =__irq_domain_add (of_node, first_hwirq + size, - first_hwirq + size,0 , ops, host_data); + domain =__irq_domain_alloc (of_node, first_hwirq + size, + first_hwirq + size,0 , ops, host_data);if (!domain)return NULL ;irq_domain_associate_many (domain, first_irq, first_hwirq, size); +__irq_domain_register (domain);return domain; }
Signature · 1 line
1.8.1.2
PATCH v6 6/13 irqdomain: add support to associate an irq_domain with a msi_chip
In reply to Thomas PetazzoniMessage Signaled Interrupts are a PCI-specific mechanism that allows PCI devices to notify interrupts to the CPU using in-band messages. The PCI subsystem represents an MSI-capable interrupt controller as an msi_chip structure, and this patch improves the irqdomain subsystem with a new pointer associating an irq_domain with the corresponding msi_chip.
The irq_domain structure gains a pointer to a msi_chip structure, and a new helper function irq_domain_add_msi() is added to help in allocating, initializing and registering an irq_domain for a MSI-type interrupt controller.
--- include/linux/irqdomain.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
include/linux/irqdomain.h +18 -0
@@ -38,6 +38,7 @@struct device_node ;struct irq_domain ;struct of_device_id ; +struct msi_chip ;/* Number of irqs reserved for a legacy isa controller */ #define NUM_ISA_INTERRUPTS 16
@@ -101,6 +102,7 @@ struct irq_domain {/* Optional data */ struct device_node *of_node;struct irq_domain_chip_generic *gc; +struct msi_chip *msi_chip;/* reverse map data. The linear map gets appended to the irq_domain */ irq_hw_number_t hwirq_max;
@@ -177,6 +179,22 @@ static inline struct irq_domain *irq_domain_add_tree(struct device_node *of_node__irq_domain_register (d);return d; } +static inline struct irq_domain *irq_domain_add_msi (struct device_node *of_node, +unsigned int size, +const struct irq_domain_ops *ops, +struct msi_chip *msi_chip, +void *host_data) +{ +struct irq_domain *d; + d =__irq_domain_alloc (of_node, size, size,0 , ops, host_data); +if (d) { + d->msi_chip = msi_chip; +__irq_domain_register (d); + } + +return d; +} +extern void irq_domain_remove (struct irq_domain *host);
Signature · 1 line
1.8.1.2
PATCH v6 7/13 irqdomain: add function to find a MSI irq_domain
In reply to Thomas PetazzoniNow that an irq_domain can be associated to a msi_chip structure, a given PCIe driver will want to find this irq_domain, based on the Device Tree node of the interrupt controller, as pointed by the 'msi-controller' DT property.
However, since on those platforms a single piece of hardware, represented by a single DT node can provide both a "normal" IRQ domain and a MSI-type IRQ domain, we need separate lookup functions to distinguish them.
This patch makes irq_find_host() find only non-MSI-type IRQ domains, and introduces irq_find_msi_host() to find only MSI-type IRQ domains. It does so by factorizing the irq_find_host() logic into __irq_find_host().
--- include/linux/irqdomain.h | 21 ++++++++++++++++++++- kernel/irq/irqdomain.c | 13 ++++++++++--- 2 files changed, 30 insertions(+), 4 deletions(-)
include/linux/irqdomain.h +20 -1
@@ -129,7 +129,8 @@ struct irq_domain *irq_domain_add_legacy(struct device_node *of_node,irq_hw_number_t first_hwirq, const struct irq_domain_ops *ops, void *host_data); -extern struct irq_domain *irq_find_host (struct device_node *node); +struct irq_domain *__irq_find_host (struct device_node *node, +bool findmsi);extern void irq_set_default_host (struct irq_domain *host);/**
@@ -196,6 +197,24 @@ static inline struct irq_domain *irq_domain_add_msi(struct device_node *of_node, } +/** +* irq_find_host() - Locates a domain for a given device node +* @node: device-tree node of the interrupt controller +*/ +static inline struct irq_domain *irq_find_host (struct device_node *node) +{ +return __irq_find_host (node, false); +} + +/** +* irq_find_msi_host() - Locates a MSI domain for a given device node +* @node: device-tree node of the interrupt controller +*/ +static inline struct irq_domain *irq_find_msi_host (struct device_node *node) +{ +return __irq_find_host (node, true); +} +extern void irq_domain_remove (struct irq_domain *host); extern int irq_domain_associate(struct irq_domain *domain, unsigned int irq,
kernel/irq/irqdomain.c +10 -3
@@ -197,10 +197,14 @@ struct irq_domain *irq_domain_add_legacy(struct device_node *of_node,EXPORT_SYMBOL_GPL (irq_domain_add_legacy);/** -* irq_find_host() - Locates a domain for a given device node +* __irq_find_host() - Locates a domain for a given device node, +* taking into account whether the domain is of MSI-type or not. * @node: device-tree node of the interrupt controller +* @findmsi: true when the domain being search is of MSI-type, false +* otherwise. */ -struct irq_domain *irq_find_host (struct device_node *node) +struct irq_domain *__irq_find_host (struct device_node *node, +bool findmsi) {struct irq_domain *h, *found =NULL ;int rc;
@@ -212,6 +216,9 @@ struct irq_domain *irq_find_host(struct device_node *node)*/ mutex_lock (&irq_domain_mutex);list_for_each_entry (h, &irq_domain_list, link) { +if ((findmsi && !h->msi_chip) || + (!findmsi && h->msi_chip)) +continue ;if (h->ops->match) rc = h->ops->match (h, node);else
@@ -225,7 +232,7 @@ struct irq_domain *irq_find_host(struct device_node *node)mutex_unlock (&irq_domain_mutex);return found; } -EXPORT_SYMBOL_GPL (irq_find_host); +EXPORT_SYMBOL_GPL (__irq_find_host);/** * irq_set_default_host() - Set a "default" irq domain
Signature · 1 line
1.8.1.2
PATCH v6 8/13 irqchip: armada-370-xp: properly request resources
In reply to Thomas PetazzoniInstead of using of_iomap(), we now use of_address_to_resource(), request_mem_region() and ioremap(). This allows the corresponding I/O regions to be properly requested and visible in /proc/iomem.
The main motivation for this change is that the introduction of the MSI support requires us to get the physical address of the main interrupt controller registers, so we will need the corresponding 'struct resource' anyway.
We also take this opportunity to change a panic() to BUG_ON(), in order to be consistent with the rest of the driver.
--- drivers/irqchip/irq-armada-370-xp.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-)
drivers/irqchip/irq-armada-370-xp.c +16 -4
@@ -248,12 +248,25 @@ armada_370_xp_handle_irq(struct pt_regs *regs)static int __init armada_370_xp_mpic_of_init (struct device_node *node,struct device_node *parent) { +struct resource main_int_res, per_cpu_int_res;u32 control; - main_int_base =of_iomap (node,0 ); - per_cpu_int_base =of_iomap (node,1 ); +BUG_ON (of_address_to_resource (node,0 , &main_int_res)); +BUG_ON (of_address_to_resource (node,1 , &per_cpu_int_res)); +BUG_ON (!request_mem_region (main_int_res.start, +resource_size (&main_int_res), + node->full_name)); +BUG_ON (!request_mem_region (per_cpu_int_res.start, +resource_size (&per_cpu_int_res), + node->full_name)); + + main_int_base =ioremap (main_int_res.start, +resource_size (&main_int_res));BUG_ON (!main_int_base); + + per_cpu_int_base =ioremap (per_cpu_int_res.start, +resource_size (&per_cpu_int_res));BUG_ON (!per_cpu_int_base); control =readl (main_int_base +ARMADA_370_XP_INT_CONTROL );
@@ -262,8 +275,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,irq_domain_add_linear (node, (control >>2 ) &0x3ff , &armada_370_xp_mpic_irq_ops,NULL ); -if (!armada_370_xp_mpic_domain) -panic ("Unable to add Armada_370_Xp MPIC irq domain (DT)\n" ); +BUG_ON (!armada_370_xp_mpic_domain);irq_set_default_host (armada_370_xp_mpic_domain);
Signature · 1 line
1.8.1.2
PATCH v6 9/13 irqchip: armada-370-xp: implement MSI support
In reply to Thomas PetazzoniThis commit introduces the support for the MSI interrupts in the armada-370-xp interrupt controller driver. It registers an MSI chip to the MSI chip registry, which will be used by the Marvell PCIe host controller driver.
The MSI interrupts use the 16 high doorbells, and are therefore notified using IRQ1 of the main interrupt controller.
--- .../devicetree/bindings/arm/armada-370-xp-mpic.txt | 3 + drivers/irqchip/irq-armada-370-xp.c | 133 ++++++++++++++++++++- 2 files changed, 135 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt +3 -0
@@ -4,6 +4,8 @@ Marvell Armada 370 and Armada XP Interrupt Controller Required properties: - compatible: Should be "marvell,mpic" - interrupt-controller: Identifies the node as an interrupt controller. +- msi-controller: Identifies the node as an PCI Message Signaled + Interrupt controller. - #interrupt-cells: The number of cells to define the interrupts. Should be 1. The cell is the IRQ number
@@ -24,6 +26,7 @@ Example: #address-cells = <1>; #size-cells = <1>; interrupt-controller; + msi-controller; reg = <0xd0020a00 0x1d0>, <0xd0021070 0x58>; };
drivers/irqchip/irq-armada-370-xp.c +132 -1
181 lines not on this page · raw message
Signature · 1 line
1.8.1.2
PATCH v6 10/13 ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pci
In reply to Thomas PetazzoniSome PCI drivers may need to adjust the pci_bus structure after it has been allocated by the Linux PCI core. The PCI core allows architectures to implement the pcibios_add_bus() and pcibios_remove_bus() for this purpose. This commit therefore extends the hw_pci and pci_sys_data structures of the ARM PCI core to allow PCI drivers to register ->add_bus() and ->remove_bus() in hw_pci, which will get called when a bus is added or removed from the system.
This will be used for example by the Marvell PCIe driver to connect a particular PCI bus with its corresponding MSI chip to handle Message Signaled Interrupts.
--- arch/arm/include/asm/mach/pci.h | 4 ++++ arch/arm/kernel/bios32.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+)
arch/arm/include/asm/mach/pci.h +4 -0
@@ -36,6 +36,8 @@ struct hw_pci {resource_size_t start, resource_size_t size, resource_size_t align); +void (*add_bus)(struct pci_bus *bus); +void (*remove_bus)(struct pci_bus *bus); };/*
@@ -63,6 +65,8 @@ struct pci_sys_data {resource_size_t start, resource_size_t size, resource_size_t align); +void (*add_bus)(struct pci_bus *bus); +void (*remove_bus)(struct pci_bus *bus);void *private_data;/* platform controller private data */ };
arch/arm/kernel/bios32.c +16 -0
@@ -363,6 +363,20 @@ void pcibios_fixup_bus(struct pci_bus *bus) }EXPORT_SYMBOL (pcibios_fixup_bus); +void pcibios_add_bus (struct pci_bus *bus) +{ +struct pci_sys_data *sys = bus->sysdata; +if (sys->add_bus) + sys->add_bus (bus); +} + +void pcibios_remove_bus (struct pci_bus *bus) +{ +struct pci_sys_data *sys = bus->sysdata; +if (sys->remove_bus) + sys->remove_bus (bus); +} +/* * Swizzle the device pin each time we cross a bridge. If a platform does * not provide a swizzle function, we perform the standard PCI swizzling.
@@ -464,6 +478,8 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, sys->swizzle = hw->swizzle; sys->map_irq = hw->map_irq; sys->align_resource = hw->align_resource; + sys->add_bus = hw->add_bus; + sys->remove_bus = hw->remove_bus;INIT_LIST_HEAD (&sys->resources);if (hw->private_data)
Signature · 1 line
1.8.1.2
PATCH v6 11/13 ARM: mvebu: the MPIC now provides MSI controller features
In reply to Thomas PetazzoniAdds the 'msi-controller' property to the main interrupt controller Device Tree node, to indicate that it can now behave as a MSI controller.
--- arch/arm/boot/dts/armada-370-xp.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm/boot/dts/armada-370-xp.dtsi +1 -0
@@ -56,6 +56,7 @@ #interrupt-cells = <1>; #size-cells = <1>; interrupt-controller; + msi-controller; }; coherency-fabric at 20200 {
Signature · 1 line
1.8.1.2
PATCH v6 12/13 PCI: mvebu: add support for MSI
In reply to Thomas PetazzoniThis commit adds support for Message Signaled Interrupts in the Marvell PCIe host controller. The work is very simple: it simply gets a reference to the msi_chip associated to the PCIe controller thanks to the msi-parent DT property, and stores this reference in the pci_bus structure. This is enough to let the Linux PCI core use the functions of msi_chip to setup and teardown MSIs.
--- .../devicetree/bindings/pci/mvebu-pci.txt | 3 +++ drivers/pci/host/pci-mvebu.c | 31 ++++++++++++++++++++++ 2 files changed, 34 insertions(+)
Documentation/devicetree/bindings/pci/mvebu-pci.txt +3 -0
@@ -12,6 +12,8 @@ Mandatory properties: - device_type, set to "pci" - ranges: ranges for the PCI memory and I/O regions, as well as the MMIO registers to control the PCIe interfaces. +- msi-parent: Link to the hardware entity that serves as the Message + Signaled Interrupt controller for this PCI controller. In addition, the Device Tree node must have sub-nodes describing each PCIe interface, having the following mandatory properties:
@@ -46,6 +48,7 @@ pcie-controller { #size-cells = <2>; bus-range = <0x00 0xff>; + msi-parent = <&mpic>; ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
drivers/pci/host/pci-mvebu.c +31 -0
@@ -11,6 +11,7 @@#include <linux/clk.h> #include <linux/module.h> #include <linux/mbus.h> +#include <linux/msi.h> #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/of_address.h>
@@ -107,6 +108,7 @@ struct mvebu_pcie_port;struct mvebu_pcie {struct platform_device *pdev;struct mvebu_pcie_port *ports; +struct msi_chip *msi;struct resource io;struct resource realio;struct resource mem;
@@ -695,6 +697,12 @@ static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)return bus; } +void mvebu_pcie_add_bus (struct pci_bus *bus) +{ +struct mvebu_pcie *pcie =sys_to_pcie (bus->sysdata); + bus->msi = pcie->msi; +} + resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, const struct resource *res, resource_size_t start,
@@ -731,6 +739,7 @@ static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie) hw.map_irq = mvebu_pcie_map_irq; hw.ops = &mvebu_pcie_ops; hw.align_resource = mvebu_pcie_align_resource; + hw.add_bus = mvebu_pcie_add_bus;pci_common_init (&hw); }
@@ -755,6 +764,26 @@ mvebu_pcie_map_registers(struct platform_device *pdev,return devm_request_and_ioremap (&pdev->dev, ®s); } +static void __init mvebu_pcie_msi_enable (struct mvebu_pcie *pcie) +{ +struct device_node *msi_node; +struct irq_domain *msi_domain; + + msi_node =of_parse_phandle (pcie->pdev->dev.of_node, +"msi-parent" ,0 ); +if (!msi_node) +return ; + + msi_domain =irq_find_msi_host (msi_node); +if (!msi_domain) +return ; + + pcie->msi = msi_domain->msi_chip; + +if (pcie->msi) + pcie->msi->dev = &pcie->pdev->dev; +} +static int __init mvebu_pcie_probe (struct platform_device *pdev) {struct mvebu_pcie *pcie;
@@ -879,6 +908,8 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev) i++; } +mvebu_pcie_msi_enable (pcie); +mvebu_pcie_enable (pcie);return 0 ;
Signature · 1 line
1.8.1.2
PATCH v6 13/13 ARM: mvebu: link PCIe controllers to the MSI controller
In reply to Thomas PetazzoniThis commit adjusts the Armada 370 and Armada XP PCIe controllers Device Tree informations to reference their MSI controller. In the case of this platform, the MSI controller is implemented by the MPIC.
--- arch/arm/boot/dts/armada-370.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 1 + 4 files changed, 4 insertions(+)
arch/arm/boot/dts/armada-370.dtsi +1 -0
@@ -178,6 +178,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
arch/arm/boot/dts/armada-xp-mv78230.dtsi +1 -0
@@ -91,6 +91,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
arch/arm/boot/dts/armada-xp-mv78260.dtsi +1 -0
@@ -111,6 +111,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
arch/arm/boot/dts/armada-xp-mv78460.dtsi +1 -0
@@ -127,6 +127,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
Signature · 1 line
1.8.1.2
v6 cover MSI support for Marvell EBU PCIe driver
In reply to Thomas PetazzoniQuoted 7 lines · Thomas Petazzoni
Hello,
This set of patches introduces Message Signaled Interrupt support in the Marvell EBU PCIe driver. It has been successfully tested on the Armada XP GP platform with an Intel e1000e PCIe network card that supports MSI.
Quoted 7 lines
This patch set is intended for merging in 3.12, so the respective maintainers of the different areas are invited to review/ack the patches, see below for the details. Note that several of those patches are also needed for the Tegra PCIe driver.
There are still missing ACKs from Grant Likely (5, 6, 7), Thomas Gleixner (8, 9) and Bjorn Helgaas (2, 12).
Recall that Grant gave up most/all of his maintainerships, so you probably want someone else to approve patches 5/6/7. It looks like Benjamin Herrenschmidt <[email protected]> is listed in MAINTAINERS for those patches.
v6 cover MSI support for Marvell EBU PCIe driver
Dear Stephen Warren,
Quoted 13 lines · Stephen Warren
Quoted 12 lines · Thomas Petazzoni
Hello,
This set of patches introduces Message Signaled Interrupt support in the Marvell EBU PCIe driver. It has been successfully tested on the Armada XP GP platform with an Intel e1000e PCIe network card that supports MSI.
This patch set is intended for merging in 3.12, so the respective maintainers of the different areas are invited to review/ack the patches, see below for the details. Note that several of those patches are also needed for the Tegra PCIe driver.
Quoted 7 lines
Quoted 2 lines
There are still missing ACKs from Grant Likely (5, 6, 7), Thomas Gleixner (8, 9) and Bjorn Helgaas (2, 12).
Recall that Grant gave up most/all of his maintainerships, so you probably want someone else to approve patches 5/6/7. It looks like Benjamin Herrenschmidt <[email protected]> is listed in
MAINTAINERSfor those patches.
Thanks. I see you've Cc'ed Ben, thanks.
However, it is worth noting that the previous approach was based on a drivers/of registry of msi_chip, which Rob Herring, as drivers/of maintainer, has Acked. But then, this Sunday, Grant said he disagreed with the approach. So even though he is no longer an official maintainer, he seems to be the one who decides what direction drivers/of and irqdomain should be having.
Of course, if Ben could look at those irqdomain patches and give his Acked-by, it'd be great.
Thanks!
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Bjorn Helgaas
maintainerv6 cover MSI support for Marvell EBU PCIe driver
In reply to Thomas PetazzoniQuoted 7 lines · Thomas Petazzoni
Hello,
This set of patches introduces Message Signaled Interrupt support in the Marvell EBU PCIe driver. It has been successfully tested on the Armada XP GP platform with an Intel e1000e PCIe network card that supports MSI.
Quoted 7 lines
This patch set is intended for merging in 3.12, so the respective maintainers of the different areas are invited to review/ack the patches, see below for the details. Note that several of those patches are also needed for the Tegra PCIe driver.
There are still missing ACKs from Grant Likely (5, 6, 7), Thomas Gleixner (8, 9) and Bjorn Helgaas (2, 12).
I just acked 2, and my ack is already on 12. Let me know if you need anything else from me.
Bjorn
v6 cover MSI support for Marvell EBU PCIe driver
Dear Bjorn Helgaas,
Quoted 14 lines · Bjorn Helgaas
Quoted 12 lines · Thomas Petazzoni
Hello,
This set of patches introduces Message Signaled Interrupt support in the Marvell EBU PCIe driver. It has been successfully tested on the Armada XP GP platform with an Intel e1000e PCIe network card that supports MSI.
This patch set is intended for merging in 3.12, so the respective maintainers of the different areas are invited to review/ack the patches, see below for the details. Note that several of those patches are also needed for the Tegra PCIe driver.
Quoted 5 lines
Quoted 2 lines
There are still missing ACKs from Grant Likely (5, 6, 7), Thomas Gleixner (8, 9) and Bjorn Helgaas (2, 12).
I just acked 2, and my ack is already on 12. Let me know if you need anything else from me.
That's good, thanks a lot!
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
v6 cover MSI support for Marvell EBU PCIe driver
In reply to Thomas PetazzoniBenjamin, Thomas,
This patch set has been around for two months now, and I would really like to see it merged. Your ACKs are the only ones missing to merge the whole thing.
Would you mind having a look at:
* Patches 4, 5, 6, 7 for Benjamin as the irqdomain maintainer.
* Patches 8 and 9 for Thomas as the drivers/irqchip maintainer.
Thanks a lot!
Thomas
Quoted 244 lines · Thomas Petazzoni
Hello,
This set of patches introduces Message Signaled Interrupt support in the Marvell EBU PCIe driver. It has been successfully tested on the Armada XP GP platform with an Intel e1000e PCIe network card that supports MSI.
This patch set is intended for merging in 3.12, so the respective maintainers of the different areas are invited to review/ack the patches, see below for the details. Note that several of those patches are also needed for the Tegra PCIe driver.
There are still missing ACKs from Grant Likely (5, 6, 7), Thomas Gleixner (8, 9) and Bjorn Helgaas (2, 12).
The patches do the following:
* Patch 1 reworks how the architecture-specific MSI functions can be overriden by architecture-specific code, by using weak functions. It was suggested by Bjorn Helgaas.
This patch has been acked by Bjorn Helgaas, the PCI maintainter.
* Patch 2 removes the
ARCH_SUPPORTS_MSIhidden kconfig boolean which is no longer needed now that we have weak functions for all MSI architecture-specific hooks.This patch needs the Ack from Bjorn Helgaas, and the relevant architecture maintainers.
* Patch 3 adds a minimal
msi_chipinfrastructure, that allows apci_busto be connected to amsi_chip, and that provides default implementations of the architecture-specific MSI functions to usemsi_chip.This patch has been acked by Bjorn Helgaas, the PCI maintainter.
* Patch 4 adds an IRQ domain function that allows to allocate dynamically a free hwirq number from an IRQ domain, and create a virq mapping to it. It was suggested by Grant Likely in order to remove the hwirq allocation code from the IRQ driver itself.
Patch has been Acked by Grant Likely,
irq_domainmaintainer.* Patch 5 refactors the
__irq_domain_add()function in theirq_domaincode, in preparation for the introduction of MSI support inirq_domain.This patch needs the ACK of Grant Likely.
* Patch 6 allows to create an
irq_domainassociated with amsi_chip, thanks to the newirq_domain_add_msi()function.This patch needs the ACK of Grant Likely.
* Patch 7 adds a new function
irq_find_msi_host()to find the MSI-type interrupt controller associated to a given DT node, and adjustsirq_find_host()to not match MSI-type interrupt controllers.This patch needs the ACK of Grant Likely.
* Patch 8 makes some not very interesting preparation in the Armada 370/XP IRQ controller driver.
This patch needs the Ack from Thomas Gleixner.
* Patch 9 implements the MSI support in the Armada 370/XP IRQ controller driver. It registers an
msi_chipusing themsi_chip_add()function added in PATCH 3.This patch needs the Ack from Thomas Gleixner.
* Patch 10 extends the ARM PCI core to expose ->add_bus() and ->remove_bus() hooks to PCI drivers. This was suggested by Bjorn Helgaas to allow the PCI driver to connected the PCI busses with the corresponding MSI chip.
This patch has been Acked by Russell King, the ARM maintainer.
* Patch 11 adjust the Armada 370/XP Device Tree to indicate that the MPIC is not only an interrupt-controller, but also an msi-controller.
This patch needs the Ack from Jason Cooper, Gregory Clement and/or Andrew Lunn, the Marvell maintainers.
* Patch 12 adds MSI support in the Marvell PCIe host controller driver. The work to do here is minimal: get a reference to the msi-parent controller thanks to
msi_chip_find_by_of_node(), and link it to thepci_busstructure before the bus gets enumerated.This patch needs the Ack from Bjorn Helgaas.
* Patch 13 adjusts the Armada 370/XP Device Tree to add the msi-parent properties in the PCIe controller nodes.
This patch needs the Ack from Jason Cooper, Gregory Clement and/or Andrew Lunn, the Marvell Maintainers.
This version 6 follows:
* PATCH version 5 sent on July, 15th 2013
* PATCH version 4 sent on July, 1st 2013
* PATCH version 3 sent on June, 19th 2013
* PATCH version 2 sent on June, 6th 2013
* RFC version 1 sent on March, 26th 2013Changes since v5:
* Rebased on top of 3.11-rc3.
* Implemented the suggestions of Grant Likely on "irqdomain: add
irq_alloc_mapping()function" and added his Acked-by.* Added Bjorn Helgaas Acked-by on "PCI: use weak functions for MSI arch-specific functions".
* Added Bjorn Helgaas Acked-by on "PCI: Introduce new MSI chip infrastructure".
* Remove the
drivers/ofglobal registry ofirq_chip, and as suggested by Grant Likely, create an association between anirq_domainand amsi_chip. This required refactoring the__irq_domain_add()function, adding a 'msi_chip' pointer to 'irq_domain', adding anirq_domain_add_msi()function and airq_find_msi_host()function.* Added Russell King Acked-by on "ARM: pci: add ->add_bus() and ->remove_bus() hooks to
hw_pci"Changes since v4:
* Rebased on top of 3.11-rc1.
* Slightly rework the implementation of
arch_setup_msi_irq(),arch_teardown_msi_irqandarch_msi_check_device()according to the suggestions of Bjorn Helgaas (PATCH 4)* Make a few improvements to the
msi_chipregistry, according to the suggestion of Bjorn Helgaas and Rob Herring: coding style fixes, usage of mutex while traversing the list ofmsi_chip, usage of of_pci_msi_* prefix instead of just of_msi_*.Changes since v3:
* Keep only a
default_teardown_msi_irqs()function needed for the Xen PCI x86 code, and remove all other default_*() function and put the default behavior directly in the weak functions. Suggested by Thierry Redding and Bjorn Helgaas.* Misc small improvements the MSI chip registry code: compiled only under
CONFIG_PCI_MSI, functions exported to modules, addition of anof_msi_chip_remove()function, renaming ofof_msi_chip_find_by_node()toof_find_msi_chip_by_node(), move the test of the "msi-controller" property to theof_msi_chip_add()function, renamed thelist_headfield from link to list, added dummy functions in the header files when !CONFIG_PCI_MSI && !CONFIG_OF. All suggested by Thierry Redding.* Add a patch that entirely removes the
ARCH_SUPPORTS_MSI, as we now have weak functions, so even if an arch doesn't actually use/support MSI, the code will build properly. Suggested by Thierry Redding.* Added Device Tree binding documentation updates for the IRQ controller and the PCIe controller.
Changes since v2:
* Add an IRQ domain function that allows to allocate dynamically a free hwirq number from an IRQ domain, and create a virq mapping to it. It was suggested by Grant Likely in order to remove the hwirq allocation code from the IRQ driver itself. (PATCH 1)
* Separate the use of weak functions from the introduction of the
msi_chipinfrastructure, and use weak functions for all architecture-specific MSI hooks. Suggested by Bjorn Helgaas (PATCH 2).* Move the
msi_chipregistry todrivers/of. Suggested by Bjorn Helgaas (PATCH 4).* Use
pcibios_add_bus()andpcibios_remove_bus()to connect the PCI busses to theirmsi_chip, as suggested by Bjorn Helgaas. Requires some ARM PCI core changes (PATCH 7), and then changes to the PCI driver itself (PATCH 9).This set of patches applies on top of 3.11-rc3, and is available as a Git branch at
https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-msi-v6.Thanks,
Thomas
Thierry Reding (1):
PCI: Introduce new MSI chip infrastructureThomas Petazzoni (12):
PCI: use weak functions for MSI arch-specific functions
PCI: removeARCH_SUPPORTS_MSIkconfig option
irqdomain: addirq_alloc_mapping()function
irqdomain: refactor__irq_domain_add()
irqdomain: add support to associate anirq_domainwith amsi_chip
irqdomain: add function to find a MSIirq_domain
irqchip: armada-370-xp: properly request resources
irqchip: armada-370-xp: implement MSI support
ARM: pci: add ->add_bus() and ->remove_bus() hooks tohw_pci
ARM: mvebu: the MPIC now provides MSI controller features
PCI: mvebu: add support for MSI
ARM: mvebu: link PCIe controllers to the MSI controller.../devicetree/bindings/arm/armada-370-xp-mpic.txt | 3 + .../devicetree/bindings/pci/mvebu-pci.txt | 3 + arch/arm/Kconfig | 1 - arch/arm/boot/dts/armada-370-xp.dtsi | 1 + arch/arm/boot/dts/armada-370.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 1 + arch/arm/include/asm/mach/pci.h | 4 + arch/arm/kernel/bios32.c | 16 +++ arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 2 - arch/mips/include/asm/pci.h | 5 - arch/powerpc/Kconfig | 1 - arch/powerpc/include/asm/pci.h | 5 - arch/s390/Kconfig | 1 - arch/s390/include/asm/pci.h | 4 - arch/sparc/Kconfig | 1 - arch/tile/Kconfig | 1 - arch/x86/Kconfig | 1 - arch/x86/include/asm/pci.h | 28 ---- arch/x86/kernel/x86_init.c | 21 +++ drivers/irqchip/irq-armada-370-xp.c | 153 ++++++++++++++++++++- drivers/pci/Kconfig | 4 - drivers/pci/host/pci-mvebu.c | 31 +++++ drivers/pci/msi.c | 66 +++++---- drivers/pci/probe.c | 1 + include/linux/irqdomain.h | 62 ++++++++- include/linux/msi.h | 18 ++- include/linux/pci.h | 1 + kernel/irq/irqdomain.c | 89 +++++++++--- 31 files changed, 422 insertions(+), 106 deletions(-)
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
v6 cover MSI support for Marvell EBU PCIe driver
Quoted 9 lines · Thomas Petazzoni
Benjamin, Thomas,
This patch set has been around for two months now, and I would really like to see it merged. Your ACKs are the only ones missing to merge the whole thing.
Would you mind having a look at:
* Patches 4, 5, 6, 7 for Benjamin as the irqdomain maintainer.
Ah sorry, I wasn't aware you were actually waiting for my acks, I didn't read the whole thread, my bad. I'm not irqdomain maintainer btw. I wrote the original powerpc implementation but since then it has been taken over by Grant and others. But I can certainly comment :-)
Cheers,
Ben.
Quoted 254 lines
* Patches 8 and 9 for Thomas as the
drivers/irqchipmaintainer.Thanks a lot!
Thomas
Quoted 244 lines · Thomas Petazzoni
Hello,
This set of patches introduces Message Signaled Interrupt support in the Marvell EBU PCIe driver. It has been successfully tested on the Armada XP GP platform with an Intel e1000e PCIe network card that supports MSI.
This patch set is intended for merging in 3.12, so the respective maintainers of the different areas are invited to review/ack the patches, see below for the details. Note that several of those patches are also needed for the Tegra PCIe driver.
There are still missing ACKs from Grant Likely (5, 6, 7), Thomas Gleixner (8, 9) and Bjorn Helgaas (2, 12).
The patches do the following:
* Patch 1 reworks how the architecture-specific MSI functions can be overriden by architecture-specific code, by using weak functions. It was suggested by Bjorn Helgaas.
This patch has been acked by Bjorn Helgaas, the PCI maintainter.
* Patch 2 removes the
ARCH_SUPPORTS_MSIhidden kconfig boolean which is no longer needed now that we have weak functions for all MSI architecture-specific hooks.This patch needs the Ack from Bjorn Helgaas, and the relevant architecture maintainers.
* Patch 3 adds a minimal
msi_chipinfrastructure, that allows apci_busto be connected to amsi_chip, and that provides default implementations of the architecture-specific MSI functions to usemsi_chip.This patch has been acked by Bjorn Helgaas, the PCI maintainter.
* Patch 4 adds an IRQ domain function that allows to allocate dynamically a free hwirq number from an IRQ domain, and create a virq mapping to it. It was suggested by Grant Likely in order to remove the hwirq allocation code from the IRQ driver itself.
Patch has been Acked by Grant Likely,
irq_domainmaintainer.* Patch 5 refactors the
__irq_domain_add()function in theirq_domaincode, in preparation for the introduction of MSI support inirq_domain.This patch needs the ACK of Grant Likely.
* Patch 6 allows to create an
irq_domainassociated with amsi_chip, thanks to the newirq_domain_add_msi()function.This patch needs the ACK of Grant Likely.
* Patch 7 adds a new function
irq_find_msi_host()to find the MSI-type interrupt controller associated to a given DT node, and adjustsirq_find_host()to not match MSI-type interrupt controllers.This patch needs the ACK of Grant Likely.
* Patch 8 makes some not very interesting preparation in the Armada 370/XP IRQ controller driver.
This patch needs the Ack from Thomas Gleixner.
* Patch 9 implements the MSI support in the Armada 370/XP IRQ controller driver. It registers an
msi_chipusing themsi_chip_add()function added in PATCH 3.This patch needs the Ack from Thomas Gleixner.
* Patch 10 extends the ARM PCI core to expose ->add_bus() and ->remove_bus() hooks to PCI drivers. This was suggested by Bjorn Helgaas to allow the PCI driver to connected the PCI busses with the corresponding MSI chip.
This patch has been Acked by Russell King, the ARM maintainer.
* Patch 11 adjust the Armada 370/XP Device Tree to indicate that the MPIC is not only an interrupt-controller, but also an msi-controller.
This patch needs the Ack from Jason Cooper, Gregory Clement and/or Andrew Lunn, the Marvell maintainers.
* Patch 12 adds MSI support in the Marvell PCIe host controller driver. The work to do here is minimal: get a reference to the msi-parent controller thanks to
msi_chip_find_by_of_node(), and link it to thepci_busstructure before the bus gets enumerated.This patch needs the Ack from Bjorn Helgaas.
* Patch 13 adjusts the Armada 370/XP Device Tree to add the msi-parent properties in the PCIe controller nodes.
This patch needs the Ack from Jason Cooper, Gregory Clement and/or Andrew Lunn, the Marvell Maintainers.
This version 6 follows:
* PATCH version 5 sent on July, 15th 2013
* PATCH version 4 sent on July, 1st 2013
* PATCH version 3 sent on June, 19th 2013
* PATCH version 2 sent on June, 6th 2013
* RFC version 1 sent on March, 26th 2013Changes since v5:
* Rebased on top of 3.11-rc3.
* Implemented the suggestions of Grant Likely on "irqdomain: add
irq_alloc_mapping()function" and added his Acked-by.* Added Bjorn Helgaas Acked-by on "PCI: use weak functions for MSI arch-specific functions".
* Added Bjorn Helgaas Acked-by on "PCI: Introduce new MSI chip infrastructure".
* Remove the
drivers/ofglobal registry ofirq_chip, and as suggested by Grant Likely, create an association between anirq_domainand amsi_chip. This required refactoring the__irq_domain_add()function, adding a 'msi_chip' pointer to 'irq_domain', adding anirq_domain_add_msi()function and airq_find_msi_host()function.* Added Russell King Acked-by on "ARM: pci: add ->add_bus() and ->remove_bus() hooks to
hw_pci"Changes since v4:
* Rebased on top of 3.11-rc1.
* Slightly rework the implementation of
arch_setup_msi_irq(),arch_teardown_msi_irqandarch_msi_check_device()according to the suggestions of Bjorn Helgaas (PATCH 4)* Make a few improvements to the
msi_chipregistry, according to the suggestion of Bjorn Helgaas and Rob Herring: coding style fixes, usage of mutex while traversing the list ofmsi_chip, usage of of_pci_msi_* prefix instead of just of_msi_*.Changes since v3:
* Keep only a
default_teardown_msi_irqs()function needed for the Xen PCI x86 code, and remove all other default_*() function and put the default behavior directly in the weak functions. Suggested by Thierry Redding and Bjorn Helgaas.* Misc small improvements the MSI chip registry code: compiled only under
CONFIG_PCI_MSI, functions exported to modules, addition of anof_msi_chip_remove()function, renaming ofof_msi_chip_find_by_node()toof_find_msi_chip_by_node(), move the test of the "msi-controller" property to theof_msi_chip_add()function, renamed thelist_headfield from link to list, added dummy functions in the header files when !CONFIG_PCI_MSI && !CONFIG_OF. All suggested by Thierry Redding.* Add a patch that entirely removes the
ARCH_SUPPORTS_MSI, as we now have weak functions, so even if an arch doesn't actually use/support MSI, the code will build properly. Suggested by Thierry Redding.* Added Device Tree binding documentation updates for the IRQ controller and the PCIe controller.
Changes since v2:
* Add an IRQ domain function that allows to allocate dynamically a free hwirq number from an IRQ domain, and create a virq mapping to it. It was suggested by Grant Likely in order to remove the hwirq allocation code from the IRQ driver itself. (PATCH 1)
* Separate the use of weak functions from the introduction of the
msi_chipinfrastructure, and use weak functions for all architecture-specific MSI hooks. Suggested by Bjorn Helgaas (PATCH 2).* Move the
msi_chipregistry todrivers/of. Suggested by Bjorn Helgaas (PATCH 4).* Use
pcibios_add_bus()andpcibios_remove_bus()to connect the PCI busses to theirmsi_chip, as suggested by Bjorn Helgaas. Requires some ARM PCI core changes (PATCH 7), and then changes to the PCI driver itself (PATCH 9).This set of patches applies on top of 3.11-rc3, and is available as a Git branch at
https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-msi-v6.Thanks,
Thomas
Thierry Reding (1):
PCI: Introduce new MSI chip infrastructureThomas Petazzoni (12):
PCI: use weak functions for MSI arch-specific functions
PCI: removeARCH_SUPPORTS_MSIkconfig option
irqdomain: addirq_alloc_mapping()function
irqdomain: refactor__irq_domain_add()
irqdomain: add support to associate anirq_domainwith amsi_chip
irqdomain: add function to find a MSIirq_domain
irqchip: armada-370-xp: properly request resources
irqchip: armada-370-xp: implement MSI support
ARM: pci: add ->add_bus() and ->remove_bus() hooks tohw_pci
ARM: mvebu: the MPIC now provides MSI controller features
PCI: mvebu: add support for MSI
ARM: mvebu: link PCIe controllers to the MSI controller.../devicetree/bindings/arm/armada-370-xp-mpic.txt | 3 + .../devicetree/bindings/pci/mvebu-pci.txt | 3 + arch/arm/Kconfig | 1 - arch/arm/boot/dts/armada-370-xp.dtsi | 1 + arch/arm/boot/dts/armada-370.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 1 + arch/arm/include/asm/mach/pci.h | 4 + arch/arm/kernel/bios32.c | 16 +++ arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 2 - arch/mips/include/asm/pci.h | 5 - arch/powerpc/Kconfig | 1 - arch/powerpc/include/asm/pci.h | 5 - arch/s390/Kconfig | 1 - arch/s390/include/asm/pci.h | 4 - arch/sparc/Kconfig | 1 - arch/tile/Kconfig | 1 - arch/x86/Kconfig | 1 - arch/x86/include/asm/pci.h | 28 ---- arch/x86/kernel/x86_init.c | 21 +++ drivers/irqchip/irq-armada-370-xp.c | 153 ++++++++++++++++++++- drivers/pci/Kconfig | 4 - drivers/pci/host/pci-mvebu.c | 31 +++++ drivers/pci/msi.c | 66 +++++---- drivers/pci/probe.c | 1 + include/linux/irqdomain.h | 62 ++++++++- include/linux/msi.h | 18 ++- include/linux/pci.h | 1 + kernel/irq/irqdomain.c | 89 +++++++++--- 31 files changed, 422 insertions(+), 106 deletions(-)
v6 cover MSI support for Marvell EBU PCIe driver
Dear Benjamin Herrenschmidt,
Quoted 6 lines · Benjamin Herrenschmidt
Quoted 3 lines
Would you mind having a look at:
* Patches 4, 5, 6, 7 for Benjamin as the irqdomain maintainer.
Ah sorry, I wasn't aware you were actually waiting for my acks, I didn't read the whole thread, my bad. I'm not irqdomain maintainer btw.
Hum, interesting. This is not what my 3.11-rc3 kernel tree says:
IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY)
M: Benjamin Herrenschmidt <[email protected]> S: Maintained
As of a0062d4e3a0a ('MAINTAINERS: Remove Grant Likely'), Grant resigned as the maintainer of IRQ DOMAINS, so you are now the only maintainer for this subsystem.
Quoted 2 lines
I wrote the original powerpc implementation but since then it has been taken over by Grant and others. But I can certainly comment :-)
As the official maintainer, your comments would certainly be appreciated.
Thanks,
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
v6 cover MSI support for Marvell EBU PCIe driver
In reply to Benjamin HerrenschmidtQuoted 7 lines · Benjamin Herrenschmidt
Quoted 6 lines · Thomas Petazzoni
Benjamin, Thomas,
This patch set has been around for two months now, and I would really like to see it merged. Your ACKs are the only ones missing to merge the whole thing.
Quoted 8 lines
Quoted 3 lines
Would you mind having a look at:
* Patches 4, 5, 6, 7 for Benjamin as the irqdomain maintainer.
Ah sorry, I wasn't aware you were actually waiting for my acks, I didn't read the whole thread, my bad. I'm not irqdomain maintainer btw. I wrote the original powerpc implementation but since then it has been taken over by Grant and others. But I can certainly comment :-)
When I moved the code I put both your name and mine in the maintainer file. When I resigned from irq_domain maintainership that left you as the maintainer by default. :-)
I would /like/ to keep maintaining the code, but as evidenced by my complete lack of activity on this thread, I don't have the bandwidth anymore. I'll comment on things whenever I can, but I'm unfortunately very limited in what I can do. :-(
g.
v6 cover MSI support for Marvell EBU PCIe driver
In reply to Thomas PetazzoniQuoted 6 lines · Thomas Petazzoni
Hello,
This set of patches introduces Message Signaled Interrupt support in the Marvell EBU PCIe driver. It has been successfully tested on the Armada XP GP platform with an Intel e1000e PCIe network card that supports MSI.
Thomas,
I tested this set of patches on a custom Marvell Armada XP 78260 based board. It was connected to another system over PCIe, through a non-transparent bridge; MSI support was required. We also tested a similar configuration using the Armada XP GP platform. The patch seems to work for us. Many thanks!
-dp
--
Daniel Price; daniel.price at gmail.com; Twitter: @danielbprice
v6 cover MSI support for Marvell EBU PCIe driver
Quoted 8 lines · Daniel Price
Quoted 6 lines · Thomas Petazzoni
Hello,
This set of patches introduces Message Signaled Interrupt support in the Marvell EBU PCIe driver. It has been successfully tested on the Armada XP GP platform with an Intel e1000e PCIe network card that supports MSI.
Quoted 7 lines
Thomas,
I tested this set of patches on a custom Marvell Armada XP 78260 based board. It was connected to another system over PCIe, through a non-transparent bridge; MSI support was required. We also tested a similar configuration using the Armada XP GP platform. The patch seems to work for us. Many thanks!
That's awesome!
Quoted 1 line
Tested-by Daniel Price <[email protected]>
Thanks, I've added this to the patches.
thx,
Jason.
v6 cover MSI support for Marvell EBU PCIe driver
In reply to Thomas PetazzoniThomas,
In order to get some testing in -next, I've *tentatively* applied this series in the following way:
+---+ mvebu/msi_common (1,2,3,10)
|
+---+---+ mvebu/msi_irq (4-9)
|
+---+---+ mvebu/msi_mvebu (11-13)I had to make one change to patch #9, I protected the last two blocks with #ifdef CONFIG_PCI_MSI to prevent a build failure at that point.
mvebu/msi_common should be appropriate for Thierry to base off, however, I make no guarantees about the stability of the branch until I send a PR for it. Code-wise, it should be fine, but the commit-ids may change due to adding Tested-by's, etc.
thx,
Jason.
Quoted 252 lines · Thomas Petazzoni
Hello,
This set of patches introduces Message Signaled Interrupt support in the Marvell EBU PCIe driver. It has been successfully tested on the Armada XP GP platform with an Intel e1000e PCIe network card that supports MSI.
This patch set is intended for merging in 3.12, so the respective maintainers of the different areas are invited to review/ack the patches, see below for the details. Note that several of those patches are also needed for the Tegra PCIe driver.
There are still missing ACKs from Grant Likely (5, 6, 7), Thomas Gleixner (8, 9) and Bjorn Helgaas (2, 12).
The patches do the following:
* Patch 1 reworks how the architecture-specific MSI functions can be overriden by architecture-specific code, by using weak functions. It was suggested by Bjorn Helgaas.
This patch has been acked by Bjorn Helgaas, the PCI maintainter.
* Patch 2 removes the
ARCH_SUPPORTS_MSIhidden kconfig boolean which is no longer needed now that we have weak functions for all MSI architecture-specific hooks.This patch needs the Ack from Bjorn Helgaas, and the relevant architecture maintainers.
* Patch 3 adds a minimal
msi_chipinfrastructure, that allows apci_busto be connected to amsi_chip, and that provides default implementations of the architecture-specific MSI functions to usemsi_chip.This patch has been acked by Bjorn Helgaas, the PCI maintainter.
* Patch 4 adds an IRQ domain function that allows to allocate dynamically a free hwirq number from an IRQ domain, and create a virq mapping to it. It was suggested by Grant Likely in order to remove the hwirq allocation code from the IRQ driver itself.
Patch has been Acked by Grant Likely,
irq_domainmaintainer.* Patch 5 refactors the
__irq_domain_add()function in theirq_domaincode, in preparation for the introduction of MSI support inirq_domain.This patch needs the ACK of Grant Likely.
* Patch 6 allows to create an
irq_domainassociated with amsi_chip, thanks to the newirq_domain_add_msi()function.This patch needs the ACK of Grant Likely.
* Patch 7 adds a new function
irq_find_msi_host()to find the MSI-type interrupt controller associated to a given DT node, and adjustsirq_find_host()to not match MSI-type interrupt controllers.This patch needs the ACK of Grant Likely.
* Patch 8 makes some not very interesting preparation in the Armada 370/XP IRQ controller driver.
This patch needs the Ack from Thomas Gleixner.
* Patch 9 implements the MSI support in the Armada 370/XP IRQ controller driver. It registers an
msi_chipusing themsi_chip_add()function added in PATCH 3.This patch needs the Ack from Thomas Gleixner.
* Patch 10 extends the ARM PCI core to expose ->add_bus() and ->remove_bus() hooks to PCI drivers. This was suggested by Bjorn Helgaas to allow the PCI driver to connected the PCI busses with the corresponding MSI chip.
This patch has been Acked by Russell King, the ARM maintainer.
* Patch 11 adjust the Armada 370/XP Device Tree to indicate that the MPIC is not only an interrupt-controller, but also an msi-controller.
This patch needs the Ack from Jason Cooper, Gregory Clement and/or Andrew Lunn, the Marvell maintainers.
* Patch 12 adds MSI support in the Marvell PCIe host controller driver. The work to do here is minimal: get a reference to the msi-parent controller thanks to
msi_chip_find_by_of_node(), and link it to thepci_busstructure before the bus gets enumerated.This patch needs the Ack from Bjorn Helgaas.
* Patch 13 adjusts the Armada 370/XP Device Tree to add the msi-parent properties in the PCIe controller nodes.
This patch needs the Ack from Jason Cooper, Gregory Clement and/or Andrew Lunn, the Marvell Maintainers.
This version 6 follows:
* PATCH version 5 sent on July, 15th 2013
* PATCH version 4 sent on July, 1st 2013
* PATCH version 3 sent on June, 19th 2013
* PATCH version 2 sent on June, 6th 2013
* RFC version 1 sent on March, 26th 2013Changes since v5:
* Rebased on top of 3.11-rc3.
* Implemented the suggestions of Grant Likely on "irqdomain: add
irq_alloc_mapping()function" and added his Acked-by.* Added Bjorn Helgaas Acked-by on "PCI: use weak functions for MSI arch-specific functions".
* Added Bjorn Helgaas Acked-by on "PCI: Introduce new MSI chip infrastructure".
* Remove the
drivers/ofglobal registry ofirq_chip, and as suggested by Grant Likely, create an association between anirq_domainand amsi_chip. This required refactoring the__irq_domain_add()function, adding a 'msi_chip' pointer to 'irq_domain', adding anirq_domain_add_msi()function and airq_find_msi_host()function.* Added Russell King Acked-by on "ARM: pci: add ->add_bus() and ->remove_bus() hooks to
hw_pci"Changes since v4:
* Rebased on top of 3.11-rc1.
* Slightly rework the implementation of
arch_setup_msi_irq(),arch_teardown_msi_irqandarch_msi_check_device()according to the suggestions of Bjorn Helgaas (PATCH 4)* Make a few improvements to the
msi_chipregistry, according to the suggestion of Bjorn Helgaas and Rob Herring: coding style fixes, usage of mutex while traversing the list ofmsi_chip, usage of of_pci_msi_* prefix instead of just of_msi_*.Changes since v3:
* Keep only a
default_teardown_msi_irqs()function needed for the Xen PCI x86 code, and remove all other default_*() function and put the default behavior directly in the weak functions. Suggested by Thierry Redding and Bjorn Helgaas.* Misc small improvements the MSI chip registry code: compiled only under
CONFIG_PCI_MSI, functions exported to modules, addition of anof_msi_chip_remove()function, renaming ofof_msi_chip_find_by_node()toof_find_msi_chip_by_node(), move the test of the "msi-controller" property to theof_msi_chip_add()function, renamed thelist_headfield from link to list, added dummy functions in the header files when !CONFIG_PCI_MSI && !CONFIG_OF. All suggested by Thierry Redding.* Add a patch that entirely removes the
ARCH_SUPPORTS_MSI, as we now have weak functions, so even if an arch doesn't actually use/support MSI, the code will build properly. Suggested by Thierry Redding.* Added Device Tree binding documentation updates for the IRQ controller and the PCIe controller.
Changes since v2:
* Add an IRQ domain function that allows to allocate dynamically a free hwirq number from an IRQ domain, and create a virq mapping to it. It was suggested by Grant Likely in order to remove the hwirq allocation code from the IRQ driver itself. (PATCH 1)
* Separate the use of weak functions from the introduction of the
msi_chipinfrastructure, and use weak functions for all architecture-specific MSI hooks. Suggested by Bjorn Helgaas (PATCH 2).* Move the
msi_chipregistry todrivers/of. Suggested by Bjorn Helgaas (PATCH 4).* Use
pcibios_add_bus()andpcibios_remove_bus()to connect the PCI busses to theirmsi_chip, as suggested by Bjorn Helgaas. Requires some ARM PCI core changes (PATCH 7), and then changes to the PCI driver itself (PATCH 9).This set of patches applies on top of 3.11-rc3, and is available as a Git branch at
https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-msi-v6.Thanks,
Thomas
Thierry Reding (1):
PCI: Introduce new MSI chip infrastructureThomas Petazzoni (12):
PCI: use weak functions for MSI arch-specific functions
PCI: removeARCH_SUPPORTS_MSIkconfig option
irqdomain: addirq_alloc_mapping()function
irqdomain: refactor__irq_domain_add()
irqdomain: add support to associate anirq_domainwith amsi_chip
irqdomain: add function to find a MSIirq_domain
irqchip: armada-370-xp: properly request resources
irqchip: armada-370-xp: implement MSI support
ARM: pci: add ->add_bus() and ->remove_bus() hooks tohw_pci
ARM: mvebu: the MPIC now provides MSI controller features
PCI: mvebu: add support for MSI
ARM: mvebu: link PCIe controllers to the MSI controller.../devicetree/bindings/arm/armada-370-xp-mpic.txt | 3 + .../devicetree/bindings/pci/mvebu-pci.txt | 3 + arch/arm/Kconfig | 1 - arch/arm/boot/dts/armada-370-xp.dtsi | 1 + arch/arm/boot/dts/armada-370.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 1 + arch/arm/include/asm/mach/pci.h | 4 + arch/arm/kernel/bios32.c | 16 +++ arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 2 - arch/mips/include/asm/pci.h | 5 - arch/powerpc/Kconfig | 1 - arch/powerpc/include/asm/pci.h | 5 - arch/s390/Kconfig | 1 - arch/s390/include/asm/pci.h | 4 - arch/sparc/Kconfig | 1 - arch/tile/Kconfig | 1 - arch/x86/Kconfig | 1 - arch/x86/include/asm/pci.h | 28 ---- arch/x86/kernel/x86_init.c | 21 +++ drivers/irqchip/irq-armada-370-xp.c | 153 ++++++++++++++++++++- drivers/pci/Kconfig | 4 - drivers/pci/host/pci-mvebu.c | 31 +++++ drivers/pci/msi.c | 66 +++++---- drivers/pci/probe.c | 1 + include/linux/irqdomain.h | 62 ++++++++- include/linux/msi.h | 18 ++- include/linux/pci.h | 1 + kernel/irq/irqdomain.c | 89 +++++++++--- 31 files changed, 422 insertions(+), 106 deletions(-)Signature · 7 lines
1.8.1.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel at lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
v6 cover MSI support for Marvell EBU PCIe driver
Quoted 11 lines · Jason Cooper
Thomas,
In order to get some testing in -next, I've *tentatively* applied this series in the following way:
+---+ mvebu/msi_common (1,2,3,10) | +---+---+ mvebu/msi_irq (4-9) | +---+---+ mvebu/msi_mvebu (11-13)
Quoted 7 lines
I had to make one change to patch #9, I protected the last two blocks with #ifdef
CONFIG_PCI_MSIto prevent a build failure at that point.mvebu/msi_common should be appropriate for Thierry to base off, however, I make no guarantees about the stability of the branch until I send a PR for it. Code-wise, it should be fine, but the commit-ids may change due to adding Tested-by's, etc.
When do you intend to send the pull-request? I need a stable branch before I can even apply Thierry's changes, and I'd prefer to get those changes applied and in linux-next well before I send my pull requests to arm-soc. At the very latest, I need enough time to apply Thierry's patches on top of your final version of that branch, get it briefly tested, and then send a pull-request to arm-soc before -rc6 is out, so if your pull request goes in just before -rc6, that's going to be a problem.
v6 cover MSI support for Marvell EBU PCIe driver
Quoted 20 lines · Stephen Warren
Quoted 11 lines · Jason Cooper
Thomas,
In order to get some testing in -next, I've *tentatively* applied this series in the following way:
+---+ mvebu/msi_common (1,2,3,10) | +---+---+ mvebu/msi_irq (4-9) | +---+---+ mvebu/msi_mvebu (11-13)Quoted 7 lines
I had to make one change to patch #9, I protected the last two blocks with #ifdef
CONFIG_PCI_MSIto prevent a build failure at that point.mvebu/msi_common should be appropriate for Thierry to base off, however, I make no guarantees about the stability of the branch until I send a PR for it. Code-wise, it should be fine, but the commit-ids may change due to adding Tested-by's, etc.
Quoted 7 lines
When do you intend to send the pull-request? I need a stable branch before I can even apply Thierry's changes, and I'd prefer to get those changes applied and in linux-next well before I send my pull requests to arm-soc. At the very latest, I need enough time to apply Thierry's patches on top of your final version of that branch, get it briefly tested, and then send a pull-request to arm-soc before -rc6 is out, so if your pull request goes in just before -rc6, that's going to be a problem.
I'll tag the head of mvebu/msi_common once it makes it through -next successfully (I saw a linux-next email go by, but I haven't gotten that far down my inbox yet)
Hopefully today or tomorrow, depending on where the -next problem is. I'll send the PR along side that. Once I tag it, you should be able to base off of it before it gets into arm-soc, since the commit-id won't change.
thx,
Jason.
v6 cover MSI support for Marvell EBU PCIe driver
In reply to Jason CooperQuoted 11 lines · Jason Cooper
Thomas,
In order to get some testing in -next, I've *tentatively* applied this series in the following way:
+---+ mvebu/msi_common (1,2,3,10) | +---+---+ mvebu/msi_irq (4-9) | +---+---+ mvebu/msi_mvebu (11-13)
Quoted 7 lines
I had to make one change to patch #9, I protected the last two blocks with #ifdef
CONFIG_PCI_MSIto prevent a build failure at that point.mvebu/msi_common should be appropriate for Thierry to base off, however, I make no guarantees about the stability of the branch until I send a PR for it. Code-wise, it should be fine, but the commit-ids may change due to adding Tested-by's, etc.
I noticed that patch 10 has my Reviewed-by, even though my comments weren't addressed. They were about stylistic issues but I'd still like to see them fixed now rather than having to fix them up later. Also I think I gave my Tested-by on those patches somewhere already and I think it's unlikely that anybody else will test them, so with the consistency style fixes applied I don't see any reason why that branch can't be stabilized right away.
Thierry
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v6 cover MSI support for Marvell EBU PCIe driver
Quoted 20 lines · Thierry Reding
Quoted 11 lines · Jason Cooper
Thomas,
In order to get some testing in -next, I've *tentatively* applied this series in the following way:
+---+ mvebu/msi_common (1,2,3,10) | +---+---+ mvebu/msi_irq (4-9) | +---+---+ mvebu/msi_mvebu (11-13)Quoted 7 lines
I had to make one change to patch #9, I protected the last two blocks with #ifdef
CONFIG_PCI_MSIto prevent a build failure at that point.mvebu/msi_common should be appropriate for Thierry to base off, however, I make no guarantees about the stability of the branch until I send a PR for it. Code-wise, it should be fine, but the commit-ids may change due to adding Tested-by's, etc.
Quoted 7 lines
I noticed that patch 10 has my Reviewed-by, even though my comments weren't addressed. They were about stylistic issues but I'd still like to see them fixed now rather than having to fix them up later. Also I think I gave my Tested-by on those patches somewhere already and I think it's unlikely that anybody else will test them, so with the consistency style fixes applied I don't see any reason why that branch can't be stabilized right away.
Ahh, thanks. I did miss your tested-by. We did get one other from Daniel Price (which sounded like a pretty cool setup, btw), so I'll add yours before I tag it.
wrt your Reviewed-by, that came with the patch and may be from a previous revision. At any rate, I saw your comments about the whitespace/alignment, and I'll fixup v7 as I pull it in.
thx,
Jason.