powerpc/tm: Add checkpointed versions of some SPRs to thread_struct

PATCH Superseded Michael Neuling 2 participants 16 messages Aug 7, 2013 – Aug 9, 2013 PowerPC

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Michael Neuling

author

2013-08-07 06:11 UTC #0 lore raw

PATCH 1/4 powerpc/tm: Add checkpointed versions of some SPRs to thread_struct

Transactional memory will restore the TAR, PPR and DSCR on transaction failure.

Add these to the thread_struct for use in the future

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]>

---
 arch/powerpc/include/asm/processor.h | 4 ++++
 arch/powerpc/kernel/asm-offsets.c    | 3 +++
 2 files changed, 7 insertions(+)

arch/powerpc/include/asm/processor.h +4 -0

index 47a35b0..e378ccc 100644
@@ -247,6 +247,10 @@ struct thread_struct {
 	unsigned long	tm_orig_msr;	/* Thread's MSR on ctx switch */
 	struct pt_regs	ckpt_regs;	/* Checkpointed registers */
 
+	unsigned long	tm_tar;
+	unsigned long	tm_ppr;
+	unsigned long	tm_dscr;
+
 	/*
 	 * Transactional FP and VSX 0-31 register set.
 	 * NOTE: the sense of these is the opposite of the integer ckpt_regs!

arch/powerpc/kernel/asm-offsets.c +3 -0

index c7e8afc..8207459 100644
@@ -138,6 +138,9 @@ int main(void)
 	DEFINE(THREAD_TM_TFHAR, offsetof(struct thread_struct, tm_tfhar));
 	DEFINE(THREAD_TM_TEXASR, offsetof(struct thread_struct, tm_texasr));
 	DEFINE(THREAD_TM_TFIAR, offsetof(struct thread_struct, tm_tfiar));
+	DEFINE(THREAD_TM_TAR, offsetof(struct thread_struct, tm_tar));
+	DEFINE(THREAD_TM_PPR, offsetof(struct thread_struct, tm_ppr));
+	DEFINE(THREAD_TM_DSCR, offsetof(struct thread_struct, tm_dscr));
 	DEFINE(PT_CKPT_REGS, offsetof(struct thread_struct, ckpt_regs));
 	DEFINE(THREAD_TRANSACT_VR0, offsetof(struct thread_struct,
 					 transact_vr[0]));

Signature · 1 line

1.8.1.2

Michael Neuling

author

2013-08-07 06:11 UTC #1 lore raw

PATCH 2/4 powerpc: Add new save_tar() register function.

Add save_tar() function to save the Target Address Register (TAR). This will be used in a future patch to save the TAR earlier than it currently is.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]>

---
 arch/powerpc/include/asm/switch_to.h |  5 +++++
 arch/powerpc/kernel/entry_64.S       | 12 ++++++++++++
 2 files changed, 17 insertions(+)

arch/powerpc/include/asm/switch_to.h +5 -0

index 49a13e0..4531068 100644
@@ -15,6 +15,11 @@ extern struct task_struct *__switch_to(struct task_struct *,
 struct thread_struct;
 extern struct task_struct *_switch(struct thread_struct *prev,
 				   struct thread_struct *next);
+#ifdef CONFIG_PPC_BOOK3S_64
+extern void _save_tar(struct thread_struct *prev);
+#else
+static inline void _save_tar(struct thread_struct *prev) {}
+#endif
 
 extern void giveup_fpu(struct task_struct *);
 extern void load_up_fpu(void);

arch/powerpc/kernel/entry_64.S +12 -0

index 4674fe6..32e18f3 100644
@@ -389,6 +389,18 @@ DSCR_DEFAULT:
 	.tc dscr_default[TC],dscr_default
 
 	.section	".text"
+#ifdef CONFIG_PPC_BOOK3S_64
+_GLOBAL(_save_tar)
+	/*
+	 * Back up the TAR across context switches.  Note that the TAR is not
+	 * available for use in the kernel.  (To provide this, the TAR should
+	 * be backed up/restored on exception entry/exit instead, and be in
+	 * pt_regs.  FIXME, this should be in pt_regs anyway (for debug).)
+	 */
+	mfspr	r0,SPRN_TAR
+	std	r0,THREAD_TAR(r3)
+	blr
+#endif
 
 /*
  * This routine switches between two different tasks.  The process

Signature · 1 line

1.8.1.2

Paul Mackerras

2013-08-07 08:07 UTC #2 lore raw

Re: [PATCH 2/4] powerpc: Add new save_tar() register function.

Quoted 36 lines · Michael Neuling

Add save_tar() function to save the Target Address Register (TAR). This will be used in a future patch to save the TAR earlier than it currently is.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]>

---
 arch/powerpc/include/asm/switch_to.h |  5 +++++
 arch/powerpc/kernel/entry_64.S       | 12 ++++++++++++
 2 files changed, 17 insertions(+)

arch/powerpc/include/asm/switch_to.h +5 -0

index 49a13e0..4531068 100644
@@ -15,6 +15,11 @@ extern struct task_struct *__switch_to(struct task_struct *,
 struct thread_struct;
 extern struct task_struct *_switch(struct thread_struct *prev,
 				   struct thread_struct *next);
+#ifdef CONFIG_PPC_BOOK3S_64
+extern void _save_tar(struct thread_struct *prev);
+#else
+static inline void _save_tar(struct thread_struct *prev) {}
+#endif
 
 extern void giveup_fpu(struct task_struct *);
 extern void load_up_fpu(void);

arch/powerpc/kernel/entry_64.S +2 -0

index 4674fe6..32e18f3 100644
@@ -389,6 +389,18 @@ DSCR_DEFAULT:
 	.tc dscr_default[TC],dscr_default
 
 	.section	".text"
+#ifdef CONFIG_PPC_BOOK3S_64
+_GLOBAL(_save_tar)

arch/powerpc/kernel/entry_64.S DSCR_DEFAULT: · line 403

Quoted 10 lines

arch/powerpc/kernel/entry_64.S +10 -0

+	/*
+	 * Back up the TAR across context switches.  Note that the TAR is not
+	 * available for use in the kernel.  (To provide this, the TAR should
+	 * be backed up/restored on exception entry/exit instead, and be in
+	 * pt_regs.  FIXME, this should be in pt_regs anyway (for debug).)
+	 */
+	mfspr	r0,SPRN_TAR
+	std	r0,THREAD_TAR(r3)
+	blr
+#endif

Why not do this in C, as in prev->tar = mfspr(SPRN_TAR); ?

Paul.

Michael Neuling

author

2013-08-07 10:55 UTC #3 lore raw

Re: [PATCH 2/4] powerpc: Add new save_tar() register function.

Quoted 6 lines

arch/powerpc/kernel/entry_64.S +6 -0

+#ifdef CONFIG_PPC_BOOK3S_64
+_GLOBAL(_save_tar)
+	/*
+	 * Back up the TAR across context switches.  Note that the TAR is not
+	 * available for use in the kernel.  (To provide this, the TAR should
+	 * be backed up/restored on exception entry/exit instead, and be in

Quoted 8 lines

arch/powerpc/kernel/entry_64.S DSCR_DEFAULT: · line 403
Quoted 6 lines
arch/powerpc/kernel/entry_64.S +6 -0
+	 * pt_regs.  FIXME, this should be in pt_regs anyway (for debug).)
+	 */
+	mfspr	r0,SPRN_TAR
+	std	r0,THREAD_TAR(r3)
+	blr
+#endif
Why not do this in C, as in prev->tar = mfspr(SPRN_TAR); ?

Good point!

I'd just copied the original code which was inline asm in _switch().

Thanks,
Mikey

Michael Neuling

author

2013-08-08 02:33 UTC #4 lore raw

PATCH v2 1/4 powerpc/tm: Add checkpointed versions of some SPRs to thread_struct

Transactional memory will restore the TAR, PPR and DSCR on transaction failure.

Add these to the thread_struct for use in the future

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]>

---
 arch/powerpc/include/asm/processor.h | 4 ++++
 arch/powerpc/kernel/asm-offsets.c    | 3 +++
 2 files changed, 7 insertions(+)

arch/powerpc/include/asm/processor.h +4 -0

index 47a35b0..e378ccc 100644
@@ -247,6 +247,10 @@ struct thread_struct {
 	unsigned long	tm_orig_msr;	/* Thread's MSR on ctx switch */
 	struct pt_regs	ckpt_regs;	/* Checkpointed registers */
 
+	unsigned long	tm_tar;
+	unsigned long	tm_ppr;
+	unsigned long	tm_dscr;
+
 	/*
 	 * Transactional FP and VSX 0-31 register set.
 	 * NOTE: the sense of these is the opposite of the integer ckpt_regs!

arch/powerpc/kernel/asm-offsets.c +3 -0

index c7e8afc..8207459 100644
@@ -138,6 +138,9 @@ int main(void)
 	DEFINE(THREAD_TM_TFHAR, offsetof(struct thread_struct, tm_tfhar));
 	DEFINE(THREAD_TM_TEXASR, offsetof(struct thread_struct, tm_texasr));
 	DEFINE(THREAD_TM_TFIAR, offsetof(struct thread_struct, tm_tfiar));
+	DEFINE(THREAD_TM_TAR, offsetof(struct thread_struct, tm_tar));
+	DEFINE(THREAD_TM_PPR, offsetof(struct thread_struct, tm_ppr));
+	DEFINE(THREAD_TM_DSCR, offsetof(struct thread_struct, tm_dscr));
 	DEFINE(PT_CKPT_REGS, offsetof(struct thread_struct, ckpt_regs));
 	DEFINE(THREAD_TRANSACT_VR0, offsetof(struct thread_struct,
 					 transact_vr[0]));

Signature · 1 line

1.8.1.2

Michael Neuling

author

2013-08-08 02:33 UTC #5 lore raw

PATCH v2 2/4 powerpc: Add new save_tar() register function.

Add save_tar() function to save the Target Address Register (TAR). This will be used in a future patch to save the TAR earlier than it currently is.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]>

---
 arch/powerpc/include/asm/switch_to.h | 9 +++++++++
 arch/powerpc/kernel/entry_64.S       | 1 -
 2 files changed, 9 insertions(+), 1 deletion(-)

arch/powerpc/include/asm/switch_to.h +9 -0

index 49a13e0..294c2ce 100644
@@ -15,6 +15,15 @@ extern struct task_struct *__switch_to(struct task_struct *,
 struct thread_struct;
 extern struct task_struct *_switch(struct thread_struct *prev,
 				   struct thread_struct *next);
+#ifdef CONFIG_PPC_BOOK3S_64
+static inline void save_tar(struct thread_struct *prev)
+{
+	if (cpu_has_feature(CPU_FTR_ARCH_207S))
+		prev->tar = mfspr(SPRN_TAR);
+}
+#else
+static inline void save_tar(struct thread_struct *prev) {}
+#endif
 
 extern void giveup_fpu(struct task_struct *);
 extern void load_up_fpu(void);

arch/powerpc/kernel/entry_64.S +0 -1

index 4674fe6..cfb6de4 100644
@@ -389,7 +389,6 @@ DSCR_DEFAULT:
 	.tc dscr_default[TC],dscr_default
 
 	.section	".text"
-
 /*
  * This routine switches between two different tasks.  The process
  * state of one is saved on its kernel stack.  Then the state

Signature · 1 line

1.8.1.2

Michael Neuling

author

2013-08-09 03:43 UTC #6 lore raw

PATCH v3 2/4 powerpc: Add new save_tar() register function.

powerpc: Add new save_tar() register function.

Add save_tar() function to save the Target Address Register (TAR). This will be used in a future patch to save the TAR earlier than it currently is.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]>

---
v3: remove whitespace screw age noticed by sfr

arch/powerpc/include/asm/switch_to.h +9 -0

index 49a13e0..294c2ce 100644
@@ -15,6 +15,15 @@ extern struct task_struct *__switch_to(struct task_struct *,
 struct thread_struct;
 extern struct task_struct *_switch(struct thread_struct *prev,
 				   struct thread_struct *next);
+#ifdef CONFIG_PPC_BOOK3S_64
+static inline void save_tar(struct thread_struct *prev)
+{
+	if (cpu_has_feature(CPU_FTR_ARCH_207S))
+		prev->tar = mfspr(SPRN_TAR);
+}
+#else
+static inline void save_tar(struct thread_struct *prev) {}
+#endif
 
 extern void giveup_fpu(struct task_struct *);
 extern void load_up_fpu(void);

Michael Neuling

author

2013-08-08 02:33 UTC #7 lore raw

PATCH v2 3/4 powerpc: Save the TAR register earlier

In reply to Michael Neuling

This moves us to use the save_tar() function to save the Target Address Register (TAR) a lot earlier in __switch_to.

We need to save the TAR earlier as we may overwrite it in the transactional memory reclaim/recheckpoint path.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]>

---
 arch/powerpc/kernel/entry_64.S | 9 ---------
 arch/powerpc/kernel/process.c  | 5 +++++
 2 files changed, 5 insertions(+), 9 deletions(-)

arch/powerpc/kernel/entry_64.S +0 -9

index cfb6de4..08f2e2e 100644
@@ -448,15 +448,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
 
 #ifdef CONFIG_PPC_BOOK3S_64
 BEGIN_FTR_SECTION
-	/*
-	 * Back up the TAR across context switches.  Note that the TAR is not
-	 * available for use in the kernel.  (To provide this, the TAR should
-	 * be backed up/restored on exception entry/exit instead, and be in
-	 * pt_regs.  FIXME, this should be in pt_regs anyway (for debug).)
-	 */
-	mfspr	r0,SPRN_TAR
-	std	r0,THREAD_TAR(r3)
-
 	/* Event based branch registers */
 	mfspr	r0, SPRN_BESCR
 	std	r0, THREAD_BESCR(r3)

arch/powerpc/kernel/process.c +5 -0

index c517dbe..4ef77df 100644
@@ -600,6 +600,11 @@ struct task_struct *__switch_to(struct task_struct *prev,
 	struct ppc64_tlb_batch *batch;
 #endif
 
+	/* Save the tar before we do treclaim/trecheckpoint as these
+	 * will change the TAR
+	 */
+	save_tar(&prev->thread);
+
 	__switch_to_tm(prev);
 
 #ifdef CONFIG_SMP

Signature · 1 line

1.8.1.2

Michael Neuling

author

2013-08-08 02:33 UTC #8 lore raw

PATCH v2 4/4 powerpc/tm: Save and restore checkpointed TAR, PPR and DSCR

In reply to Michael Neuling

Currently we don't save and restore the checkpointed TAR, PPR and DSCR.

This adds the required save and restore to the treclaim and trechkpt code.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]>

---
 arch/powerpc/kernel/tm.S | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

arch/powerpc/kernel/tm.S +20 -0

index 51be8fb..0554d1f 100644
@@ -233,6 +233,16 @@ dont_backup_fp:
 	std	r5, _CCR(r7)
 	std	r6, _XER(r7)
 
+
+	/* ******************** TAR, PPR, DSCR ********** */
+	mfspr	r3, SPRN_TAR
+	mfspr	r4, SPRN_PPR
+	mfspr	r5, SPRN_DSCR
+
+	std	r3, THREAD_TM_TAR(r12)
+	std	r4, THREAD_TM_PPR(r12)
+	std	r5, THREAD_TM_DSCR(r12)
+
 	/* MSR and flags:  We don't change CRs, and we don't need to alter
 	 * MSR.
 	 */

@@ -347,6 +357,16 @@ dont_restore_fp:
 	mtmsr	r6				/* FP/Vec off again! */
 
 restore_gprs:
+
+	/* ******************** TAR, PPR, DSCR ********** */
+	ld	r4, THREAD_TM_TAR(r3)
+	ld	r5, THREAD_TM_PPR(r3)
+	ld	r6, THREAD_TM_DSCR(r3)
+
+	mtspr	SPRN_TAR,	r4
+	mtspr	SPRN_PPR,	r5
+	mtspr	SPRN_DSCR,	r6
+
 	/* ******************** CR,LR,CCR,MSR ********** */
 	ld	r3, _CTR(r7)
 	ld	r4, _LINK(r7)

Signature · 1 line

1.8.1.2

Michael Neuling

author

2013-08-09 07:29 UTC #9 lore raw

PATCH 1/5 powerpc: Fix hypervisor facility unavaliable vector number

In reply to Michael Neuling

Currently if we take hypervisor facility unavaliable (from 0xf80/0x4f80) we mark it as an OS facility unavaliable (0xf60) as the two share the same code path.

The becomes a problem in facility_unavailable_exception() as we aren't able to see the hypervisor facility unavailable exceptions.

Below fixes this by duplication the required macros.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]> [v3.10]

---
 arch/powerpc/kernel/exceptions-64s.S | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

arch/powerpc/kernel/exceptions-64s.S +3 -2

index 4e00d22..902ca3c 100644
@@ -848,7 +848,7 @@ hv_facility_unavailable_relon_trampoline:
 	. = 0x4f80
 	SET_SCRATCH0(r13)
 	EXCEPTION_PROLOG_0(PACA_EXGEN)
-	b	facility_unavailable_relon_hv
+	b	hv_facility_unavailable_relon_hv
 
 	STD_RELON_EXCEPTION_PSERIES(0x5300, 0x1300, instruction_breakpoint)
 #ifdef CONFIG_PPC_DENORMALISATION

@@ -1175,6 +1175,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 	b	.ret_from_except
 
 	STD_EXCEPTION_COMMON(0xf60, facility_unavailable, .facility_unavailable_exception)
+	STD_EXCEPTION_COMMON(0xf80, hv_facility_unavailable, .facility_unavailable_exception)
 
 	.align	7
 	.globl	__end_handlers

@@ -1188,7 +1189,7 @@ __end_handlers:
 	STD_RELON_EXCEPTION_PSERIES_OOL(0xf20, altivec_unavailable)
 	STD_RELON_EXCEPTION_PSERIES_OOL(0xf40, vsx_unavailable)
 	STD_RELON_EXCEPTION_PSERIES_OOL(0xf60, facility_unavailable)
-	STD_RELON_EXCEPTION_HV_OOL(0xf80, facility_unavailable)
+	STD_RELON_EXCEPTION_HV_OOL(0xf80, hv_facility_unavailable)
 
 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
 /*

Signature · 1 line

1.8.1.2

Michael Neuling

author

2013-08-09 07:29 UTC #10 lore raw

PATCH 2/5 powerpc: Rework setting up H/FSCR bit definitions

This reworks the Facility Status and Control Regsiter (FSCR) config bit definitions so that we can access the bit numbers. This is needed for a subsequent patch to fix the userspace DSCR handling.

HFSCR and FSCR bit definitions are the same, so reuse them.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]> [v3.10]

---
 arch/powerpc/include/asm/reg.h | 31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)

arch/powerpc/include/asm/reg.h +20 ~~-11~~

index a6840e4..99222e2 100644
@@ -254,19 +254,28 @@
 #define SPRN_HRMOR	0x139	/* Real mode offset register */
 #define SPRN_HSRR0	0x13A	/* Hypervisor Save/Restore 0 */
 #define SPRN_HSRR1	0x13B	/* Hypervisor Save/Restore 1 */
+/* HFSCR and FSCR bit numbers are the same */
+#define FSCR_TAR_LG	8	/* Enable Target Address Register */
+#define FSCR_EBB_LG	7	/* Enable Event Based Branching */
+#define FSCR_TM_LG	5	/* Enable Transactional Memory */
+#define FSCR_PM_LG	4	/* Enable prob/priv access to PMU SPRs */
+#define FSCR_BHRB_LG	3	/* Enable Branch History Rolling Buffer*/
+#define FSCR_DSCR_LG	2	/* Enable Data Stream Control Register */
+#define FSCR_VECVSX_LG	1	/* Enable VMX/VSX  */
+#define FSCR_FP_LG	0	/* Enable Floating Point */
 #define SPRN_FSCR	0x099	/* Facility Status & Control Register */
-#define   FSCR_TAR	(1 << (63-55)) /* Enable Target Address Register */
-#define   FSCR_EBB	(1 << (63-56)) /* Enable Event Based Branching */
-#define   FSCR_DSCR	(1 << (63-61)) /* Enable Data Stream Control Register */
+#define   FSCR_TAR	__MASK(FSCR_TAR_LG)
+#define   FSCR_EBB	__MASK(FSCR_EBB_LG)
+#define   FSCR_DSCR	__MASK(FSCR_DSCR_LG)
 #define SPRN_HFSCR	0xbe	/* HV=1 Facility Status & Control Register */
-#define   HFSCR_TAR	(1 << (63-55)) /* Enable Target Address Register */
-#define   HFSCR_EBB	(1 << (63-56)) /* Enable Event Based Branching */
-#define   HFSCR_TM	(1 << (63-58)) /* Enable Transactional Memory */
-#define   HFSCR_PM	(1 << (63-60)) /* Enable prob/priv access to PMU SPRs */
-#define   HFSCR_BHRB	(1 << (63-59)) /* Enable Branch History Rolling Buffer*/
-#define   HFSCR_DSCR	(1 << (63-61)) /* Enable Data Stream Control Register */
-#define   HFSCR_VECVSX	(1 << (63-62)) /* Enable VMX/VSX  */
-#define   HFSCR_FP	(1 << (63-63)) /* Enable Floating Point */
+#define   HFSCR_TAR	__MASK(FSCR_TAR_LG)
+#define   HFSCR_EBB	__MASK(FSCR_EBB_LG)
+#define   HFSCR_TM	__MASK(FSCR_TM_LG)
+#define   HFSCR_PM	__MASK(FSCR_PM_LG)
+#define   HFSCR_BHRB	__MASK(FSCR_BHRB_LG)
+#define   HFSCR_DSCR	__MASK(FSCR_DSCR_LG)
+#define   HFSCR_VECVSX	__MASK(FSCR_VECVSX_LG)
+#define   HFSCR_FP	__MASK(FSCR_FP_LG)
 #define SPRN_TAR	0x32f	/* Target Address Register */
 #define SPRN_LPCR	0x13E	/* LPAR Control Register */
 #define   LPCR_VPM0	(1ul << (63-0))

Signature · 1 line

1.8.1.2

Michael Neuling

author

2013-08-09 07:29 UTC #11 lore raw

PATCH 3/5 powerpc: Fix context switch DSCR on POWER8

In reply to Michael Neuling

POWER8 allows the DSCR to be accessed directly from userspace via a new SPR number 0x3 (Rather than 0x11. DSCR SPR number 0x11 is still used on POWER8 but like POWER7, is only accessible in HV and OS modes). Currently, we allow this by setting H/FSCR DSCR bit on boot.

Unfortunately this doesn't work, as the kernel needs to see the DSCR change so that it knows to no longer restore the system wide version of DSCR on context switch (ie. to set thread.dscr_inherit).

This clears the H/FSCR DSCR bit initially. If a process then accesses the DSCR (via SPR 0x3), it'll trap into the kernel where we set thread.dscr_inherit in facility_unavailable_exception().

We also change _switch() so that we set or clear the H/FSCR DSCR bit based on the thread.dscr_inherit.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]> [v3.10]

---
 arch/powerpc/kernel/entry_64.S | 27 +++++++++++++++++++-
 arch/powerpc/kernel/traps.c    | 58 +++++++++++++++++++++++++-----------------
 2 files changed, 60 insertions(+), 25 deletions(-)

arch/powerpc/kernel/entry_64.S +26 -1

index ab15b8d..4674fe6 100644
@@ -584,9 +584,34 @@ BEGIN_FTR_SECTION
 	ld	r7,DSCR_DEFAULT@toc(2)
 	ld	r0,THREAD_DSCR(r4)
 	cmpwi	r6,0
+	li	r8, FSCR_DSCR
 	bne	1f
 	ld	r0,0(r7)
-1:	cmpd	r0,r25
+	b	3f
+1:
+  BEGIN_FTR_SECTION_NESTED(70)
+	mfspr	r6, SPRN_FSCR
+	or	r6, r6, r8
+	mtspr	SPRN_FSCR, r6
+    BEGIN_FTR_SECTION_NESTED(69)
+	mfspr	r6, SPRN_HFSCR
+	or	r6, r6, r8
+	mtspr	SPRN_HFSCR, r6
+    END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
+	b	4f
+  END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
+3:
+  BEGIN_FTR_SECTION_NESTED(70)
+	mfspr	r6, SPRN_FSCR
+	andc	r6, r6, r8
+	mtspr	SPRN_FSCR, r6
+    BEGIN_FTR_SECTION_NESTED(69)
+	mfspr	r6, SPRN_HFSCR
+	andc	r6, r6, r8
+	mtspr	SPRN_HFSCR, r6
+    END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
+  END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
+4:	cmpd	r0,r25
 	beq	2f
 	mtspr	SPRN_DSCR,r0
 2:

arch/powerpc/kernel/traps.c +34 ~~-24~~

92 lines not on this page · raw message

Signature · 1 line

1.8.1.2

Michael Neuling

author

2013-08-09 07:29 UTC #12 lore raw

PATCH 4/5 powerpc: Save the TAR register earlier

In reply to Michael Neuling

This moves us to save the Target Address Register (TAR) a earlier in __switch_to. It introduces a new function save_tar() to do this.

We need to save the TAR earlier as we will overwrite it in the transactional memory reclaim/recheckpoint path. We are going to do this in a subsequent patch which will fix saving the TAR register when it's modified inside a transaction.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]> [v3.10]

---
 arch/powerpc/include/asm/switch_to.h |  9 +++++++++
 arch/powerpc/kernel/entry_64.S       |  9 ---------
 arch/powerpc/kernel/process.c        | 10 ++++++++++
 3 files changed, 19 insertions(+), 9 deletions(-)

arch/powerpc/include/asm/switch_to.h +9 -0

index 49a13e0..294c2ce 100644
@@ -15,6 +15,15 @@ extern struct task_struct *__switch_to(struct task_struct *,
 struct thread_struct;
 extern struct task_struct *_switch(struct thread_struct *prev,
 				   struct thread_struct *next);
+#ifdef CONFIG_PPC_BOOK3S_64
+static inline void save_tar(struct thread_struct *prev)
+{
+	if (cpu_has_feature(CPU_FTR_ARCH_207S))
+		prev->tar = mfspr(SPRN_TAR);
+}
+#else
+static inline void save_tar(struct thread_struct *prev) {}
+#endif
 
 extern void giveup_fpu(struct task_struct *);
 extern void load_up_fpu(void);

arch/powerpc/kernel/entry_64.S +0 -9

index 4674fe6..2bd0b88 100644
@@ -449,15 +449,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
 
 #ifdef CONFIG_PPC_BOOK3S_64
 BEGIN_FTR_SECTION
-	/*
-	 * Back up the TAR across context switches.  Note that the TAR is not
-	 * available for use in the kernel.  (To provide this, the TAR should
-	 * be backed up/restored on exception entry/exit instead, and be in
-	 * pt_regs.  FIXME, this should be in pt_regs anyway (for debug).)
-	 */
-	mfspr	r0,SPRN_TAR
-	std	r0,THREAD_TAR(r3)
-
 	/* Event based branch registers */
 	mfspr	r0, SPRN_BESCR
 	std	r0, THREAD_BESCR(r3)

arch/powerpc/kernel/process.c +10 -0

index c517dbe..8083be2 100644
@@ -600,6 +600,16 @@ struct task_struct *__switch_to(struct task_struct *prev,
 	struct ppc64_tlb_batch *batch;
 #endif
 
+	/* Back up the TAR across context switches.
+	 * Note that the TAR is not available for use in the kernel.  (To
+	 * provide this, the TAR should be backed up/restored on exception
+	 * entry/exit instead, and be in pt_regs.  FIXME, this should be in
+	 * pt_regs anyway (for debug).)
+	 * Save the TAR here before we do treclaim/trecheckpoint as these
+	 * will change the TAR.
+	 */
+	save_tar(&prev->thread);
+
 	__switch_to_tm(prev);
 
 #ifdef CONFIG_SMP

Signature · 1 line

1.8.1.2

Michael Neuling

author

2013-08-09 07:29 UTC #13 lore raw

PATCH 5/5 powerpc/tm: Fix context switching TAR, PPR and DSCR SPRs

In reply to Michael Neuling

If a transaction is rolled back, the Target Address Register (TAR), Processor Priority Register (PPR) and Data Stream Control Register (DSCR) should be restored to the checkpointed values before the transaction began. Any changes to these SPRs inside the transaction should not be visible in the abort handler.

Currently Linux doesn't save or restore the checkpointed TAR, PPR or DSCR. If we preempt a processes inside a transaction which has modified any of these, on process restore, that same transaction may be aborted we but we won't see the checkpointed versions of these SPRs.

This adds checkpointed versions of these SPRs to the thread_struct and adds the save/restore of these three SPRs to the treclaim/trechkpt code.

Without this if any of these SPRs are modified during a transaction, users may incorrectly see a speculated SPR value even if the transaction is aborted.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]> [v3.10]

---
 arch/powerpc/include/asm/processor.h |  4 ++++
 arch/powerpc/kernel/asm-offsets.c    |  3 +++
 arch/powerpc/kernel/tm.S             | 20 ++++++++++++++++++++
 3 files changed, 27 insertions(+)

arch/powerpc/include/asm/processor.h +4 -0

index 47a35b0..e378ccc 100644
@@ -247,6 +247,10 @@ struct thread_struct {
 	unsigned long	tm_orig_msr;	/* Thread's MSR on ctx switch */
 	struct pt_regs	ckpt_regs;	/* Checkpointed registers */
 
+	unsigned long	tm_tar;
+	unsigned long	tm_ppr;
+	unsigned long	tm_dscr;
+
 	/*
 	 * Transactional FP and VSX 0-31 register set.
 	 * NOTE: the sense of these is the opposite of the integer ckpt_regs!

arch/powerpc/kernel/asm-offsets.c +3 -0

index c7e8afc..8207459 100644
@@ -138,6 +138,9 @@ int main(void)
 	DEFINE(THREAD_TM_TFHAR, offsetof(struct thread_struct, tm_tfhar));
 	DEFINE(THREAD_TM_TEXASR, offsetof(struct thread_struct, tm_texasr));
 	DEFINE(THREAD_TM_TFIAR, offsetof(struct thread_struct, tm_tfiar));
+	DEFINE(THREAD_TM_TAR, offsetof(struct thread_struct, tm_tar));
+	DEFINE(THREAD_TM_PPR, offsetof(struct thread_struct, tm_ppr));
+	DEFINE(THREAD_TM_DSCR, offsetof(struct thread_struct, tm_dscr));
 	DEFINE(PT_CKPT_REGS, offsetof(struct thread_struct, ckpt_regs));
 	DEFINE(THREAD_TRANSACT_VR0, offsetof(struct thread_struct,
 					 transact_vr[0]));

arch/powerpc/kernel/tm.S +20 -0

index 51be8fb..0554d1f 100644
@@ -233,6 +233,16 @@ dont_backup_fp:
 	std	r5, _CCR(r7)
 	std	r6, _XER(r7)
 
+
+	/* ******************** TAR, PPR, DSCR ********** */
+	mfspr	r3, SPRN_TAR
+	mfspr	r4, SPRN_PPR
+	mfspr	r5, SPRN_DSCR
+
+	std	r3, THREAD_TM_TAR(r12)
+	std	r4, THREAD_TM_PPR(r12)
+	std	r5, THREAD_TM_DSCR(r12)
+
 	/* MSR and flags:  We don't change CRs, and we don't need to alter
 	 * MSR.
 	 */

@@ -347,6 +357,16 @@ dont_restore_fp:
 	mtmsr	r6				/* FP/Vec off again! */
 
 restore_gprs:
+
+	/* ******************** TAR, PPR, DSCR ********** */
+	ld	r4, THREAD_TM_TAR(r3)
+	ld	r5, THREAD_TM_PPR(r3)
+	ld	r6, THREAD_TM_DSCR(r3)
+
+	mtspr	SPRN_TAR,	r4
+	mtspr	SPRN_PPR,	r5
+	mtspr	SPRN_DSCR,	r6
+
 	/* ******************** CR,LR,CCR,MSR ********** */
 	ld	r3, _CTR(r7)
 	ld	r4, _LINK(r7)

Signature · 1 line

1.8.1.2

Michael Neuling

author

2013-08-07 06:11 UTC #14 lore raw

PATCH 3/4 powerpc: Save the TAR register earlier

In reply to Michael Neuling

This moves us to use the save_tar() function to save the Target Address Register (TAR) a lot earlier in __switch_to.

We need to save the TAR earlier as we may overwrite it in the transactional memory reclaim/recheckpoint path.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]>

---
 arch/powerpc/kernel/entry_64.S | 9 ---------
 arch/powerpc/kernel/process.c  | 6 ++++++
 2 files changed, 6 insertions(+), 9 deletions(-)

arch/powerpc/kernel/entry_64.S +0 -9

index 32e18f3..616328e 100644
@@ -461,15 +461,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
 
 #ifdef CONFIG_PPC_BOOK3S_64
 BEGIN_FTR_SECTION
-	/*
-	 * Back up the TAR across context switches.  Note that the TAR is not
-	 * available for use in the kernel.  (To provide this, the TAR should
-	 * be backed up/restored on exception entry/exit instead, and be in
-	 * pt_regs.  FIXME, this should be in pt_regs anyway (for debug).)
-	 */
-	mfspr	r0,SPRN_TAR
-	std	r0,THREAD_TAR(r3)
-
 	/* Event based branch registers */
 	mfspr	r0, SPRN_BESCR
 	std	r0, THREAD_BESCR(r3)

arch/powerpc/kernel/process.c +6 -0

index c517dbe..6b4c649 100644
@@ -600,6 +600,12 @@ struct task_struct *__switch_to(struct task_struct *prev,
 	struct ppc64_tlb_batch *batch;
 #endif
 
+	/* Save the tar before we do treclaim/trecheckpoint as these
+	 * will change the TAR
+	 */
+	if (cpu_has_feature(CPU_FTR_ARCH_207S))
+		_save_tar(&prev->thread);
+
 	__switch_to_tm(prev);
 
 #ifdef CONFIG_SMP

Signature · 1 line

1.8.1.2

Michael Neuling

author

2013-08-07 06:11 UTC #15 lore raw

PATCH 4/4 powerpc/tm: Save and restore checkpointed TAR, PPR and DSCR

In reply to Michael Neuling

Currently we don't save and restore the checkpointed TAR, PPR and DSCR.

This adds the required save and restore to the treclaim and trechkpt code.

Signed-off-by Michael Neuling <[email protected]>

Cc <[email protected]>

---
 arch/powerpc/kernel/tm.S | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

arch/powerpc/kernel/tm.S +20 -0

index 51be8fb..0554d1f 100644
@@ -233,6 +233,16 @@ dont_backup_fp:
 	std	r5, _CCR(r7)
 	std	r6, _XER(r7)
 
+
+	/* ******************** TAR, PPR, DSCR ********** */
+	mfspr	r3, SPRN_TAR
+	mfspr	r4, SPRN_PPR
+	mfspr	r5, SPRN_DSCR
+
+	std	r3, THREAD_TM_TAR(r12)
+	std	r4, THREAD_TM_PPR(r12)
+	std	r5, THREAD_TM_DSCR(r12)
+
 	/* MSR and flags:  We don't change CRs, and we don't need to alter
 	 * MSR.
 	 */

@@ -347,6 +357,16 @@ dont_restore_fp:
 	mtmsr	r6				/* FP/Vec off again! */
 
 restore_gprs:
+
+	/* ******************** TAR, PPR, DSCR ********** */
+	ld	r4, THREAD_TM_TAR(r3)
+	ld	r5, THREAD_TM_PPR(r3)
+	ld	r6, THREAD_TM_DSCR(r3)
+
+	mtspr	SPRN_TAR,	r4
+	mtspr	SPRN_PPR,	r5
+	mtspr	SPRN_DSCR,	r6
+
 	/* ******************** CR,LR,CCR,MSR ********** */
 	ld	r3, _CTR(r7)
 	ld	r4, _LINK(r7)

Signature · 1 line

1.8.1.2