MSI support for Marvell EBU PCIe driver
Subsystems (12)
v8 cover MSI support for Marvell EBU PCIe driver
Hello,
This set of patches introduces Message Signaled Interrupt support in the Marvell EBU PCIe driver. It has been successfully tested on the Armada XP GP platform with an Intel e1000e PCIe network card that supports MSI.
The main changes compared to the previous version is that this version goes back to:
* An allocation of MSI interrupts done by the IRQ controller driver itself.
* A registry of msi_chip <-> of_node in drivers/of/.
Both of those solutions were previously rejected by Grant Likely, who instead suggested to more tightly integrate msi_chip and irq_domains. However, Grant is no longer the irq_domain or drivers/of maintainers, and the solutions he had proposed are now rejected by Benjamin Herrenschmidt, the current irq_domain maintainer.
This patch set therefore makes no modification to the irq_domain logic, and should hopefully match better the expectations of Benjamin.
This patch set is intended for merging in 3.12, so the respective maintainers of the different areas are invited to review/ack the patches, see below for the details.
The patches do the following:
* Patch 1 reworks how the architecture-specific MSI functions can be overriden by architecture-specific code, by using weak functions. It was suggested by Bjorn Helgaas.
This patch has been acked by Bjorn Helgaas, the PCI maintainter.
* Patch 2 removes the ARCH_SUPPORTS_MSI hidden kconfig boolean which is no longer needed now that we have weak functions for all MSI architecture-specific hooks.
This patch has been acked by Bjorn Helgaas, the PCI maintainer.
* Patch 3 adds a minimal msi_chip infrastructure, that allows a pci_bus to be connected to a msi_chip, and that provides default implementations of the architecture-specific MSI functions to use msi_chip.
This patch has been acked by Bjorn Helgaas, the PCI maintainter.
* Patch 4 adds a simple registry of msi_chip <-> of_node in drivers/of.
This patch has been Acked by Rob Herring.
* Patch 5 makes some not very interesting preparation in the Armada 370/XP IRQ controller driver.
This patch needs the Ack from Thomas Gleixner, as the drivers/irqchip maintainer.
* Patch 6 implements the MSI support in the Armada 370/XP IRQ controller driver. It registers an msi_chip using the msi_chip_add() function added in PATCH 3.
This patch needs the Ack from Thomas Gleixner, as the drivers/irqchip maintainer.
* Patch 7 extends the ARM PCI core to expose ->add_bus() and ->remove_bus() hooks to PCI drivers. This was suggested by Bjorn Helgaas to allow the PCI driver to connected the PCI busses with the corresponding MSI chip.
This patch has been Acked by Russell King, the ARM maintainer.
* Patch 8 adjust the Armada 370/XP Device Tree to indicate that the MPIC is not only an interrupt-controller, but also an msi-controller.
This patch needs the Ack from Jason Cooper, Gregory Clement and/or Andrew Lunn, the Marvell maintainers.
* Patch 9 adds MSI support in the Marvell PCIe host controller driver. The work to do here is minimal: get a reference to the msi-parent controller thanks to msi_chip_find_by_of_node(), and link it to the pci_bus structure before the bus gets enumerated.
This patch has been acked by Bjorn Helgaas, the PCI maintainer.
* Patch 10 adjusts the Armada 370/XP Device Tree to add the msi-parent properties in the PCIe controller nodes.
This patch needs the Ack from Jason Cooper, Gregory Clement and/or Andrew Lunn, the Marvell Maintainers.
This version 8 follows:
* PATCH version 7 sent on August, 7th 2013
* PATCH version 6 sent on August, 1st 2013
* PATCH version 5 sent on July, 15th 2013
* PATCH version 4 sent on July, 1st 2013
* PATCH version 3 sent on June, 19th 2013
* PATCH version 2 sent on June, 6th 2013
* RFC version 1 sent on March, 26th 2013
Changes since v7:
* Instead of using an irq_domain based allocation of MSI interrupts, revert back to a bitmap-based solution directly implemented inside the IRQ controller driver. This is identical to what was done in Version 2 of this patch set.
* Instead of tightly coupling msi_chip and irq_domain, revert back to the simple msi_chip <-> of_node registry in drivers/of, which was part of Version 3, Version 4 and Version 5 of this patch set.
* Remove Tested-by from Daniel Price on the two modified patches.
* Fix the indentation problem noticed by Thierry Reding on the 'ARM:
pci: add ->add_bus() and ->remove_bus() hooks to hw_pci' patch.
Changes since v6:
* Fixed x86 build failure related to default_restore_msi_irqs(), noticed by Stephen Rothwell on linux-next.
* Added Acked-by from Bjorn Helgaas on 'PCI: remove ARCH_SUPPORTS_MSI kconfig option'.
* Fixed a compile-time issue in drivers/irqchip/irq-armada-370-xp.c in the !CONFIG_PCI_MSI case.
* Fixed one of the stylistic issue raised by Thierry Reding on 'ARM:
pci: add ->add_bus() and ->remove_bus() hooks to hw_pci' (i.e do not align '=' when assigning elements of the pci_sys_data structure). I however didn't fix the tab vs. spaces indentation issue noticed by Thierry, since I couldn't see it (to me the indentation was identical in both locations).
* Added Tested-by from Daniel Price on all patches.
Changes since v5:
* Rebased on top of 3.11-rc3.
* Implemented the suggestions of Grant Likely on "irqdomain: add irq_alloc_mapping() function" and added his Acked-by.
* Added Bjorn Helgaas Acked-by on "PCI: use weak functions for MSI arch-specific functions".
* Added Bjorn Helgaas Acked-by on "PCI: Introduce new MSI chip infrastructure".
* Remove the drivers/of global registry of irq_chip, and as suggested by Grant Likely, create an association between an irq_domain and a msi_chip. This required refactoring the __irq_domain_add() function, adding a 'msi_chip' pointer to 'irq_domain', adding an irq_domain_add_msi() function and a irq_find_msi_host() function.
* Added Russell King Acked-by on "ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pci"
Changes since v4:
* Rebased on top of 3.11-rc1.
* Slightly rework the implementation of arch_setup_msi_irq(), arch_teardown_msi_irq and arch_msi_check_device() according to the suggestions of Bjorn Helgaas (PATCH 4)
* Make a few improvements to the msi_chip registry, according to the suggestion of Bjorn Helgaas and Rob Herring: coding style fixes, usage of mutex while traversing the list of msi_chip, usage of of_pci_msi_* prefix instead of just of_msi_*.
Changes since v3:
* Keep only a default_teardown_msi_irqs() function needed for the Xen PCI x86 code, and remove all other default_*() function and put the default behavior directly in the weak functions. Suggested by Thierry Redding and Bjorn Helgaas.
* Misc small improvements the MSI chip registry code: compiled only under CONFIG_PCI_MSI, functions exported to modules, addition of an of_msi_chip_remove() function, renaming of of_msi_chip_find_by_node() to of_find_msi_chip_by_node(), move the test of the "msi-controller" property to the of_msi_chip_add() function, renamed the list_head field from link to list, added dummy functions in the header files when !CONFIG_PCI_MSI && !CONFIG_OF. All suggested by Thierry Redding.
* Add a patch that entirely removes the ARCH_SUPPORTS_MSI, as we now have weak functions, so even if an arch doesn't actually use/support MSI, the code will build properly. Suggested by Thierry Redding.
* Added Device Tree binding documentation updates for the IRQ controller and the PCIe controller.
Changes since v2:
* Add an IRQ domain function that allows to allocate dynamically a free hwirq number from an IRQ domain, and create a virq mapping to it. It was suggested by Grant Likely in order to remove the hwirq allocation code from the IRQ driver itself. (PATCH 1)
* Separate the use of weak functions from the introduction of the msi_chip infrastructure, and use weak functions for all architecture-specific MSI hooks. Suggested by Bjorn Helgaas (PATCH 2).
* Move the msi_chip registry to drivers/of. Suggested by Bjorn Helgaas (PATCH 4).
* Use pcibios_add_bus() and pcibios_remove_bus() to connect the PCI busses to their msi_chip, as suggested by Bjorn Helgaas. Requires some ARM PCI core changes (PATCH 7), and then changes to the PCI driver itself (PATCH 9).
This set of patches applies on top of 3.11-rc3, and is available as a Git branch at
https://github.com/MISL-EBU-System-SW/mainline-public/tree/marvell-pcie-msi-v8.
Thanks,
Thomas
Thierry Reding (1):
PCI: Introduce new MSI chip infrastructure
Thomas Petazzoni (9):
PCI: use weak functions for MSI arch-specific functions
PCI: remove ARCH_SUPPORTS_MSI kconfig option
of: pci: add registry of MSI chips
irqchip: armada-370-xp: properly request resources
irqchip: armada-370-xp: implement MSI support
ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pci
ARM: mvebu: the MPIC now provides MSI controller features
PCI: mvebu: add support for MSI
ARM: mvebu: link PCIe controllers to the MSI controller
.../devicetree/bindings/arm/armada-370-xp-mpic.txt | 3 + .../devicetree/bindings/pci/mvebu-pci.txt | 3 + arch/arm/Kconfig | 1 - arch/arm/boot/dts/armada-370-xp.dtsi | 1 + arch/arm/boot/dts/armada-370.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 1 + arch/arm/include/asm/mach/pci.h | 4 + arch/arm/kernel/bios32.c | 16 ++ arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 2 - arch/mips/include/asm/pci.h | 5 - arch/powerpc/Kconfig | 1 - arch/powerpc/include/asm/pci.h | 5 - arch/s390/Kconfig | 1 - arch/s390/include/asm/pci.h | 4 - arch/sparc/Kconfig | 1 - arch/tile/Kconfig | 1 - arch/x86/Kconfig | 1 - arch/x86/include/asm/pci.h | 28 --- arch/x86/kernel/x86_init.c | 21 +++ drivers/irqchip/irq-armada-370-xp.c | 202 ++++++++++++++++++++- drivers/of/of_pci.c | 45 +++++ drivers/pci/Kconfig | 4 - drivers/pci/host/pci-mvebu.c | 26 +++ drivers/pci/msi.c | 69 ++++--- drivers/pci/probe.c | 1 + include/linux/msi.h | 21 ++- include/linux/of_pci.h | 12 ++ include/linux/pci.h | 1 + 31 files changed, 400 insertions(+), 84 deletions(-)
Signature · 1 line
1.8.1.2
PATCH v8 1/10 PCI: use weak functions for MSI arch-specific functions
Until now, the MSI architecture-specific functions could be overloaded using a fairly complex set of #define and compile-time conditionals. In order to prepare for the introduction of the msi_chip infrastructure, it is desirable to switch all those functions to use the 'weak' mechanism. This commit converts all the architectures that were overidding those MSI functions to use the new strategy.
Note that we keep two separate, non-weak, functions default_teardown_msi_irqs() and default_restore_msi_irqs() for the default behavior of the arch_teardown_msi_irqs() and arch_restore_msi_irqs(), as the default behavior is needed by x86 PCI code.
--- arch/mips/include/asm/pci.h | 5 ----- arch/powerpc/include/asm/pci.h | 5 ----- arch/s390/include/asm/pci.h | 4 ---- arch/x86/include/asm/pci.h | 28 ------------------------ arch/x86/kernel/x86_init.c | 21 ++++++++++++++++++ drivers/pci/msi.c | 48 +++++++++++++++++++++--------------------- include/linux/msi.h | 8 ++++++- 7 files changed, 52 insertions(+), 67 deletions(-)
arch/mips/include/asm/pci.h +0 -5
@@ -136,11 +136,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)return channel ?15 :14 ; } -#ifdef CONFIG_CPU_CAVIUM_OCTEON -/* MSI arch hook for OCTEON */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#endif -extern char * (*pcibios_plat_setup)(char *str);#ifdef CONFIG_OF
arch/powerpc/include/asm/pci.h +0 -5
@@ -113,11 +113,6 @@ extern int pci_domain_nr(struct pci_bus *bus);/* Decide whether to display the domain number in /proc */ extern int pci_proc_domain (struct pci_bus *bus); -/* MSI arch hooks */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#define arch_teardown_msi_irqs arch_teardown_msi_irqs -#define arch_msi_check_device arch_msi_check_device -struct vm_area_struct ;/* Map a range of PCI memory or I/O space for a device into user space */ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
arch/s390/include/asm/pci.h +0 -4
@@ -21,10 +21,6 @@ void pci_iounmap(struct pci_dev *, void __iomem *);int pci_domain_nr (struct pci_bus *);int pci_proc_domain (struct pci_bus *); -/* MSI arch hooks */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#define arch_teardown_msi_irqs arch_teardown_msi_irqs -#define ZPCI_BUS_NR 0/* default bus number */ #define ZPCI_DEVFN 0/* default device number */
arch/x86/include/asm/pci.h +0 -28
@@ -100,29 +100,6 @@ static inline void early_quirks(void) { }extern void pci_iommu_alloc (void );#ifdef CONFIG_PCI_MSI -/* MSI arch specific hooks */ -static inline int x86_setup_msi_irqs (struct pci_dev *dev,int nvec,int type) -{ -return x86_msi.setup_msi_irqs (dev, nvec, type); -} - -static inline void x86_teardown_msi_irqs (struct pci_dev *dev) -{ - x86_msi.teardown_msi_irqs (dev); -} - -static inline void x86_teardown_msi_irq (unsigned int irq) -{ - x86_msi.teardown_msi_irq (irq); -} -static inline void x86_restore_msi_irqs (struct pci_dev *dev,int irq) -{ - x86_msi.restore_msi_irqs (dev, irq); -} -#define arch_setup_msi_irqs x86_setup_msi_irqs -#define arch_teardown_msi_irqs x86_teardown_msi_irqs -#define arch_teardown_msi_irq x86_teardown_msi_irq -#define arch_restore_msi_irqs x86_restore_msi_irqs/* implemented in arch/x86/kernel/apic/io_apic. */ struct msi_desc ;int native_setup_msi_irqs (struct pci_dev *dev,int nvec,int type);
@@ -130,11 +107,6 @@ void native_teardown_msi_irq(unsigned int irq);void native_restore_msi_irqs (struct pci_dev *dev,int irq);int setup_msi_irq (struct pci_dev *dev,struct msi_desc *msidesc,unsigned int irq_base,unsigned int irq_offset); -/* default to the implementation in drivers/lib/msi.c */ -#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS -#define HAVE_DEFAULT_MSI_RESTORE_IRQS -void default_teardown_msi_irqs (struct pci_dev *dev); -void default_restore_msi_irqs (struct pci_dev *dev,int irq);#else #define native_setup_msi_irqs NULL#define native_teardown_msi_irq NULL
arch/x86/kernel/x86_init.c +21 -0
@@ -116,6 +116,27 @@ struct x86_msi_ops x86_msi = { .setup_hpet_msi = default_setup_hpet_msi, }; +/* MSI arch specific hooks */ +int arch_setup_msi_irqs (struct pci_dev *dev,int nvec,int type) +{ +return x86_msi.setup_msi_irqs (dev, nvec, type); +} + +void arch_teardown_msi_irqs (struct pci_dev *dev) +{ + x86_msi.teardown_msi_irqs (dev); +} + +void arch_teardown_msi_irq (unsigned int irq) +{ + x86_msi.teardown_msi_irq (irq); +} + +void arch_restore_msi_irqs (struct pci_dev *dev,int irq) +{ + x86_msi.restore_msi_irqs (dev, irq); +} +struct x86_io_apic_ops x86_io_apic_ops = { .init = native_io_apic_init_mappings, .read = native_io_apic_read,
drivers/pci/msi.c +24 -24
79 lines not on this page · raw message
include/linux/msi.h +7 -1
@@ -51,12 +51,18 @@ struct msi_desc { };/* -* The arch hook for setup up msi irqs +* The arch hooks to setup up msi irqs. Those functions are +* implemented as weak symbols so that they /can/ be overriden by +* architecture specific code if needed. */ int arch_setup_msi_irq (struct pci_dev *dev,struct msi_desc *desc);void arch_teardown_msi_irq (unsigned int irq);int arch_setup_msi_irqs (struct pci_dev *dev,int nvec,int type);void arch_teardown_msi_irqs (struct pci_dev *dev);int arch_msi_check_device (struct pci_dev * dev,int nvec,int type); +void arch_restore_msi_irqs (struct pci_dev *dev,int irq); + +void default_teardown_msi_irqs (struct pci_dev *dev); +void default_restore_msi_irqs (struct pci_dev *dev,int irq);#endif /* LINUX_MSI_H */
Signature · 1 line
1.8.1.2
PATCH v8 1/10 PCI: use weak functions for MSI arch-specific functions
Quoted 7 lines · Thomas Petazzoni
Until now, the MSI architecture-specific functions could be overloaded using a fairly complex set of #define and compile-time conditionals. In order to prepare for the introduction of the
msi_chipinfrastructure, it is desirable to switch all those functions to use the 'weak' mechanism. This commit converts all the architectures that were overidding those MSI functions to use the new strategy.
Quoted 5 lines
Note that we keep two separate, non-weak, functions
default_teardown_msi_irqs()anddefault_restore_msi_irqs()for the default behavior of thearch_teardown_msi_irqs()andarch_restore_msi_irqs(), as the default behavior is needed by x86 PCI code.
Looks good, I'll give it a quick spin to make sure there is no accidental breakage on ppc today.
Quoted 4 lines
Signed-off-by Thomas Petazzoni <[email protected]>Acked-by Bjorn Helgaas <[email protected]>Tested-by Daniel Price <[email protected]>Tested-by Thierry Reding <[email protected]>
Quoted 265 lines
Cc Paul Mackerras <[email protected]>Cc linuxppc-dev at lists.ozlabs.orgCc Martin Schwidefsky <[email protected]>Cc Heiko Carstens <[email protected]>Cc linux390 at de.ibm.comCc linux-s390 at vger.kernel.orgCc Thomas Gleixner <[email protected]>Cc Ingo Molnar <[email protected]>Cc H. Peter Anvin <[email protected]>Cc x86 at kernel.orgCc Russell King <[email protected]>Cc Tony Luck <[email protected]>Cc Fenghua Yu <[email protected]>Cc linux-ia64 at vger.kernel.orgCc Ralf Baechle <[email protected]>Cc linux-mips at linux-mips.orgCc David S. Miller <[email protected]>Cc sparclinux at vger.kernel.orgCc Chris Metcalf <[email protected]>--- arch/mips/include/asm/pci.h | 5 ----- arch/powerpc/include/asm/pci.h | 5 ----- arch/s390/include/asm/pci.h | 4 ---- arch/x86/include/asm/pci.h | 28 ------------------------ arch/x86/kernel/x86_init.c | 21 ++++++++++++++++++ drivers/pci/msi.c | 48 +++++++++++++++++++++--------------------- include/linux/msi.h | 8 ++++++- 7 files changed, 52 insertions(+), 67 deletions(-)arch/mips/include/asm/pci.h +0
-5@@ -136,11 +136,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)return channel ?15 :14 ; } -#ifdef CONFIG_CPU_CAVIUM_OCTEON -/* MSI arch hook for OCTEON */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#endif -extern char * (*pcibios_plat_setup)(char *str);#ifdef CONFIG_OF arch/powerpc/include/asm/pci.h +0
-5@@ -113,11 +113,6 @@ extern int pci_domain_nr(struct pci_bus *bus);/* Decide whether to display the domain number in /proc */ extern int pci_proc_domain (struct pci_bus *bus); -/* MSI arch hooks */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#define arch_teardown_msi_irqs arch_teardown_msi_irqs -#define arch_msi_check_device arch_msi_check_device -struct vm_area_struct ;/* Map a range of PCI memory or I/O space for a device into user space */ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,arch/s390/include/asm/pci.h +0
-4@@ -21,10 +21,6 @@ void pci_iounmap(struct pci_dev *, void __iomem *);int pci_domain_nr (struct pci_bus *);int pci_proc_domain (struct pci_bus *); -/* MSI arch hooks */ -#define arch_setup_msi_irqs arch_setup_msi_irqs -#define arch_teardown_msi_irqs arch_teardown_msi_irqs -#define ZPCI_BUS_NR 0/* default bus number */ #define ZPCI_DEVFN 0/* default device number */ arch/x86/include/asm/pci.h +0
-28@@ -100,29 +100,6 @@ static inline void early_quirks(void) { }extern void pci_iommu_alloc (void );#ifdef CONFIG_PCI_MSI -/* MSI arch specific hooks */ -static inline int x86_setup_msi_irqs (struct pci_dev *dev,int nvec,int type) -{ -return x86_msi.setup_msi_irqs (dev, nvec, type); -} - -static inline void x86_teardown_msi_irqs (struct pci_dev *dev) -{ - x86_msi.teardown_msi_irqs (dev); -} - -static inline void x86_teardown_msi_irq (unsigned int irq) -{ - x86_msi.teardown_msi_irq (irq); -} -static inline void x86_restore_msi_irqs (struct pci_dev *dev,int irq) -{ - x86_msi.restore_msi_irqs (dev, irq); -} -#define arch_setup_msi_irqs x86_setup_msi_irqs -#define arch_teardown_msi_irqs x86_teardown_msi_irqs -#define arch_teardown_msi_irq x86_teardown_msi_irq -#define arch_restore_msi_irqs x86_restore_msi_irqs/* implemented in arch/x86/kernel/apic/io_apic. */ struct msi_desc ;int native_setup_msi_irqs (struct pci_dev *dev,int nvec,int type);@@ -130,11 +107,6 @@ void native_teardown_msi_irq(unsigned int irq);void native_restore_msi_irqs (struct pci_dev *dev,int irq);int setup_msi_irq (struct pci_dev *dev,struct msi_desc *msidesc,unsigned int irq_base,unsigned int irq_offset); -/* default to the implementation in drivers/lib/msi.c */ -#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS -#define HAVE_DEFAULT_MSI_RESTORE_IRQS -void default_teardown_msi_irqs (struct pci_dev *dev); -void default_restore_msi_irqs (struct pci_dev *dev,int irq);#else #define native_setup_msi_irqs NULL#define native_teardown_msi_irq NULLarch/x86/kernel/x86_init.c +21
-0@@ -116,6 +116,27 @@ struct x86_msi_ops x86_msi = { .setup_hpet_msi = default_setup_hpet_msi, }; +/* MSI arch specific hooks */ +int arch_setup_msi_irqs (struct pci_dev *dev,int nvec,int type) +{ +return x86_msi.setup_msi_irqs (dev, nvec, type); +} + +void arch_teardown_msi_irqs (struct pci_dev *dev) +{ + x86_msi.teardown_msi_irqs (dev); +} + +void arch_teardown_msi_irq (unsigned int irq) +{ + x86_msi.teardown_msi_irq (irq); +} + +void arch_restore_msi_irqs (struct pci_dev *dev,int irq) +{ + x86_msi.restore_msi_irqs (dev, irq); +} +struct x86_io_apic_ops x86_io_apic_ops = { .init = native_io_apic_init_mappings, .read = native_io_apic_read,drivers/pci/msi.c +24
-24@@ -30,20 +30,21 @@ static int pci_msi_enable = 1;/* Arch hooks */ -#ifndef arch_msi_check_device -int arch_msi_check_device (struct pci_dev *dev,int nvec,int type) +int __weak arch_setup_msi_irq (struct pci_dev *dev,struct msi_desc *desc) { -return 0 ; +return -EINVAL ; } -#endif -#ifndef arch_setup_msi_irqs -# define arch_setup_msi_irqs default_setup_msi_irqs -# define HAVE_DEFAULT_MSI_SETUP_IRQS -#endif +void __weak arch_teardown_msi_irq (unsigned int irq) +{ +} -#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS -int default_setup_msi_irqs (struct pci_dev *dev,int nvec,int type) +int __weak arch_msi_check_device (struct pci_dev *dev,int nvec,int type) +{ +return 0 ; +} + +int __weak arch_setup_msi_irqs (struct pci_dev *dev,int nvec,int type) {struct msi_desc *entry;int ret;@@ -65,14 +66,11 @@ int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)return 0 ; } -#endif - -#ifndef arch_teardown_msi_irqs -# define arch_teardown_msi_irqs default_teardown_msi_irqs -# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS -#endif -#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS +/* +* We have a default implementation available as a separate non-weak +* function, as it is used by the Xen x86 PCI code +*/ void default_teardown_msi_irqs (struct pci_dev *dev) {struct msi_desc *entry;@@ -89,14 +87,12 @@ void default_teardown_msi_irqs(struct pci_dev *dev)arch_teardown_msi_irq (entry->irq + i); } } -#endif -#ifndef arch_restore_msi_irqs -# define arch_restore_msi_irqs default_restore_msi_irqs -# define HAVE_DEFAULT_MSI_RESTORE_IRQS -#endif +void __weak arch_teardown_msi_irqs (struct pci_dev *dev) +{ +return default_teardown_msi_irqs (dev); +} -#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS void default_restore_msi_irqs (struct pci_dev *dev,int irq) {struct msi_desc *entry;@@ -114,7 +110,11 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq)if (entry)write_msi_msg (irq, &entry->msg); } -#endif + +void __weak arch_restore_msi_irqs (struct pci_dev *dev,int irq) +{ +return default_restore_msi_irqs (dev, irq); +}static void msi_set_enable (struct pci_dev *dev,int enable) {include/linux/msi.h +7
-1@@ -51,12 +51,18 @@ struct msi_desc { };/* -* The arch hook for setup up msi irqs +* The arch hooks to setup up msi irqs. Those functions are +* implemented as weak symbols so that they /can/ be overriden by +* architecture specific code if needed. */ int arch_setup_msi_irq (struct pci_dev *dev,struct msi_desc *desc);void arch_teardown_msi_irq (unsigned int irq);int arch_setup_msi_irqs (struct pci_dev *dev,int nvec,int type);void arch_teardown_msi_irqs (struct pci_dev *dev);int arch_msi_check_device (struct pci_dev * dev,int nvec,int type); +void arch_restore_msi_irqs (struct pci_dev *dev,int irq); + +void default_teardown_msi_irqs (struct pci_dev *dev); +void default_restore_msi_irqs (struct pci_dev *dev,int irq);#endif /* LINUX_MSI_H */
PATCH v8 2/10 PCI: remove ARCH_SUPPORTS_MSI kconfig option
In reply to Thomas PetazzoniNow that we have weak versions for each of the PCI MSI architecture functions, we can actually build the MSI support for all platforms, regardless of whether they provide or not architecture-specific versions of those functions. For this reason, the ARCH_SUPPORTS_MSI hidden kconfig boolean becomes useless, and this patch gets rid of it.
--- arch/arm/Kconfig | 1 - arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 2 -- arch/powerpc/Kconfig | 1 - arch/s390/Kconfig | 1 - arch/sparc/Kconfig | 1 - arch/tile/Kconfig | 1 - arch/x86/Kconfig | 1 - drivers/pci/Kconfig | 4 ---- 9 files changed, 13 deletions(-)
arch/arm/Kconfig +0 -1
@@ -441,7 +441,6 @@ config ARCH_NETX config ARCH_IOP13XX bool "IOP13xx-based" depends on MMU - select ARCH_SUPPORTS_MSI select CPU_XSC3 select NEED_MACH_MEMORY_H select NEED_RET_TO_USER
arch/ia64/Kconfig +0 -1
@@ -9,7 +9,6 @@ config IA64 select PCI if (!IA64_HP_SIM) select ACPI if (!IA64_HP_SIM) select PM if (!IA64_HP_SIM) - select ARCH_SUPPORTS_MSI select HAVE_UNSTABLE_SCHED_CLOCK select HAVE_IDE select HAVE_OPROFILE
arch/mips/Kconfig +0 -2
@@ -726,7 +726,6 @@ config CAVIUM_OCTEON_SOC select SYS_HAS_CPU_CAVIUM_OCTEON select SWAP_IO_SPACE select HW_HAS_PCI - select ARCH_SUPPORTS_MSI select ZONE_DMA32 select USB_ARCH_HAS_OHCI select USB_ARCH_HAS_EHCI
@@ -762,7 +761,6 @@ config NLM_XLR_BOARD select CEVT_R4K select CSRC_R4K select IRQ_CPU - select ARCH_SUPPORTS_MSI select ZONE_DMA32 if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK
arch/powerpc/Kconfig +0 -1
@@ -727,7 +727,6 @@ config PCI default y if !40x && !CPM2 && !8xx && !PPC_83xx \ && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON default PCI_QSPAN if !4xx && !CPM2 && 8xx - select ARCH_SUPPORTS_MSI select GENERIC_PCI_IOMAP help Find out whether your system includes a PCI bus. PCI is the name of
arch/s390/Kconfig +0 -1
@@ -428,7 +428,6 @@ menuconfig PCI bool "PCI support" default n depends on 64BIT - select ARCH_SUPPORTS_MSI select PCI_MSI help Enable PCI support.
arch/sparc/Kconfig +0 -1
@@ -52,7 +52,6 @@ config SPARC32 config SPARC64 def_bool 64BIT - select ARCH_SUPPORTS_MSI select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FUNCTION_GRAPH_FP_TEST
arch/tile/Kconfig +0 -1
@@ -380,7 +380,6 @@ config PCI select PCI_DOMAINS select GENERIC_PCI_IOMAP select TILE_GXIO_TRIO if TILEGX - select ARCH_SUPPORTS_MSI if TILEGX select PCI_MSI if TILEGX ---help--- Enable PCI root complex support, so PCIe endpoint devices can
arch/x86/Kconfig +0 -1
@@ -2014,7 +2014,6 @@ menu "Bus options (PCI etc.)" config PCI bool "PCI support" default y - select ARCH_SUPPORTS_MSI if (X86_LOCAL_APIC && X86_IO_APIC) ---help--- Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside
drivers/pci/Kconfig +0 -4
@@ -1,13 +1,9 @@ # # PCI configuration # -config ARCH_SUPPORTS_MSI - bool - config PCI_MSI bool "Message Signaled Interrupts (MSI and MSI-X)" depends on PCI - depends on ARCH_SUPPORTS_MSI help This allows device drivers to enable MSI (Message Signaled Interrupts). Message Signaled Interrupts enable a device to
Signature · 1 line
1.8.1.2
PATCH v8 2/10 PCI: remove ARCH_SUPPORTS_MSI kconfig option
Quoted 10 lines · Thomas Petazzoni
Now that we have weak versions for each of the PCI MSI architecture functions, we can actually build the MSI support for all platforms, regardless of whether they provide or not architecture-specific versions of those functions. For this reason, the
ARCH_SUPPORTS_MSIhidden kconfig boolean becomes useless, and this patch gets rid of it.Signed-off-by Thomas Petazzoni <[email protected]>Acked-by Bjorn Helgaas <[email protected]>Tested-by Daniel Price <[email protected]>Tested-by Thierry Reding <[email protected]>
Quoted 153 lines
Cc Paul Mackerras <[email protected]>Cc linuxppc-dev at lists.ozlabs.orgCc Martin Schwidefsky <[email protected]>Cc Heiko Carstens <[email protected]>Cc linux390 at de.ibm.comCc linux-s390 at vger.kernel.orgCc Thomas Gleixner <[email protected]>Cc Ingo Molnar <[email protected]>Cc H. Peter Anvin <[email protected]>Cc x86 at kernel.orgCc Russell King <[email protected]>Cc Tony Luck <[email protected]>Cc Fenghua Yu <[email protected]>Cc linux-ia64 at vger.kernel.orgCc Ralf Baechle <[email protected]>Cc linux-mips at linux-mips.orgCc David S. Miller <[email protected]>Cc sparclinux at vger.kernel.orgCc Chris Metcalf <[email protected]>--- arch/arm/Kconfig | 1 - arch/ia64/Kconfig | 1 - arch/mips/Kconfig | 2 -- arch/powerpc/Kconfig | 1 - arch/s390/Kconfig | 1 - arch/sparc/Kconfig | 1 - arch/tile/Kconfig | 1 - arch/x86/Kconfig | 1 - drivers/pci/Kconfig | 4 ---- 9 files changed, 13 deletions(-)arch/arm/Kconfig +0
-1@@ -441,7 +441,6 @@ config ARCH_NETX config ARCH_IOP13XX bool "IOP13xx-based" depends on MMU - select ARCH_SUPPORTS_MSI select CPU_XSC3 select NEED_MACH_MEMORY_H select NEED_RET_TO_USERarch/ia64/Kconfig +0
-1@@ -9,7 +9,6 @@ config IA64 select PCI if (!IA64_HP_SIM) select ACPI if (!IA64_HP_SIM) select PM if (!IA64_HP_SIM) - select ARCH_SUPPORTS_MSI select HAVE_UNSTABLE_SCHED_CLOCK select HAVE_IDE select HAVE_OPROFILEarch/mips/Kconfig +0
-2@@ -726,7 +726,6 @@ config CAVIUM_OCTEON_SOC select SYS_HAS_CPU_CAVIUM_OCTEON select SWAP_IO_SPACE select HW_HAS_PCI - select ARCH_SUPPORTS_MSI select ZONE_DMA32 select USB_ARCH_HAS_OHCI select USB_ARCH_HAS_EHCI@@ -762,7 +761,6 @@ config NLM_XLR_BOARD select CEVT_R4K select CSRC_R4K select IRQ_CPU - select ARCH_SUPPORTS_MSI select ZONE_DMA32 if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTKarch/powerpc/Kconfig +0
-1@@ -727,7 +727,6 @@ config PCI default y if !40x && !CPM2 && !8xx && !PPC_83xx \ && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON default PCI_QSPAN if !4xx && !CPM2 && 8xx - select ARCH_SUPPORTS_MSI select GENERIC_PCI_IOMAP help Find out whether your system includes a PCI bus. PCI is the name ofarch/s390/Kconfig +0
-1@@ -428,7 +428,6 @@ menuconfig PCI bool "PCI support" default n depends on 64BIT - select ARCH_SUPPORTS_MSI select PCI_MSI help Enable PCI support.arch/sparc/Kconfig +0
-1@@ -52,7 +52,6 @@ config SPARC32 config SPARC64 def_bool 64BIT - select ARCH_SUPPORTS_MSI select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FUNCTION_GRAPH_FP_TESTarch/tile/Kconfig +0
-1@@ -380,7 +380,6 @@ config PCI select PCI_DOMAINS select GENERIC_PCI_IOMAP select TILE_GXIO_TRIO if TILEGX - select ARCH_SUPPORTS_MSI if TILEGX select PCI_MSI if TILEGX ---help--- Enable PCI root complex support, so PCIe endpoint devices canarch/x86/Kconfig +0
-1@@ -2014,7 +2014,6 @@ menu "Bus options (PCI etc.)" config PCI bool "PCI support" default y - select ARCH_SUPPORTS_MSI if (X86_LOCAL_APIC && X86_IO_APIC) ---help--- Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff insidedrivers/pci/Kconfig +0
-4@@ -1,13 +1,9 @@ # # PCI configuration # -config ARCH_SUPPORTS_MSI - bool - config PCI_MSI bool "Message Signaled Interrupts (MSI and MSI-X)" depends on PCI - depends on ARCH_SUPPORTS_MSI help This allows device drivers to enable MSI (Message Signaled Interrupts). Message Signaled Interrupts enable a device to
PATCH v8 3/10 PCI: Introduce new MSI chip infrastructure
In reply to Thomas PetazzoniFrom: Thierry Reding <[email protected]>
The new struct msi_chip is used to associated an MSI controller with a PCI bus. It is automatically handed down from the root to its children during bus enumeration.
This patch provides default (weak) implementations for the architecture- specific MSI functions (arch_setup_msi_irq(), arch_teardown_msi_irq() and arch_msi_check_device()) which check if a PCI device's bus has an attached MSI chip and forward the call appropriately.
--- drivers/pci/msi.c | 27 +++++++++++++++++++++++++-- drivers/pci/probe.c | 1 + include/linux/msi.h | 11 +++++++++++ include/linux/pci.h | 1 + 4 files changed, 38 insertions(+), 2 deletions(-)
drivers/pci/msi.c +25 -2
@@ -32,16 +32,39 @@ static int pci_msi_enable = 1;int __weak arch_setup_msi_irq (struct pci_dev *dev,struct msi_desc *desc) { -return -EINVAL ; +struct msi_chip *chip = dev->bus->msi; +int err; + +if (!chip || !chip->setup_irq) +return -EINVAL ; + + err = chip->setup_irq (chip, dev, desc); +if (err <0 ) +return err; + +irq_set_chip_data (desc->irq, chip); + +return 0 ; }void __weak arch_teardown_msi_irq (unsigned int irq) { +struct msi_chip *chip =irq_get_chip_data (irq); + +if (!chip || !chip->teardown_irq) +return ; + + chip->teardown_irq (chip, irq); }int __weak arch_msi_check_device (struct pci_dev *dev,int nvec,int type) { -return 0 ; +struct msi_chip *chip = dev->bus->msi; + +if (!chip || !chip->check_device) +return 0 ; + +return chip->check_device (chip, dev, nvec, type); }int __weak arch_setup_msi_irqs (struct pci_dev *dev,int nvec,int type)
drivers/pci/probe.c +1 -0
@@ -666,6 +666,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, child->parent = parent; child->ops = parent->ops; + child->msi = parent->msi; child->sysdata = parent->sysdata; child->bus_flags = parent->bus_flags;
include/linux/msi.h +11 -0
@@ -65,4 +65,15 @@ void arch_restore_msi_irqs(struct pci_dev *dev, int irq);void default_teardown_msi_irqs (struct pci_dev *dev);void default_restore_msi_irqs (struct pci_dev *dev,int irq); +struct msi_chip { +struct module *owner; +struct device *dev; + +int (*setup_irq)(struct msi_chip *chip,struct pci_dev *dev, +struct msi_desc *desc); +void (*teardown_irq)(struct msi_chip *chip,unsigned int irq); +int (*check_device)(struct msi_chip *chip,struct pci_dev *dev, +int nvec,int type); +}; +#endif /* LINUX_MSI_H */
include/linux/pci.h +1 -0
@@ -433,6 +433,7 @@ struct pci_bus {struct resource busn_res;/* bus numbers routed to this bus */ struct pci_ops *ops;/* configuration access functions */ +struct msi_chip *msi;/* MSI controller */ void *sysdata;/* hook for sys-specific extension */ struct proc_dir_entry *procdir;/* directory entry in /proc/bus/pci */
Signature · 1 line
1.8.1.2
PATCH v8 4/10 of: pci: add registry of MSI chips
In reply to Thomas PetazzoniThis commit adds a very basic registry of msi_chip structures, so that an IRQ controller driver can register an msi_chip, and a PCIe host controller can find it, based on a 'struct device_node'.
--- drivers/of/of_pci.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/msi.h | 2 ++ include/linux/of_pci.h | 12 ++++++++++++ 3 files changed, 59 insertions(+)
drivers/of/of_pci.c +45 -0
@@ -89,3 +89,48 @@ int of_pci_parse_bus_range(struct device_node *node, struct resource *res)return 0 ; }EXPORT_SYMBOL_GPL (of_pci_parse_bus_range); + +#ifdef CONFIG_PCI_MSI + +static LIST_HEAD (of_pci_msi_chip_list); +static DEFINE_MUTEX (of_pci_msi_chip_mutex); + +int of_pci_msi_chip_add (struct msi_chip *chip) +{ +if (!of_property_read_bool (chip->of_node,"msi-controller" )) +return -EINVAL ; + +mutex_lock (&of_pci_msi_chip_mutex); +list_add (&chip->list, &of_pci_msi_chip_list); +mutex_unlock (&of_pci_msi_chip_mutex); + +return 0 ; +} +EXPORT_SYMBOL_GPL (of_pci_msi_chip_add); + +void of_pci_msi_chip_remove (struct msi_chip *chip) +{ +mutex_lock (&of_pci_msi_chip_mutex); +list_del (&chip->list); +mutex_unlock (&of_pci_msi_chip_mutex); +} +EXPORT_SYMBOL_GPL (of_pci_msi_chip_remove); + +struct msi_chip *of_pci_find_msi_chip_by_node (struct device_node *of_node) +{ +struct msi_chip *c; + +mutex_lock (&of_pci_msi_chip_mutex); +list_for_each_entry (c, &of_pci_msi_chip_list, list) { +if (c->of_node == of_node) { +mutex_unlock (&of_pci_msi_chip_mutex); +return c; + } + } +mutex_unlock (&of_pci_msi_chip_mutex); + +return NULL ; +} +EXPORT_SYMBOL_GPL (of_pci_find_msi_chip_by_node); + +#endif /* CONFIG_PCI_MSI */
include/linux/msi.h +2 -0
@@ -68,6 +68,8 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq);struct msi_chip {struct module *owner;struct device *dev; +struct device_node *of_node; +struct list_head list;int (*setup_irq)(struct msi_chip *chip,struct pci_dev *dev,struct msi_desc *desc);
include/linux/of_pci.h +12 -0
@@ -2,6 +2,7 @@#define __OF_PCI_H#include <linux/pci.h> +#include <linux/msi.h> struct pci_dev ;struct of_irq ;
@@ -13,4 +14,15 @@ struct device_node *of_pci_find_child_device(struct device_node *parent,int of_pci_get_devfn (struct device_node *np);int of_pci_parse_bus_range (struct device_node *node,struct resource *res); +#if defined(CONFIG_OF ) && defined(CONFIG_PCI_MSI ) +int of_pci_msi_chip_add (struct msi_chip *chip); +void of_pci_msi_chip_remove (struct msi_chip *chip); +struct msi_chip *of_pci_find_msi_chip_by_node (struct device_node *of_node); +#else +static inline int of_pci_msi_chip_add (struct msi_chip *chip) {return -EINVAL ; } +static inline void of_pci_msi_chip_remove (struct msi_chip *chip) { } +static inline struct msi_chip * +of_pci_find_msi_chip_by_node(struct device_node *of_node) { return NULL }; +#endif +#endif
Signature · 1 line
1.8.1.2
PATCH v8 4/10 of: pci: add registry of MSI chips
include/linux/of_pci.h struct device_node *of_pci_find_child_device(struct device_node *parent, · line 23
Quoted 10 lines · Thomas Petazzoni
include/linux/of_pci.h +4
-0+#if defined(CONFIG_OF ) && defined(CONFIG_PCI_MSI ) +int of_pci_msi_chip_add (struct msi_chip *chip); +void of_pci_msi_chip_remove (struct msi_chip *chip); +struct msi_chip *of_pci_find_msi_chip_by_node(struct device_node
*of_node);include/linux/of_pci.h +3
-1+#else +static inline int of_pci_msi_chip_add (struct msi_chip *chip) {return -EINVAL ; } +static inline void of_pci_msi_chip_remove(struct msi_chip *chip) { }
Missing a ; at the end of the above line... breaks the build of CONFIG_PCI_MSI is not set.
Quoted 6 lines
(quoted diff) +2
-0+static inline struct msi_chip * +of_pci_find_msi_chip_by_node(struct device_node *of_node) { returnNULL };
include/linux/of_pci.h +2
-0+#endif +#endif
PATCH v8 4/10 of: pci: add registry of MSI chips
Thomas,
Quoted 14 lines · Benjamin Herrenschmidt
include/linux/of_pci.h struct device_node *of_pci_find_child_device(struct device_node *parent, · line 23
Quoted 10 lines · Thomas Petazzoni
include/linux/of_pci.h +4
-0+#if defined(CONFIG_OF ) && defined(CONFIG_PCI_MSI ) +int of_pci_msi_chip_add (struct msi_chip *chip); +void of_pci_msi_chip_remove (struct msi_chip *chip); +struct msi_chip *of_pci_find_msi_chip_by_node(struct device_node
*of_node);include/linux/of_pci.h +3
-1+#else +static inline int of_pci_msi_chip_add (struct msi_chip *chip) {return -EINVAL ; } +static inline void of_pci_msi_chip_remove(struct msi_chip *chip) { }Missing a ; at the end of the above line... breaks the build of
CONFIG_PCI_MSIis not set.
If this is the same error Randy reported yesterday from -next, I'll just fix it up when I pull it in.
thx,
Jason.
PATCH v8 4/10 of: pci: add registry of MSI chips
In reply to Benjamin HerrenschmidtQuoted 15 lines · Benjamin Herrenschmidt
Review
Quoted 10 lines · Thomas Petazzoni
(quoted diff) +4
-0+#if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI) +int of_pci_msi_chip_add(struct msi_chip *chip); +void of_pci_msi_chip_remove(struct msi_chip *chip); +struct msi_chip *of_pci_find_msi_chip_by_node(struct device_node
*of_node);(quoted diff) +3
-1+#else +static inline int of_pci_msi_chip_add(struct msi_chip *chip) { return -EINVAL; } +static inline void of_pci_msi_chip_remove(struct msi_chip *chip) { }Missing a ; at the end of the above line... breaks the build of
CONFIG_PCI_MSIis not set.
Quoted 6 lines
Review
Quoted 6 lines
(quoted diff) +2
-0+static inline struct msi_chip * +of_pci_find_msi_chip_by_node(struct device_node *of_node) { returnNULL };
(quoted diff) +2
-0+#endif + #endif
Reproduced, fixed and builds clean !CONFIG_OF and !CONFIG_PCI_MSI with:
---------------->8----------------
include/linux/of_pci.h +4 -3
@@ -19,10 +19,11 @@ int of_pci_msi_chip_add(struct msi_chip *chip);void of_pci_msi_chip_remove (struct msi_chip *chip);struct msi_chip *of_pci_find_msi_chip_by_node (struct device_node *of_node);#else -static inline int of_pci_msi_chip_add (struct msi_chip *chip) {return -EINVAL ; } -static inline void of_pci_msi_chip_remove (struct msi_chip *chip) { } +static inline int +of_pci_msi_chip_add (struct msi_chip *chip) {return -EINVAL ; }; +static inline void of_pci_msi_chip_remove (struct msi_chip *chip) { };static inline struct msi_chip * -of_pci_find_msi_chip_by_node(struct device_node *of_node) { return NULL }; +of_pci_find_msi_chip_by_node (struct device_node *of_node) {return NULL ; };#endif #endif
PATCH v8 4/10 of: pci: add registry of MSI chips
Quoted 35 lines · Jason Cooper
Quoted 15 lines · Benjamin Herrenschmidt
Review
Quoted 10 lines · Thomas Petazzoni
(quoted diff) +4
-0+#if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI) +int of_pci_msi_chip_add(struct msi_chip *chip); +void of_pci_msi_chip_remove(struct msi_chip *chip); +struct msi_chip *of_pci_find_msi_chip_by_node(struct device_node
*of_node);(quoted diff) +3
-1+#else +static inline int of_pci_msi_chip_add(struct msi_chip *chip) { return -EINVAL; } +static inline void of_pci_msi_chip_remove(struct msi_chip *chip) { }Missing a ; at the end of the above line... breaks the build of
CONFIG_PCI_MSIis not set.Quoted 6 lines
Review
Quoted 6 lines
(quoted diff) +2
-0+static inline struct msi_chip * +of_pci_find_msi_chip_by_node(struct device_node *of_node) { returnNULL };
(quoted diff) +2
-0+#endif + #endifReproduced, fixed and builds clean !CONFIG_OF and !CONFIG_PCI_MSI with:
---------------->8----------------
include/linux/of_pci.h +0
-1@@ -19,10 +19,11 @@ int of_pci_msi_chip_add(struct msi_chip *chip);void of_pci_msi_chip_remove (struct msi_chip *chip);struct msi_chip *of_pci_find_msi_chip_by_node (struct device_node *of_node);#else -static inline int of_pci_msi_chip_add (struct msi_chip *chip) {return -EINVAL ; }
include/linux/of_pci.h int of_pci_msi_chip_add(struct msi_chip *chip); · line 29
Quoted 10 lines
include/linux/of_pci.h +4
-2-static inline void of_pci_msi_chip_remove (struct msi_chip *chip) { } +static inline int +of_pci_msi_chip_add (struct msi_chip *chip) {return -EINVAL ; }; +static inline void of_pci_msi_chip_remove (struct msi_chip *chip) { };static inline struct msi_chip * -of_pci_find_msi_chip_by_node(struct device_node *of_node) { return NULL }; +of_pci_find_msi_chip_by_node (struct device_node *of_node) {return NULL ; };#endif #endif
So why do we need a semi-colon after a closing brace? I can understand how the missing semi-colon after NULL would cause the compiler to flag an error, but all the other changes look unnecessary to me.
Thierry
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PATCH v8 4/10 of: pci: add registry of MSI chips
Quoted 45 lines · Thierry Reding
Quoted 44 lines · Jason Cooper
Quoted 15 lines · Benjamin Herrenschmidt
Review
Quoted 10 lines · Thomas Petazzoni
(quoted diff) +4
-0+#if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI) +int of_pci_msi_chip_add(struct msi_chip *chip); +void of_pci_msi_chip_remove(struct msi_chip *chip); +struct msi_chip *of_pci_find_msi_chip_by_node(struct device_node
*of_node);(quoted diff) +3
-1+#else +static inline int of_pci_msi_chip_add(struct msi_chip *chip) { return -EINVAL; } +static inline void of_pci_msi_chip_remove(struct msi_chip *chip) { }Missing a ; at the end of the above line... breaks the build of
CONFIG_PCI_MSIis not set.Quoted 6 lines
Review
Quoted 6 lines
(quoted diff) +2
-0+static inline struct msi_chip * +of_pci_find_msi_chip_by_node(struct device_node *of_node) { returnNULL };
(quoted diff) +2
-0+#endif + #endifReproduced, fixed and builds clean !CONFIG_OF and !CONFIG_PCI_MSI with:
---------------->8----------------
include/linux/of_pci.h +4
-3@@ -19,10 +19,11 @@ int of_pci_msi_chip_add(struct msi_chip *chip);void of_pci_msi_chip_remove (struct msi_chip *chip);struct msi_chip *of_pci_find_msi_chip_by_node (struct device_node *of_node);#else -static inline int of_pci_msi_chip_add (struct msi_chip *chip) {return -EINVAL ; } -static inline void of_pci_msi_chip_remove (struct msi_chip *chip) { } +static inline int +of_pci_msi_chip_add (struct msi_chip *chip) {return -EINVAL ; }; +static inline void of_pci_msi_chip_remove (struct msi_chip *chip) { };static inline struct msi_chip * -of_pci_find_msi_chip_by_node(struct device_node *of_node) { return NULL }; +of_pci_find_msi_chip_by_node (struct device_node *of_node) {return NULL ; };#endif
Quoted 5 lines
include/linux/of_pci.h int of_pci_msi_chip_add(struct msi_chip *chip); · line 29
Quoted 1 line
include/linux/of_pci.h +0
-0#endif So why do we need a semi-colon after a closing brace? I can understand how the missing semi-colon after NULL would cause the compiler to flag an error, but all the other changes look unnecessary to me.
You're correct, I sent this a little too hastily. I thought Ben knew something I didn't (see above), but the error was only where you indicated. I'm revising my fix to just append the semi-colon after the NULL.
thx,
Jason.
PATCH v8 4/10 of: pci: add registry of MSI chips
Quoted 6 lines · Jason Cooper
You're correct, I sent this a little too hastily. I thought Ben knew something I didn't (see above), but the error was only where you indicated. I'm revising my fix to just append the semi-colon after the
NULL.
I messed up in my reply, I was talking about the one after the NULL.
Cheers,
Ben.
PATCH v8 4/10 of: pci: add registry of MSI chips
In reply to Thomas PetazzoniQuoted 5 lines · Thomas Petazzoni
This commit adds a very basic registry of
msi_chipstructures, so that an IRQ controller driver can register anmsi_chip, and a PCIe host controller can find it, based on a 'structdevice_node'.Signed-off-by Thomas Petazzoni <[email protected]>
Quoted 100 lines
--- drivers/of/of_pci.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/msi.h | 2 ++ include/linux/of_pci.h | 12 ++++++++++++ 3 files changed, 59 insertions(+)drivers/of/of_pci.c +45
-0@@ -89,3 +89,48 @@ int of_pci_parse_bus_range(struct device_node *node, struct resource *res)return 0 ; }EXPORT_SYMBOL_GPL (of_pci_parse_bus_range); + +#ifdef CONFIG_PCI_MSI + +static LIST_HEAD (of_pci_msi_chip_list); +static DEFINE_MUTEX (of_pci_msi_chip_mutex); + +int of_pci_msi_chip_add (struct msi_chip *chip) +{ +if (!of_property_read_bool (chip->of_node,"msi-controller" )) +return -EINVAL ; + +mutex_lock (&of_pci_msi_chip_mutex); +list_add (&chip->list, &of_pci_msi_chip_list); +mutex_unlock (&of_pci_msi_chip_mutex); + +return 0 ; +} +EXPORT_SYMBOL_GPL (of_pci_msi_chip_add); + +void of_pci_msi_chip_remove (struct msi_chip *chip) +{ +mutex_lock (&of_pci_msi_chip_mutex); +list_del (&chip->list); +mutex_unlock (&of_pci_msi_chip_mutex); +} +EXPORT_SYMBOL_GPL (of_pci_msi_chip_remove); + +struct msi_chip *of_pci_find_msi_chip_by_node (struct device_node *of_node) +{ +struct msi_chip *c; + +mutex_lock (&of_pci_msi_chip_mutex); +list_for_each_entry (c, &of_pci_msi_chip_list, list) { +if (c->of_node == of_node) { +mutex_unlock (&of_pci_msi_chip_mutex); +return c; + } + } +mutex_unlock (&of_pci_msi_chip_mutex); + +return NULL ; +} +EXPORT_SYMBOL_GPL (of_pci_find_msi_chip_by_node); + +#endif /* CONFIG_PCI_MSI */ include/linux/msi.h +2
-0@@ -68,6 +68,8 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq);struct msi_chip {struct module *owner;struct device *dev; +struct device_node *of_node; +struct list_head list;int (*setup_irq)(struct msi_chip *chip,struct pci_dev *dev,struct msi_desc *desc);include/linux/of_pci.h +12
-0@@ -2,6 +2,7 @@#define __OF_PCI_H#include <linux/pci.h> +#include <linux/msi.h> struct pci_dev ;struct of_irq ;@@ -13,4 +14,15 @@ struct device_node *of_pci_find_child_device(struct device_node *parent,int of_pci_get_devfn (struct device_node *np);int of_pci_parse_bus_range (struct device_node *node,struct resource *res); +#if defined(CONFIG_OF ) && defined(CONFIG_PCI_MSI ) +int of_pci_msi_chip_add (struct msi_chip *chip); +void of_pci_msi_chip_remove (struct msi_chip *chip); +struct msi_chip *of_pci_find_msi_chip_by_node (struct device_node *of_node); +#else +static inline int of_pci_msi_chip_add (struct msi_chip *chip) {return -EINVAL ; } +static inline void of_pci_msi_chip_remove (struct msi_chip *chip) { } +static inline struct msi_chip * +of_pci_find_msi_chip_by_node(struct device_node *of_node) { return NULL }; +#endif +#endif
PATCH v8 5/10 irqchip: armada-370-xp: properly request resources
In reply to Thomas PetazzoniInstead of using of_iomap(), we now use of_address_to_resource(), request_mem_region() and ioremap(). This allows the corresponding I/O regions to be properly requested and visible in /proc/iomem.
The main motivation for this change is that the introduction of the MSI support requires us to get the physical address of the main interrupt controller registers, so we will need the corresponding 'struct resource' anyway.
We also take this opportunity to change a panic() to BUG_ON(), in order to be consistent with the rest of the driver.
--- drivers/irqchip/irq-armada-370-xp.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-)
drivers/irqchip/irq-armada-370-xp.c +16 -4
@@ -248,12 +248,25 @@ armada_370_xp_handle_irq(struct pt_regs *regs)static int __init armada_370_xp_mpic_of_init (struct device_node *node,struct device_node *parent) { +struct resource main_int_res, per_cpu_int_res;u32 control; - main_int_base =of_iomap (node,0 ); - per_cpu_int_base =of_iomap (node,1 ); +BUG_ON (of_address_to_resource (node,0 , &main_int_res)); +BUG_ON (of_address_to_resource (node,1 , &per_cpu_int_res)); +BUG_ON (!request_mem_region (main_int_res.start, +resource_size (&main_int_res), + node->full_name)); +BUG_ON (!request_mem_region (per_cpu_int_res.start, +resource_size (&per_cpu_int_res), + node->full_name)); + + main_int_base =ioremap (main_int_res.start, +resource_size (&main_int_res));BUG_ON (!main_int_base); + + per_cpu_int_base =ioremap (per_cpu_int_res.start, +resource_size (&per_cpu_int_res));BUG_ON (!per_cpu_int_base); control =readl (main_int_base +ARMADA_370_XP_INT_CONTROL );
@@ -262,8 +275,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,irq_domain_add_linear (node, (control >>2 ) &0x3ff , &armada_370_xp_mpic_irq_ops,NULL ); -if (!armada_370_xp_mpic_domain) -panic ("Unable to add Armada_370_Xp MPIC irq domain (DT)\n" ); +BUG_ON (!armada_370_xp_mpic_domain);irq_set_default_host (armada_370_xp_mpic_domain);
Signature · 1 line
1.8.1.2
PATCH v8 5/10 irqchip: armada-370-xp: properly request resources
Quoted 9 lines · Thomas Petazzoni
Instead of using
of_iomap(), we now useof_address_to_resource(),request_mem_region()andioremap(). This allows the corresponding I/O regions to be properly requested and visible in/proc/iomem.The main motivation for this change is that the introduction of the MSI support requires us to get the physical address of the main interrupt controller registers, so we will need the corresponding 'struct resource' anyway.
Quoted 5 lines
We also take this opportunity to change a
panic()toBUG_ON(), in order to be consistent with the rest of the driver.Signed-off-by Thomas Petazzoni <[email protected]>Tested-by Daniel Price <[email protected]>
Quoted 47 lines
--- drivers/irqchip/irq-armada-370-xp.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-)drivers/irqchip/irq-armada-370-xp.c +16
-4@@ -248,12 +248,25 @@ armada_370_xp_handle_irq(struct pt_regs *regs)static int __init armada_370_xp_mpic_of_init (struct device_node *node,struct device_node *parent) { +struct resource main_int_res, per_cpu_int_res;u32 control; - main_int_base =of_iomap (node,0 ); - per_cpu_int_base =of_iomap (node,1 ); +BUG_ON (of_address_to_resource (node,0 , &main_int_res)); +BUG_ON (of_address_to_resource (node,1 , &per_cpu_int_res)); +BUG_ON (!request_mem_region (main_int_res.start, +resource_size (&main_int_res), + node->full_name)); +BUG_ON (!request_mem_region (per_cpu_int_res.start, +resource_size (&per_cpu_int_res), + node->full_name)); + + main_int_base =ioremap (main_int_res.start, +resource_size (&main_int_res));BUG_ON (!main_int_base); + + per_cpu_int_base =ioremap (per_cpu_int_res.start, +resource_size (&per_cpu_int_res));BUG_ON (!per_cpu_int_base); control =readl (main_int_base +ARMADA_370_XP_INT_CONTROL );@@ -262,8 +275,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,irq_domain_add_linear (node, (control >>2 ) &0x3ff , &armada_370_xp_mpic_irq_ops,NULL ); -if (!armada_370_xp_mpic_domain) -panic ("Unable to add Armada_370_Xp MPIC irq domain (DT)\n" ); +BUG_ON (!armada_370_xp_mpic_domain);irq_set_default_host (armada_370_xp_mpic_domain);
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
PATCH v8 6/10 irqchip: armada-370-xp: implement MSI support
In reply to Thomas PetazzoniThis commit introduces the support for the MSI interrupts in the armada-370-xp interrupt controller driver. It registers an MSI chip to the MSI chip registry, which will be used by the Marvell PCIe host controller driver.
The MSI interrupts use the 16 high doorbells, and are therefore notified using IRQ1 of the main interrupt controller.
--- .../devicetree/bindings/arm/armada-370-xp-mpic.txt | 3 + drivers/irqchip/irq-armada-370-xp.c | 182 ++++++++++++++++++++- 2 files changed, 184 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt +3 -0
@@ -4,6 +4,8 @@ Marvell Armada 370 and Armada XP Interrupt Controller Required properties: - compatible: Should be "marvell,mpic" - interrupt-controller: Identifies the node as an interrupt controller. +- msi-controller: Identifies the node as an PCI Message Signaled + Interrupt controller. - #interrupt-cells: The number of cells to define the interrupts. Should be 1. The cell is the IRQ number
@@ -24,6 +26,7 @@ Example: #address-cells = <1>; #size-cells = <1>; interrupt-controller; + msi-controller; reg = <0xd0020a00 0x1d0>, <0xd0021070 0x58>; };
drivers/irqchip/irq-armada-370-xp.c +181 -1
224 lines not on this page · raw message
Signature · 1 line
1.8.1.2
PATCH v8 6/10 irqchip: armada-370-xp: implement MSI support
Quoted 7 lines · Thomas Petazzoni
This commit introduces the support for the MSI interrupts in the armada-370-xp interrupt controller driver. It registers an MSI chip to the MSI chip registry, which will be used by the Marvell PCIe host controller driver.
The MSI interrupts use the 16 high doorbells, and are therefore notified using IRQ1 of the main interrupt controller.
When you have a bit of time, have a look at
arch/powerpc/sysdev/msi_bitmap.c
This should be usable pretty-much as-is and thus could be moved to a generic place and replace your custom bitmap allocator.
Cheers,
Ben.
Quoted 260 lines
Signed-off-by Thomas Petazzoni <[email protected]>--- .../devicetree/bindings/arm/armada-370-xp-mpic.txt | 3 + drivers/irqchip/irq-armada-370-xp.c | 182 ++++++++++++++++++++- 2 files changed, 184 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt +3
-0@@ -4,6 +4,8 @@ Marvell Armada 370 and Armada XP Interrupt Controller Required properties: - compatible: Should be "marvell,mpic" - interrupt-controller: Identifies the node as an interrupt controller. +- msi-controller: Identifies the node as an PCI Message Signaled + Interrupt controller. - #interrupt-cells: The number of cells to define the interrupts. Should be 1. The cell is the IRQ number@@ -24,6 +26,7 @@ Example: #address-cells = <1>; #size-cells = <1>; interrupt-controller; + msi-controller; reg = <0xd0020a00 0x1d0>, <0xd0021070 0x58>; };drivers/irqchip/irq-armada-370-xp.c +181
-1@@ -21,7 +21,10 @@#include <linux/io.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/of_pci.h> #include <linux/irqdomain.h> +#include <linux/slab.h> +#include <linux/msi.h> #include <asm/mach/arch.h> #include <asm/exception.h> #include <asm/smp_plat.h> @@ -51,12 +54,22 @@#define IPI_DOORBELL_START (0)#define IPI_DOORBELL_END (8)#define IPI_DOORBELL_MASK 0xFF +#define PCI_MSI_DOORBELL_START (16) +#define PCI_MSI_DOORBELL_NR (16) +#define PCI_MSI_DOORBELL_END (32) +#define PCI_MSI_DOORBELL_MASK 0xFFFF0000static DEFINE_RAW_SPINLOCK (irq_controller_lock);static void __iomem *per_cpu_int_base;static void __iomem *main_int_base;static struct irq_domain *armada_370_xp_mpic_domain; +#ifdef CONFIG_PCI_MSI +static struct irq_domain *armada_370_xp_msi_domain; +static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR); +static DEFINE_MUTEX (msi_used_lock); +static phys_addr_t msi_doorbell_addr; +#endif /* * In SMP mode: @@ -87,6 +100,144 @@ static void armada_370_xp_irq_unmask(struct irq_data *d) ARMADA_370_XP_INT_CLEAR_MASK_OFFS); } +#ifdef CONFIG_PCI_MSI + +static int armada_370_xp_alloc_msi (void ) +{ +int hwirq; + +mutex_lock (&msi_used_lock); + hwirq =find_first_zero_bit (&msi_used,PCI_MSI_DOORBELL_NR ); +if (hwirq >=PCI_MSI_DOORBELL_NR ) + hwirq = -ENOSPC ; +else +set_bit (hwirq, msi_used); +mutex_unlock (&msi_used_lock); + +return hwirq; +} + +static void armada_370_xp_free_msi (int hwirq) +{ +mutex_lock (&msi_used_lock); +if (!test_bit (hwirq, msi_used)) +pr_err ("trying to free unused MSI#%d\n" , hwirq); +else +clear_bit (hwirq, msi_used); +mutex_unlock (&msi_used_lock); +} + +static int armada_370_xp_setup_msi_irq (struct msi_chip *chip, +struct pci_dev *pdev, +struct msi_desc *desc) +{ +struct msi_msg msg; +irq_hw_number_t hwirq; +int virq; + + hwirq =armada_370_xp_alloc_msi (); +if (hwirq <0 ) +return hwirq; + + virq =irq_create_mapping (armada_370_xp_msi_domain, hwirq); +if (!virq) { +armada_370_xp_free_msi (hwirq); +return -EINVAL ; + } + +irq_set_msi_desc (virq, desc); + + msg.address_lo = msi_doorbell_addr; + msg.address_hi =0 ; + msg.data =0xf00 | (hwirq +16 ); + +write_msi_msg (virq, &msg); +return 0 ; +} + +static void armada_370_xp_teardown_msi_irq (struct msi_chip *chip, +unsigned int irq) +{ +struct irq_data *d =irq_get_irq_data (irq); +irq_dispose_mapping (irq); +armada_370_xp_free_msi (d->hwirq); +} + +static struct irq_chip armada_370_xp_msi_irq_chip = { + .name ="armada_370_xp_msi_irq" , + .irq_enable = unmask_msi_irq, + .irq_disable = mask_msi_irq, + .irq_mask = mask_msi_irq, + .irq_unmask = unmask_msi_irq, +}; + +static int armada_370_xp_msi_map (struct irq_domain *domain,unsigned int virq, +irq_hw_number_t hw) +{ +irq_set_chip_and_handler (virq, &armada_370_xp_msi_irq_chip, + handle_simple_irq); +set_irq_flags (virq,IRQF_VALID ); + +return 0 ; +} + +static const struct irq_domain_ops armada_370_xp_msi_irq_ops = { + .map = armada_370_xp_msi_map, +}; + +static int armada_370_xp_msi_init (struct device_node *node, +phys_addr_t main_int_phys_base) +{ +struct msi_chip *msi_chip; +u32 reg; +int ret; + + msi_doorbell_addr = main_int_phys_base + +ARMADA_370_XP_SW_TRIG_INT_OFFS ; + + msi_chip =kzalloc (sizeof (*msi_chip),GFP_KERNEL ); +if (!msi_chip) +return -ENOMEM ; + + msi_chip->setup_irq = armada_370_xp_setup_msi_irq; + msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq; + msi_chip->of_node = node; + + armada_370_xp_msi_domain = +irq_domain_add_linear (NULL ,PCI_MSI_DOORBELL_NR , + &armada_370_xp_msi_irq_ops, +NULL ); +if (!armada_370_xp_msi_domain) { +kfree (msi_chip); +return -ENOMEM ; + } + + ret =of_pci_msi_chip_add (msi_chip); +if (ret <0 ) { +irq_domain_remove (armada_370_xp_msi_domain); +kfree (msi_chip); +return ret; + } + + reg =readl (per_cpu_int_base +ARMADA_370_XP_IN_DRBEL_MSK_OFFS ) + |PCI_MSI_DOORBELL_MASK ; + +writel (reg, per_cpu_int_base + +ARMADA_370_XP_IN_DRBEL_MSK_OFFS ); + +/* Unmask IPI interrupt */ +writel (1 , per_cpu_int_base +ARMADA_370_XP_INT_CLEAR_MASK_OFFS ); + +return 0 ; +} +#else +static inline int armada_370_xp_msi_init (struct device_node *node, +phys_addr_t main_int_phys_base) +{ +return 0 ; +} +#endif +#ifdef CONFIG_SMP static int armada_xp_set_affinity (struct irq_data *d,const struct cpumask *mask_val,bool force)@@ -214,12 +365,39 @@ armada_370_xp_handle_irq(struct pt_regs *regs)if (irqnr >1022 )break ; -if (irqnr >0 ) { +if (irqnr >1 ) { irqnr =irq_find_mapping (armada_370_xp_mpic_domain, irqnr);handle_IRQ (irqnr, regs);continue ; } + +#ifdef CONFIG_PCI_MSI +/* MSI handling */ +if (irqnr ==1 ) { +u32 msimask, msinr; + + msimask =readl_relaxed (per_cpu_int_base + +ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS ) + &PCI_MSI_DOORBELL_MASK ; + +writel (~PCI_MSI_DOORBELL_MASK , per_cpu_int_base + +ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS ); + +for (msinr =PCI_MSI_DOORBELL_START ; + msinr <PCI_MSI_DOORBELL_END ; msinr++) { +int irq; + +if (!(msimask &BIT (msinr))) +continue ; + + irq =irq_find_mapping (armada_370_xp_msi_domain, + msinr -16 ); +handle_IRQ (irq, regs); + } + } +#endif +#ifdef CONFIG_SMP /* IPI Handling */ if (irqnr ==0 ) {@@ -292,6 +470,8 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,#endif +armada_370_xp_msi_init (node, main_int_res.start); +set_handle_irq (armada_370_xp_handle_irq);return 0 ;
PATCH v8 6/10 irqchip: armada-370-xp: implement MSI support
In reply to Thomas PetazzoniQuoted 9 lines · Thomas Petazzoni
This commit introduces the support for the MSI interrupts in the armada-370-xp interrupt controller driver. It registers an MSI chip to the MSI chip registry, which will be used by the Marvell PCIe host controller driver.
The MSI interrupts use the 16 high doorbells, and are therefore notified using IRQ1 of the main interrupt controller.
Signed-off-by Thomas Petazzoni <[email protected]>
Quoted 260 lines
--- .../devicetree/bindings/arm/armada-370-xp-mpic.txt | 3 + drivers/irqchip/irq-armada-370-xp.c | 182 ++++++++++++++++++++- 2 files changed, 184 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt +3
-0@@ -4,6 +4,8 @@ Marvell Armada 370 and Armada XP Interrupt Controller Required properties: - compatible: Should be "marvell,mpic" - interrupt-controller: Identifies the node as an interrupt controller. +- msi-controller: Identifies the node as an PCI Message Signaled + Interrupt controller. - #interrupt-cells: The number of cells to define the interrupts. Should be 1. The cell is the IRQ number@@ -24,6 +26,7 @@ Example: #address-cells = <1>; #size-cells = <1>; interrupt-controller; + msi-controller; reg = <0xd0020a00 0x1d0>, <0xd0021070 0x58>; };drivers/irqchip/irq-armada-370-xp.c +181
-1@@ -21,7 +21,10 @@#include <linux/io.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/of_pci.h> #include <linux/irqdomain.h> +#include <linux/slab.h> +#include <linux/msi.h> #include <asm/mach/arch.h> #include <asm/exception.h> #include <asm/smp_plat.h> @@ -51,12 +54,22 @@#define IPI_DOORBELL_START (0)#define IPI_DOORBELL_END (8)#define IPI_DOORBELL_MASK 0xFF +#define PCI_MSI_DOORBELL_START (16) +#define PCI_MSI_DOORBELL_NR (16) +#define PCI_MSI_DOORBELL_END (32) +#define PCI_MSI_DOORBELL_MASK 0xFFFF0000static DEFINE_RAW_SPINLOCK (irq_controller_lock);static void __iomem *per_cpu_int_base;static void __iomem *main_int_base;static struct irq_domain *armada_370_xp_mpic_domain; +#ifdef CONFIG_PCI_MSI +static struct irq_domain *armada_370_xp_msi_domain; +static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR); +static DEFINE_MUTEX (msi_used_lock); +static phys_addr_t msi_doorbell_addr; +#endif /* * In SMP mode: @@ -87,6 +100,144 @@ static void armada_370_xp_irq_unmask(struct irq_data *d) ARMADA_370_XP_INT_CLEAR_MASK_OFFS); } +#ifdef CONFIG_PCI_MSI + +static int armada_370_xp_alloc_msi (void ) +{ +int hwirq; + +mutex_lock (&msi_used_lock); + hwirq =find_first_zero_bit (&msi_used,PCI_MSI_DOORBELL_NR ); +if (hwirq >=PCI_MSI_DOORBELL_NR ) + hwirq = -ENOSPC ; +else +set_bit (hwirq, msi_used); +mutex_unlock (&msi_used_lock); + +return hwirq; +} + +static void armada_370_xp_free_msi (int hwirq) +{ +mutex_lock (&msi_used_lock); +if (!test_bit (hwirq, msi_used)) +pr_err ("trying to free unused MSI#%d\n" , hwirq); +else +clear_bit (hwirq, msi_used); +mutex_unlock (&msi_used_lock); +} + +static int armada_370_xp_setup_msi_irq (struct msi_chip *chip, +struct pci_dev *pdev, +struct msi_desc *desc) +{ +struct msi_msg msg; +irq_hw_number_t hwirq; +int virq; + + hwirq =armada_370_xp_alloc_msi (); +if (hwirq <0 ) +return hwirq; + + virq =irq_create_mapping (armada_370_xp_msi_domain, hwirq); +if (!virq) { +armada_370_xp_free_msi (hwirq); +return -EINVAL ; + } + +irq_set_msi_desc (virq, desc); + + msg.address_lo = msi_doorbell_addr; + msg.address_hi =0 ; + msg.data =0xf00 | (hwirq +16 ); + +write_msi_msg (virq, &msg); +return 0 ; +} + +static void armada_370_xp_teardown_msi_irq (struct msi_chip *chip, +unsigned int irq) +{ +struct irq_data *d =irq_get_irq_data (irq); +irq_dispose_mapping (irq); +armada_370_xp_free_msi (d->hwirq); +} + +static struct irq_chip armada_370_xp_msi_irq_chip = { + .name ="armada_370_xp_msi_irq" , + .irq_enable = unmask_msi_irq, + .irq_disable = mask_msi_irq, + .irq_mask = mask_msi_irq, + .irq_unmask = unmask_msi_irq, +}; + +static int armada_370_xp_msi_map (struct irq_domain *domain,unsigned int virq, +irq_hw_number_t hw) +{ +irq_set_chip_and_handler (virq, &armada_370_xp_msi_irq_chip, + handle_simple_irq); +set_irq_flags (virq,IRQF_VALID ); + +return 0 ; +} + +static const struct irq_domain_ops armada_370_xp_msi_irq_ops = { + .map = armada_370_xp_msi_map, +}; + +static int armada_370_xp_msi_init (struct device_node *node, +phys_addr_t main_int_phys_base) +{ +struct msi_chip *msi_chip; +u32 reg; +int ret; + + msi_doorbell_addr = main_int_phys_base + +ARMADA_370_XP_SW_TRIG_INT_OFFS ; + + msi_chip =kzalloc (sizeof (*msi_chip),GFP_KERNEL ); +if (!msi_chip) +return -ENOMEM ; + + msi_chip->setup_irq = armada_370_xp_setup_msi_irq; + msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq; + msi_chip->of_node = node; + + armada_370_xp_msi_domain = +irq_domain_add_linear (NULL ,PCI_MSI_DOORBELL_NR , + &armada_370_xp_msi_irq_ops, +NULL ); +if (!armada_370_xp_msi_domain) { +kfree (msi_chip); +return -ENOMEM ; + } + + ret =of_pci_msi_chip_add (msi_chip); +if (ret <0 ) { +irq_domain_remove (armada_370_xp_msi_domain); +kfree (msi_chip); +return ret; + } + + reg =readl (per_cpu_int_base +ARMADA_370_XP_IN_DRBEL_MSK_OFFS ) + |PCI_MSI_DOORBELL_MASK ; + +writel (reg, per_cpu_int_base + +ARMADA_370_XP_IN_DRBEL_MSK_OFFS ); + +/* Unmask IPI interrupt */ +writel (1 , per_cpu_int_base +ARMADA_370_XP_INT_CLEAR_MASK_OFFS ); + +return 0 ; +} +#else +static inline int armada_370_xp_msi_init (struct device_node *node, +phys_addr_t main_int_phys_base) +{ +return 0 ; +} +#endif +#ifdef CONFIG_SMP static int armada_xp_set_affinity (struct irq_data *d,const struct cpumask *mask_val,bool force)@@ -214,12 +365,39 @@ armada_370_xp_handle_irq(struct pt_regs *regs)if (irqnr >1022 )break ; -if (irqnr >0 ) { +if (irqnr >1 ) { irqnr =irq_find_mapping (armada_370_xp_mpic_domain, irqnr);handle_IRQ (irqnr, regs);continue ; } + +#ifdef CONFIG_PCI_MSI +/* MSI handling */ +if (irqnr ==1 ) { +u32 msimask, msinr; + + msimask =readl_relaxed (per_cpu_int_base + +ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS ) + &PCI_MSI_DOORBELL_MASK ; + +writel (~PCI_MSI_DOORBELL_MASK , per_cpu_int_base + +ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS ); + +for (msinr =PCI_MSI_DOORBELL_START ; + msinr <PCI_MSI_DOORBELL_END ; msinr++) { +int irq; + +if (!(msimask &BIT (msinr))) +continue ; + + irq =irq_find_mapping (armada_370_xp_msi_domain, + msinr -16 ); +handle_IRQ (irq, regs); + } + } +#endif +#ifdef CONFIG_SMP /* IPI Handling */ if (irqnr ==0 ) {@@ -292,6 +470,8 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,#endif +armada_370_xp_msi_init (node, main_int_res.start); +set_handle_irq (armada_370_xp_handle_irq);return 0 ;
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
PATCH v8 7/10 ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pci
In reply to Thomas PetazzoniSome PCI drivers may need to adjust the pci_bus structure after it has been allocated by the Linux PCI core. The PCI core allows architectures to implement the pcibios_add_bus() and pcibios_remove_bus() for this purpose. This commit therefore extends the hw_pci and pci_sys_data structures of the ARM PCI core to allow PCI drivers to register ->add_bus() and ->remove_bus() in hw_pci, which will get called when a bus is added or removed from the system.
This will be used for example by the Marvell PCIe driver to connect a particular PCI bus with its corresponding MSI chip to handle Message Signaled Interrupts.
--- arch/arm/include/asm/mach/pci.h | 4 ++++ arch/arm/kernel/bios32.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+)
arch/arm/include/asm/mach/pci.h +4 -0
@@ -36,6 +36,8 @@ struct hw_pci {resource_size_t start, resource_size_t size, resource_size_t align); +void (*add_bus)(struct pci_bus *bus); +void (*remove_bus)(struct pci_bus *bus); };/*
@@ -63,6 +65,8 @@ struct pci_sys_data {resource_size_t start, resource_size_t size, resource_size_t align); +void (*add_bus)(struct pci_bus *bus); +void (*remove_bus)(struct pci_bus *bus);void *private_data;/* platform controller private data */ };
arch/arm/kernel/bios32.c +16 -0
@@ -363,6 +363,20 @@ void pcibios_fixup_bus(struct pci_bus *bus) }EXPORT_SYMBOL (pcibios_fixup_bus); +void pcibios_add_bus (struct pci_bus *bus) +{ +struct pci_sys_data *sys = bus->sysdata; +if (sys->add_bus) + sys->add_bus (bus); +} + +void pcibios_remove_bus (struct pci_bus *bus) +{ +struct pci_sys_data *sys = bus->sysdata; +if (sys->remove_bus) + sys->remove_bus (bus); +} +/* * Swizzle the device pin each time we cross a bridge. If a platform does * not provide a swizzle function, we perform the standard PCI swizzling.
@@ -464,6 +478,8 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, sys->swizzle = hw->swizzle; sys->map_irq = hw->map_irq; sys->align_resource = hw->align_resource; + sys->add_bus = hw->add_bus; + sys->remove_bus = hw->remove_bus;INIT_LIST_HEAD (&sys->resources);if (hw->private_data)
Signature · 1 line
1.8.1.2
PATCH v8 8/10 ARM: mvebu: the MPIC now provides MSI controller features
In reply to Thomas PetazzoniAdds the 'msi-controller' property to the main interrupt controller Device Tree node, to indicate that it can now behave as a MSI controller.
--- arch/arm/boot/dts/armada-370-xp.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm/boot/dts/armada-370-xp.dtsi +1 -0
@@ -56,6 +56,7 @@ #interrupt-cells = <1>; #size-cells = <1>; interrupt-controller; + msi-controller; }; coherency-fabric at 20200 {
Signature · 1 line
1.8.1.2
PATCH v8 8/10 ARM: mvebu: the MPIC now provides MSI controller features
Quoted 7 lines · Thomas Petazzoni
Adds the 'msi-controller' property to the main interrupt controller Device Tree node, to indicate that it can now behave as a MSI controller.
Signed-off-by Thomas Petazzoni <[email protected]>Reviewed-by Thierry Reding <[email protected]>Tested-by Daniel Price <[email protected]>
Quoted 17 lines
--- arch/arm/boot/dts/armada-370-xp.dtsi | 1 + 1 file changed, 1 insertion(+)arch/arm/boot/dts/armada-370-xp.dtsi +1
-0@@ -56,6 +56,7 @@ #interrupt-cells = <1>; #size-cells = <1>; interrupt-controller; + msi-controller; }; coherency-fabric at 20200 {
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
PATCH v8 9/10 PCI: mvebu: add support for MSI
In reply to Thomas PetazzoniThis commit adds support for Message Signaled Interrupts in the Marvell PCIe host controller. The work is very simple: it simply gets a reference to the msi_chip associated to the PCIe controller thanks to the msi-parent DT property, and stores this reference in the pci_bus structure. This is enough to let the Linux PCI core use the functions of msi_chip to setup and teardown MSIs.
--- .../devicetree/bindings/pci/mvebu-pci.txt | 3 +++ drivers/pci/host/pci-mvebu.c | 26 ++++++++++++++++++++++ 2 files changed, 29 insertions(+)
Documentation/devicetree/bindings/pci/mvebu-pci.txt +3 -0
@@ -12,6 +12,8 @@ Mandatory properties: - device_type, set to "pci" - ranges: ranges for the PCI memory and I/O regions, as well as the MMIO registers to control the PCIe interfaces. +- msi-parent: Link to the hardware entity that serves as the Message + Signaled Interrupt controller for this PCI controller. In addition, the Device Tree node must have sub-nodes describing each PCIe interface, having the following mandatory properties:
@@ -46,6 +48,7 @@ pcie-controller { #size-cells = <2>; bus-range = <0x00 0xff>; + msi-parent = <&mpic>; ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
drivers/pci/host/pci-mvebu.c +26 -0
@@ -11,6 +11,7 @@#include <linux/clk.h> #include <linux/module.h> #include <linux/mbus.h> +#include <linux/msi.h> #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/of_address.h>
@@ -107,6 +108,7 @@ struct mvebu_pcie_port;struct mvebu_pcie {struct platform_device *pdev;struct mvebu_pcie_port *ports; +struct msi_chip *msi;struct resource io;struct resource realio;struct resource mem;
@@ -695,6 +697,12 @@ static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)return bus; } +void mvebu_pcie_add_bus (struct pci_bus *bus) +{ +struct mvebu_pcie *pcie =sys_to_pcie (bus->sysdata); + bus->msi = pcie->msi; +} + resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, const struct resource *res, resource_size_t start,
@@ -731,6 +739,7 @@ static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie) hw.map_irq = mvebu_pcie_map_irq; hw.ops = &mvebu_pcie_ops; hw.align_resource = mvebu_pcie_align_resource; + hw.add_bus = mvebu_pcie_add_bus;pci_common_init (&hw); }
@@ -755,6 +764,21 @@ mvebu_pcie_map_registers(struct platform_device *pdev,return devm_request_and_ioremap (&pdev->dev, ®s); } +static void __init mvebu_pcie_msi_enable (struct mvebu_pcie *pcie) +{ +struct device_node *msi_node; + + msi_node =of_parse_phandle (pcie->pdev->dev.of_node, +"msi-parent" ,0 ); +if (!msi_node) +return ; + + pcie->msi =of_pci_find_msi_chip_by_node (msi_node); + +if (pcie->msi) + pcie->msi->dev = &pcie->pdev->dev; +} +static int __init mvebu_pcie_probe (struct platform_device *pdev) {struct mvebu_pcie *pcie;
@@ -879,6 +903,8 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev) i++; } +mvebu_pcie_msi_enable (pcie); +mvebu_pcie_enable (pcie);return 0 ;
Signature · 1 line
1.8.1.2
PATCH v8 10/10 ARM: mvebu: link PCIe controllers to the MSI controller
In reply to Thomas PetazzoniThis commit adjusts the Armada 370 and Armada XP PCIe controllers Device Tree informations to reference their MSI controller. In the case of this platform, the MSI controller is implemented by the MPIC.
--- arch/arm/boot/dts/armada-370.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 1 + 4 files changed, 4 insertions(+)
arch/arm/boot/dts/armada-370.dtsi +1 -0
@@ -178,6 +178,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
arch/arm/boot/dts/armada-xp-mv78230.dtsi +1 -0
@@ -91,6 +91,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
arch/arm/boot/dts/armada-xp-mv78260.dtsi +1 -0
@@ -111,6 +111,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
arch/arm/boot/dts/armada-xp-mv78460.dtsi +1 -0
@@ -127,6 +127,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
Signature · 1 line
1.8.1.2
PATCH v8 10/10 ARM: mvebu: link PCIe controllers to the MSI controller
Quoted 6 lines · Thomas Petazzoni
This commit adjusts the Armada 370 and Armada XP PCIe controllers Device Tree informations to reference their MSI controller. In the case of this platform, the MSI controller is implemented by the MPIC.
Signed-off-by Thomas Petazzoni <[email protected]>Tested-by Daniel Price <[email protected]>
Quoted 56 lines
--- arch/arm/boot/dts/armada-370.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 1 + 4 files changed, 4 insertions(+)arch/arm/boot/dts/armada-370.dtsi +1
-0@@ -178,6 +178,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */arch/arm/boot/dts/armada-xp-mv78230.dtsi +1
-0@@ -91,6 +91,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */arch/arm/boot/dts/armada-xp-mv78260.dtsi +1
-0@@ -111,6 +111,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */arch/arm/boot/dts/armada-xp-mv78460.dtsi +1
-0@@ -127,6 +127,7 @@ #address-cells = <3>; #size-cells = <2>; + msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
Signature · 4 lines
Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
v8 cover MSI support for Marvell EBU PCIe driver
In reply to Thomas PetazzoniQuoted 6 lines · Thomas Petazzoni
Hello,
This set of patches introduces Message Signaled Interrupt support in the Marvell EBU PCIe driver. It has been successfully tested on the Armada XP GP platform with an Intel e1000e PCIe network card that supports MSI.
Appart from the build breakage when not using CONFIG_PCI_MSI which I reported in a previous email, I'm fine with the series. No need to add my acks to all of the ARM specific stuff.
Cheers,
Ben.