mmc: dw_mmc-exynos: Common bindings for dw-mshc timing
Subsystems (4)
PATCH 1/1 mmc: dw_mmc-exynos: Common bindings for dw-mshc timing
From: Dinh Nguyen <[email protected]>
Remove the "samsung" in "samsung,dw-mshc-ciu-div", "samsung,dw-mshc-sdr-timing", and "samsung,dw-mshc-ddr-timing". These characteristics are not applicable to just Samsung platforms, but to any platform that uses the Synopsis SD/MMC IP.
Signed-off-by Dinh Nguyen <[email protected]>
CC Arnd Bergmann <[email protected]>
Cc Olof Johansson <[email protected]>
Cc Jaehoon Chung <[email protected]>
Cc Seungwon Jeon <[email protected]>
Cc Rob Herring <[email protected]>
Cc Pawel Moll <[email protected]>
Cc Mark Rutland <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Ian Campbell <[email protected]>
--- .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 30 -------------------- .../devicetree/bindings/mmc/synopsis-dw-mshc.txt | 29 +++++++++++++++++++ arch/arm/boot/dts/cros5250-common.dtsi | 18 ++++++------ arch/arm/boot/dts/exynos4412-odroidx.dts | 6 ++-- arch/arm/boot/dts/exynos4412-origen.dts | 6 ++-- arch/arm/boot/dts/exynos5250-arndale.dts | 12 ++++---- arch/arm/boot/dts/exynos5250-smdk5250.dts | 12 ++++---- drivers/mmc/host/dw_mmc-exynos.c | 6 ++-- 8 files changed, 59 insertions(+), 60 deletions(-)
Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +0 -30
@@ -17,33 +17,6 @@ Required Properties: - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 specific extensions. -* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface - unit (ciu) clock. This property is applicable only for Exynos5 SoC's and - ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7. - -* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for single - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - -* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for double - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - - Notes for the sdr-timing and ddr-timing values: - - The order of the cells should be - - First Cell: CIU clock phase shift value for tx mode. - - Second Cell: CIU clock phase shift value for rx mode. - - Valid values for SDR and DDR CIU clock timing for Exynos5250: - - valid value for tx phase shift and rx phase shift is 0 to 7. - - when CIU clock divider value is set to 3, all possible 8 phase shift - values can be used. - - if CIU clock divider value is 0 (that is divide by 1), both tx and rx - phase shift clocks should be 0. - Required properties for a slot: * gpios: specifies a list of gpios used for command, clock and data bus. The
@@ -71,9 +44,6 @@ Example: broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>;
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +29 -0
@@ -71,6 +71,32 @@ Optional properties: * vmmc-supply: The phandle to the regulator to use for vmmc. If this is specified we'll defer probe until we can find this regulator. +* dw-mshc-ciu-div: Specifies the divider value for the card interface + unit (ciu) clock. The valid range of divider value is 0 to 7. + +* dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value + in transmit mode and CIU clock phase shift value in receive mode for single + data rate mode operation. Refer notes below for the order of the cells and the + valid values. + +* dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value + in transmit mode and CIU clock phase shift value in receive mode for double + data rate mode operation. Refer notes below for the order of the cells and the + valid values. + + Notes for the sdr-timing and ddr-timing values: + + The order of the cells should be + - First Cell: CIU clock phase shift value for tx mode. + - Second Cell: CIU clock phase shift value for rx mode. + + Valid values for SDR and DDR CIU clock timing for Exynos5250: + - valid value for tx phase shift and rx phase shift is 0 to 7. + - when CIU clock divider value is set to 3, all possible 8 phase shift + values can be used. + - if CIU clock divider value is 0 (that is divide by 1), both tx and rx + phase shift clocks should be 0. + Aliases: - All the MSHC controller nodes should be represented in the aliases node using
@@ -99,6 +125,9 @@ board specific portions as listed below. fifo-depth = <0x80>; card-detect-delay = <200>; vmmc-supply = <&buck8>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>;
arch/arm/boot/dts/cros5250-common.dtsi +9 -9
@@ -235,9 +235,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
@@ -256,9 +256,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
@@ -275,9 +275,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; /* See board-specific dts files for pin setup */ slot@0 {
arch/arm/boot/dts/exynos4412-odroidx.dts +3 -3
@@ -51,9 +51,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>;
arch/arm/boot/dts/exynos4412-origen.dts +3 -3
@@ -122,9 +122,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>;
arch/arm/boot/dts/exynos5250-arndale.dts +6 -6
@@ -324,9 +324,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
@@ -346,9 +346,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
arch/arm/boot/dts/exynos5250-smdk5250.dts +6 -6
@@ -146,9 +146,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
@@ -167,9 +167,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
drivers/mmc/host/dw_mmc-exynos.c +3 -3
@@ -131,18 +131,18 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)u32 div =0 ;int ret; -of_property_read_u32 (np,"samsung,dw-mshc-ciu-div" , &div); +of_property_read_u32 (np,"dw-mshc-ciu-div" , &div); priv->ciu_div = div; ret =of_property_read_u32_array (np, -"samsung,dw-mshc-sdr-timing" , timing,2 ); +"dw-mshc-sdr-timing" , timing,2 );if (ret)return ret; priv->sdr_timing =SDMMC_CLKSEL_TIMING (timing[0 ], timing[1 ], div); ret =of_property_read_u32_array (np, -"samsung,dw-mshc-ddr-timing" , timing,2 ); +"dw-mshc-ddr-timing" , timing,2 );if (ret)return ret;
Signature · 1 line
1.7.9.5
Jaehoon Chung
maintainerPATCH 1/1 mmc: dw_mmc-exynos: Common bindings for dw-mshc timing
Hi Dinh
Quoted 96 lines · On 08/09/2013 07:55 AM, [email protected] wrote:
From: Dinh Nguyen <[email protected]>
Remove the "samsung" in "samsung,dw-mshc-ciu-div", "samsung,dw-mshc-sdr-timing", and "samsung,dw-mshc-ddr-timing". These characteristics are not applicable to just Samsung platforms, but to any platform that uses the Synopsis SD/MMC IP.
Signed-off-by Dinh Nguyen <[email protected]>CC Arnd Bergmann <[email protected]>Cc Olof Johansson <[email protected]>Cc Jaehoon Chung <[email protected]>Cc Seungwon Jeon <[email protected]>Cc Rob Herring <[email protected]>Cc Pawel Moll <[email protected]>Cc Mark Rutland <[email protected]>Cc Stephen Warren <[email protected]>Cc Ian Campbell <[email protected]>--- .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 30 -------------------- .../devicetree/bindings/mmc/synopsis-dw-mshc.txt | 29 +++++++++++++++++++ arch/arm/boot/dts/cros5250-common.dtsi | 18 ++++++------ arch/arm/boot/dts/exynos4412-odroidx.dts | 6 ++-- arch/arm/boot/dts/exynos4412-origen.dts | 6 ++-- arch/arm/boot/dts/exynos5250-arndale.dts | 12 ++++---- arch/arm/boot/dts/exynos5250-smdk5250.dts | 12 ++++---- drivers/mmc/host/dw_mmc-exynos.c | 6 ++-- 8 files changed, 59 insertions(+), 60 deletions(-)Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +0
-30@@ -17,33 +17,6 @@ Required Properties: - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 specific extensions. -* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface - unit (ciu) clock. This property is applicable only for Exynos5 SoC's and - ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7. - -* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for single - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - -* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for double - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - - Notes for the sdr-timing and ddr-timing values: - - The order of the cells should be - - First Cell: CIU clock phase shift value for tx mode. - - Second Cell: CIU clock phase shift value for rx mode. - - Valid values for SDR and DDR CIU clock timing for Exynos5250: - - valid value for tx phase shift and rx phase shift is 0 to 7. - - when CIU clock divider value is set to 3, all possible 8 phase shift - values can be used. - - if CIU clock divider value is 0 (that is divide by 1), both tx and rx - phase shift clocks should be 0. - Required properties for a slot: * gpios: specifies a list of gpios used for command, clock and data bus. The@@ -71,9 +44,6 @@ Example: broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>;Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +10
-0@@ -71,6 +71,32 @@ Optional properties: * vmmc-supply: The phandle to the regulator to use for vmmc. If this is specified we'll defer probe until we can find this regulator. +* dw-mshc-ciu-div: Specifies the divider value for the card interface + unit (ciu) clock. The valid range of divider value is 0 to 7. + +* dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value + in transmit mode and CIU clock phase shift value in receive mode for single + data rate mode operation. Refer notes below for the order of the cells and the + valid values. + +* dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value + in transmit mode and CIU clock phase shift value in receive mode for double
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt Optional properties: · line 93
Quoted 10 lines
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +10
-0+ data rate mode operation. Refer notes below for the order of the cells and the + valid values. + + Notes for the sdr-timing and ddr-timing values: + + The order of the cells should be + - First Cell: CIU clock phase shift value for tx mode. + - Second Cell: CIU clock phase shift value for rx mode. + + Valid values for SDR and DDR CIU clock timing for Exynos5250:
Exynos5250? Maybe It should be mentioned common SoC.
Quoted 171 lines
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +9
-0+ - valid value for tx phase shift and rx phase shift is 0 to 7. + - when CIU clock divider value is set to 3, all possible 8 phase shift + values can be used. + - if CIU clock divider value is 0 (that is divide by 1), both tx and rx + phase shift clocks should be 0. + Aliases: - All the MSHC controller nodes should be represented in the aliases node using@@ -99,6 +125,9 @@ board specific portions as listed below. fifo-depth = <0x80>; card-detect-delay = <200>; vmmc-supply = <&buck8>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>;arch/arm/boot/dts/cros5250-common.dtsi +9
-9@@ -235,9 +235,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;@@ -256,9 +256,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;@@ -275,9 +275,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; /* See board-specific dts files for pin setup */ slot@0 {arch/arm/boot/dts/exynos4412-odroidx.dts +3
-3@@ -51,9 +51,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>;arch/arm/boot/dts/exynos4412-origen.dts +3
-3@@ -122,9 +122,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>;arch/arm/boot/dts/exynos5250-arndale.dts +6
-6@@ -324,9 +324,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;@@ -346,9 +346,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;arch/arm/boot/dts/exynos5250-smdk5250.dts +6
-6@@ -146,9 +146,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;@@ -167,9 +167,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;drivers/mmc/host/dw_mmc-exynos.c +2
-2@@ -131,18 +131,18 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)u32 div =0 ;int ret; -of_property_read_u32 (np,"samsung,dw-mshc-ciu-div" , &div); +of_property_read_u32 (np,"dw-mshc-ciu-div" , &div); priv->ciu_div = div; ret =of_property_read_u32_array (np, -"samsung,dw-mshc-sdr-timing" , timing,2 ); +"dw-mshc-sdr-timing" , timing,2 );
drivers/mmc/host/dw_mmc-exynos.c static int dw_mci_exynos_parse_dt(struct dw_mci *host) · line 147
Quoted 10 lines
drivers/mmc/host/dw_mmc-exynos.c +1
-1if (ret)return ret; priv->sdr_timing =SDMMC_CLKSEL_TIMING (timing[0 ], timing[1 ], div); ret =of_property_read_u32_array (np, -"samsung,dw-mshc-ddr-timing" , timing,2 ); +"dw-mshc-ddr-timing" , timing,2 );if (ret)return ret;
Then we can move functions related with clksel from dw-mmc-exynos.c to dw-mmc.c, isn't it?
Best Regards,
Jaehoon Chung
Quoted 2 lines
PATCH 1/1 mmc: dw_mmc-exynos: Common bindings for dw-mshc timing
Quoted 9 lines · Jaehoon Chung
Hi Dinh
Quoted 6 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
Remove the "samsung" in "samsung,dw-mshc-ciu-div", "samsung,dw-mshc-sdr-timing", and "samsung,dw-mshc-ddr-timing". These characteristics are not applicable to just Samsung platforms, but to any platform that uses the Synopsis SD/MMC IP.
Though host controller based on Synopsys is required to implement clock phase shift, actual implementation could be different. I'm not sure that this above parameters are common just now. But if some more host controllers are introduced, we may define clearly.
Thanks,
Seungwon Jeon
Quoted 295 lines
Quoted 24 lines
Signed-off-by Dinh Nguyen <[email protected]>CC Arnd Bergmann <[email protected]>Cc Olof Johansson <[email protected]>Cc Jaehoon Chung <[email protected]>Cc Seungwon Jeon <[email protected]>Cc Rob Herring <[email protected]>Cc Pawel Moll <[email protected]>Cc Mark Rutland <[email protected]>Cc Stephen Warren <[email protected]>Cc Ian Campbell <[email protected]>Cc devicetree at vger.kernel.orgCc linux-mmc at vger.kernel.orgCC linux-arm-kernel at lists.infradead.org--- .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 30 -------------------- .../devicetree/bindings/mmc/synopsis-dw-mshc.txt | 29 +++++++++++++++++++ arch/arm/boot/dts/cros5250-common.dtsi | 18 ++++++------ arch/arm/boot/dts/exynos4412-odroidx.dts | 6 ++-- arch/arm/boot/dts/exynos4412-origen.dts | 6 ++-- arch/arm/boot/dts/exynos5250-arndale.dts | 12 ++++---- arch/arm/boot/dts/exynos5250-smdk5250.dts | 12 ++++---- drivers/mmc/host/dw_mmc-exynos.c | 6 ++-- 8 files changed, 59 insertions(+), 60 deletions(-)Review
Quoted 1 line
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-0
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txtReview
Quoted 48 lines
index 6d1c098..ddb1d95 100644
Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +0
-30@@ -17,33 +17,6 @@ Required Properties: - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 specific extensions. -* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface - unit (ciu) clock. This property is applicable only for Exynos5 SoC's and - ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7. - -* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for single - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - -* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for double - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - - Notes for the sdr-timing and ddr-timing values: - - The order of the cells should be - - First Cell: CIU clock phase shift value for tx mode. - - Second Cell: CIU clock phase shift value for rx mode. - - Valid values for SDR and DDR CIU clock timing for Exynos5250: - - valid value for tx phase shift and rx phase shift is 0 to 7. - - when CIU clock divider value is set to 3, all possible 8 phase shift - values can be used. - - if CIU clock divider value is 0 (that is divide by 1), both tx and rx - phase shift clocks should be 0. - Required properties for a slot: * gpios: specifies a list of gpios used for command, clock and data bus. The@@ -71,9 +44,6 @@ Example: broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; slot at 0 { reg = <0>;(quoted diff) +0
-0
b/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txtQuoted 17 lines
index cdcebea..cf85a8c 100644
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +10
-0@@ -71,6 +71,32 @@ Optional properties: * vmmc-supply: The phandle to the regulator to use for vmmc. If this is specified we'll defer probe until we can find this regulator. +* dw-mshc-ciu-div: Specifies the divider value for the card interface + unit (ciu) clock. The valid range of divider value is 0 to 7. + +* dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value + in transmit mode and CIU clock phase shift value in receive mode for single + data rate mode operation. Refer notes below for the order of the cells and the + valid values. + +* dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value + in transmit mode and CIU clock phase shift value in receive mode for doubleDocumentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt Optional properties: · line 93
Quoted 10 lines
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +10
-0+ data rate mode operation. Refer notes below for the order of the cells and the + valid values. + + Notes for the sdr-timing and ddr-timing values: + + The order of the cells should be + - First Cell: CIU clock phase shift value for tx mode. + - Second Cell: CIU clock phase shift value for rx mode. + + Valid values for SDR and DDR CIU clock timing for Exynos5250:Exynos5250? Maybe It should be mentioned common SoC.
Quoted 171 lines
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +9
-0+ - valid value for tx phase shift and rx phase shift is 0 to 7. + - when CIU clock divider value is set to 3, all possible 8 phase shift + values can be used. + - if CIU clock divider value is 0 (that is divide by 1), both tx and rx + phase shift clocks should be 0. + Aliases: - All the MSHC controller nodes should be represented in the aliases node using@@ -99,6 +125,9 @@ board specific portions as listed below. fifo-depth = <0x80>; card-detect-delay = <200>; vmmc-supply = <&buck8>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot at 0 { reg = <0>;arch/arm/boot/dts/cros5250-common.dtsi +9
-9@@ -235,9 +235,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;@@ -256,9 +256,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;@@ -275,9 +275,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; /* See board-specific dts files for pin setup */ slot at 0 {arch/arm/boot/dts/exynos4412-odroidx.dts +3
-3@@ -51,9 +51,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot at 0 { reg = <0>;arch/arm/boot/dts/exynos4412-origen.dts +3
-3@@ -122,9 +122,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot at 0 { reg = <0>;arch/arm/boot/dts/exynos5250-arndale.dts +6
-6@@ -324,9 +324,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;@@ -346,9 +346,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;arch/arm/boot/dts/exynos5250-smdk5250.dts +6
-6@@ -146,9 +146,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;@@ -167,9 +167,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;drivers/mmc/host/dw_mmc-exynos.c +2
-2@@ -131,18 +131,18 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)u32 div =0 ;int ret; -of_property_read_u32 (np,"samsung,dw-mshc-ciu-div" , &div); +of_property_read_u32 (np,"dw-mshc-ciu-div" , &div); priv->ciu_div = div; ret =of_property_read_u32_array (np, -"samsung,dw-mshc-sdr-timing" , timing,2 ); +"dw-mshc-sdr-timing" , timing,2 );drivers/mmc/host/dw_mmc-exynos.c static int dw_mci_exynos_parse_dt(struct dw_mci *host) · line 147
Quoted 10 lines
drivers/mmc/host/dw_mmc-exynos.c +1
-1if (ret)return ret; priv->sdr_timing =SDMMC_CLKSEL_TIMING (timing[0 ], timing[1 ], div); ret =of_property_read_u32_array (np, -"samsung,dw-mshc-ddr-timing" , timing,2 ); +"dw-mshc-ddr-timing" , timing,2 );if (ret)return ret;Then we can move functions related with clksel from
dw-mmc-exynos.ctodw-mmc.c, isn't it?Best Regards,
Jaehoon ChungQuoted 2 lines
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PATCH 1/1 mmc: dw_mmc-exynos: Common bindings for dw-mshc timing
Hi Seungwon Jeon,
Quoted 6 lines · Seungwon Jeon
Quoted 5 lines · Jaehoon Chung
Hi Dinh
Quoted 2 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
Quoted 7 lines
Quoted 4 lines
Quoted 4 lines
Remove the "samsung" in "samsung,dw-mshc-ciu-div", "samsung,dw-mshc-sdr-timing", and "samsung,dw-mshc-ddr-timing". These characteristics are not applicable to just Samsung platforms, but to any platform that uses the Synopsis SD/MMC IP.
Though host controller based on Synopsys is required to implement clock phase shift, actual implementation could be different. I'm not sure that this above parameters are common just now. But if some more host controllers are introduced, we may define clearly.
But the bindings can be common between socfpga and exynos right? The values in the bindings represent the same thing, just the implementation for the clock phase shift can be different.
Thanks,
Dinh
Quoted 301 lines
Thanks,
Seungwon JeonQuoted 295 lines
Quoted 24 lines
Signed-off-by Dinh Nguyen <[email protected]>CC Arnd Bergmann <[email protected]>Cc Olof Johansson <[email protected]>Cc Jaehoon Chung <[email protected]>Cc Seungwon Jeon <[email protected]>Cc Rob Herring <[email protected]>Cc Pawel Moll <[email protected]>Cc Mark Rutland <[email protected]>Cc Stephen Warren <[email protected]>Cc Ian Campbell <[email protected]>Cc devicetree at vger.kernel.orgCc linux-mmc at vger.kernel.orgCC linux-arm-kernel at lists.infradead.org--- .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 30 -------------------- .../devicetree/bindings/mmc/synopsis-dw-mshc.txt | 29 +++++++++++++++++++ arch/arm/boot/dts/cros5250-common.dtsi | 18 ++++++------ arch/arm/boot/dts/exynos4412-odroidx.dts | 6 ++-- arch/arm/boot/dts/exynos4412-origen.dts | 6 ++-- arch/arm/boot/dts/exynos5250-arndale.dts | 12 ++++---- arch/arm/boot/dts/exynos5250-smdk5250.dts | 12 ++++---- drivers/mmc/host/dw_mmc-exynos.c | 6 ++-- 8 files changed, 59 insertions(+), 60 deletions(-)Review
Quoted 1 line
(quoted diff) +0
-0
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txtReview
Quoted 48 lines
index 6d1c098..ddb1d95 100644
Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +0
-30@@ -17,33 +17,6 @@ Required Properties: - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 specific extensions. -* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface - unit (ciu) clock. This property is applicable only for Exynos5 SoC's and - ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7. - -* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for single - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - -* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for double - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - - Notes for the sdr-timing and ddr-timing values: - - The order of the cells should be - - First Cell: CIU clock phase shift value for tx mode. - - Second Cell: CIU clock phase shift value for rx mode. - - Valid values for SDR and DDR CIU clock timing for Exynos5250: - - valid value for tx phase shift and rx phase shift is 0 to 7. - - when CIU clock divider value is set to 3, all possible 8 phase shift - values can be used. - - if CIU clock divider value is 0 (that is divide by 1), both tx and rx - phase shift clocks should be 0. - Required properties for a slot: * gpios: specifies a list of gpios used for command, clock and data bus. The@@ -71,9 +44,6 @@ Example: broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; slot at 0 { reg = <0>;(quoted diff) +0
-0
b/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txtQuoted 17 lines
index cdcebea..cf85a8c 100644
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +10
-0@@ -71,6 +71,32 @@ Optional properties: * vmmc-supply: The phandle to the regulator to use for vmmc. If this is specified we'll defer probe until we can find this regulator. +* dw-mshc-ciu-div: Specifies the divider value for the card interface + unit (ciu) clock. The valid range of divider value is 0 to 7. + +* dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value + in transmit mode and CIU clock phase shift value in receive mode for single + data rate mode operation. Refer notes below for the order of the cells and the + valid values. + +* dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value + in transmit mode and CIU clock phase shift value in receive mode for doubleDocumentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt Optional properties: · line 93
Quoted 10 lines
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +10
-0+ data rate mode operation. Refer notes below for the order of the cells and the + valid values. + + Notes for the sdr-timing and ddr-timing values: + + The order of the cells should be + - First Cell: CIU clock phase shift value for tx mode. + - Second Cell: CIU clock phase shift value for rx mode. + + Valid values for SDR and DDR CIU clock timing for Exynos5250:Exynos5250? Maybe It should be mentioned common SoC.
Quoted 171 lines
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +9
-0+ - valid value for tx phase shift and rx phase shift is 0 to 7. + - when CIU clock divider value is set to 3, all possible 8 phase shift + values can be used. + - if CIU clock divider value is 0 (that is divide by 1), both tx and rx + phase shift clocks should be 0. + Aliases: - All the MSHC controller nodes should be represented in the aliases node using@@ -99,6 +125,9 @@ board specific portions as listed below. fifo-depth = <0x80>; card-detect-delay = <200>; vmmc-supply = <&buck8>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot at 0 { reg = <0>;arch/arm/boot/dts/cros5250-common.dtsi +9
-9@@ -235,9 +235,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;@@ -256,9 +256,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;@@ -275,9 +275,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; /* See board-specific dts files for pin setup */ slot at 0 {arch/arm/boot/dts/exynos4412-odroidx.dts +3
-3@@ -51,9 +51,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot at 0 { reg = <0>;arch/arm/boot/dts/exynos4412-origen.dts +3
-3@@ -122,9 +122,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot at 0 { reg = <0>;arch/arm/boot/dts/exynos5250-arndale.dts +6
-6@@ -324,9 +324,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;@@ -346,9 +346,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;arch/arm/boot/dts/exynos5250-smdk5250.dts +6
-6@@ -146,9 +146,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;@@ -167,9 +167,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;drivers/mmc/host/dw_mmc-exynos.c +2
-2@@ -131,18 +131,18 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)u32 div =0 ;int ret; -of_property_read_u32 (np,"samsung,dw-mshc-ciu-div" , &div); +of_property_read_u32 (np,"dw-mshc-ciu-div" , &div); priv->ciu_div = div; ret =of_property_read_u32_array (np, -"samsung,dw-mshc-sdr-timing" , timing,2 ); +"dw-mshc-sdr-timing" , timing,2 );drivers/mmc/host/dw_mmc-exynos.c static int dw_mci_exynos_parse_dt(struct dw_mci *host) · line 147
Quoted 10 lines
drivers/mmc/host/dw_mmc-exynos.c +1
-1if (ret)return ret; priv->sdr_timing =SDMMC_CLKSEL_TIMING (timing[0 ], timing[1 ], div); ret =of_property_read_u32_array (np, -"samsung,dw-mshc-ddr-timing" , timing,2 ); +"dw-mshc-ddr-timing" , timing,2 );if (ret)return ret;Then we can move functions related with clksel from
dw-mmc-exynos.ctodw-mmc.c, isn't it?Best Regards,
Jaehoon ChungQuoted 2 lines
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PATCH 1/1 mmc: dw_mmc-exynos: Common bindings for dw-mshc timing
Quoted 13 lines · Dinh Nguyen
Hi Seungwon Jeon,
Quoted 10 lines · Seungwon Jeon
Quoted 9 lines · Jaehoon Chung
Hi Dinh
Quoted 6 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
Remove the "samsung" in "samsung,dw-mshc-ciu-div", "samsung,dw-mshc-sdr-timing", and "samsung,dw-mshc-ddr-timing". These characteristics are not applicable to just Samsung platforms, but to any platform that uses the Synopsis SD/MMC IP.
Quoted 8 lines
Quoted 2 lines
Though host controller based on Synopsys is required to implement clock phase shift, actual implementation could be different. I'm not sure that this above parameters are common just
now.
Quoted 1 line
But if some more host controllers are introduced, we may define clearly.
But the bindings can be common between socfpga and exynos right? The values in the bindings represent the same thing, just the implementation for the clock phase shift can be different.
Hmm. I also feel like similar though I didn't see the socfpga. As I take a glance, div of socfpga currently seems fixed in host side. Do you need it from dts?
How about rockchip's mshc platform?
I guess we could wait and see more.
Thanks,
Seungwon Jeon
PATCH 1/1 mmc: dw_mmc-exynos: Common bindings for dw-mshc timing
In reply to Jaehoon ChungQuoted 284 lines · Jaehoon Chung
Hi Dinh
Quoted 96 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
Remove the "samsung" in "samsung,dw-mshc-ciu-div", "samsung,dw-mshc-sdr-timing", and "samsung,dw-mshc-ddr-timing". These characteristics are not applicable to just Samsung platforms, but to any platform that uses the Synopsis SD/MMC IP.
Signed-off-by Dinh Nguyen <[email protected]>CC Arnd Bergmann <[email protected]>Cc Olof Johansson <[email protected]>Cc Jaehoon Chung <[email protected]>Cc Seungwon Jeon <[email protected]>Cc Rob Herring <[email protected]>Cc Pawel Moll <[email protected]>Cc Mark Rutland <[email protected]>Cc Stephen Warren <[email protected]>Cc Ian Campbell <[email protected]>Cc devicetree at vger.kernel.orgCc linux-mmc at vger.kernel.orgCC linux-arm-kernel at lists.infradead.org--- .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 30 -------------------- .../devicetree/bindings/mmc/synopsis-dw-mshc.txt | 29 +++++++++++++++++++ arch/arm/boot/dts/cros5250-common.dtsi | 18 ++++++------ arch/arm/boot/dts/exynos4412-odroidx.dts | 6 ++-- arch/arm/boot/dts/exynos4412-origen.dts | 6 ++-- arch/arm/boot/dts/exynos5250-arndale.dts | 12 ++++---- arch/arm/boot/dts/exynos5250-smdk5250.dts | 12 ++++---- drivers/mmc/host/dw_mmc-exynos.c | 6 ++-- 8 files changed, 59 insertions(+), 60 deletions(-)Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +0
-30@@ -17,33 +17,6 @@ Required Properties: - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 specific extensions. -* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface - unit (ciu) clock. This property is applicable only for Exynos5 SoC's and - ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7. - -* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for single - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - -* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for double - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - - Notes for the sdr-timing and ddr-timing values: - - The order of the cells should be - - First Cell: CIU clock phase shift value for tx mode. - - Second Cell: CIU clock phase shift value for rx mode. - - Valid values for SDR and DDR CIU clock timing for Exynos5250: - - valid value for tx phase shift and rx phase shift is 0 to 7. - - when CIU clock divider value is set to 3, all possible 8 phase shift - values can be used. - - if CIU clock divider value is 0 (that is divide by 1), both tx and rx - phase shift clocks should be 0. - Required properties for a slot: * gpios: specifies a list of gpios used for command, clock and data bus. The@@ -71,9 +44,6 @@ Example: broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; slot at 0 { reg = <0>;Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +10
-0@@ -71,6 +71,32 @@ Optional properties: * vmmc-supply: The phandle to the regulator to use for vmmc. If this is specified we'll defer probe until we can find this regulator. +* dw-mshc-ciu-div: Specifies the divider value for the card interface + unit (ciu) clock. The valid range of divider value is 0 to 7. + +* dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value + in transmit mode and CIU clock phase shift value in receive mode for single + data rate mode operation. Refer notes below for the order of the cells and the + valid values. + +* dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value + in transmit mode and CIU clock phase shift value in receive mode for doubleDocumentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt Optional properties: · line 93
Quoted 10 lines
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +10
-0+ data rate mode operation. Refer notes below for the order of the cells and the + valid values. + + Notes for the sdr-timing and ddr-timing values: + + The order of the cells should be + - First Cell: CIU clock phase shift value for tx mode. + - Second Cell: CIU clock phase shift value for rx mode. + + Valid values for SDR and DDR CIU clock timing for Exynos5250:Exynos5250? Maybe It should be mentioned common SoC.
Quoted 174 lines
Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +9
-0+ - valid value for tx phase shift and rx phase shift is 0 to 7. + - when CIU clock divider value is set to 3, all possible 8 phase shift + values can be used. + - if CIU clock divider value is 0 (that is divide by 1), both tx and rx + phase shift clocks should be 0. + Aliases: - All the MSHC controller nodes should be represented in the aliases node using@@ -99,6 +125,9 @@ board specific portions as listed below. fifo-depth = <0x80>; card-detect-delay = <200>; vmmc-supply = <&buck8>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot at 0 { reg = <0>;arch/arm/boot/dts/cros5250-common.dtsi +9
-9@@ -235,9 +235,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;@@ -256,9 +256,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;@@ -275,9 +275,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; /* See board-specific dts files for pin setup */ slot at 0 {arch/arm/boot/dts/exynos4412-odroidx.dts +3
-3@@ -51,9 +51,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot at 0 { reg = <0>;arch/arm/boot/dts/exynos4412-origen.dts +3
-3@@ -122,9 +122,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot at 0 { reg = <0>;arch/arm/boot/dts/exynos5250-arndale.dts +6
-6@@ -324,9 +324,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;@@ -346,9 +346,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;arch/arm/boot/dts/exynos5250-smdk5250.dts +6
-6@@ -146,9 +146,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;@@ -167,9 +167,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;drivers/mmc/host/dw_mmc-exynos.c +2
-2@@ -131,18 +131,18 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)u32 div =0 ;int ret; -of_property_read_u32 (np,"samsung,dw-mshc-ciu-div" , &div); +of_property_read_u32 (np,"dw-mshc-ciu-div" , &div); priv->ciu_div = div; ret =of_property_read_u32_array (np, -"samsung,dw-mshc-sdr-timing" , timing,2 ); +"dw-mshc-sdr-timing" , timing,2 );if (ret)return ret;
Quoted 8 lines
drivers/mmc/host/dw_mmc-exynos.c static int dw_mci_exynos_parse_dt(struct dw_mci *host) · line 147
Quoted 7 lines
drivers/mmc/host/dw_mmc-exynos.c +1
-1priv->sdr_timing =SDMMC_CLKSEL_TIMING (timing[0 ], timing[1 ], div); ret =of_property_read_u32_array (np, -"samsung,dw-mshc-ddr-timing" , timing,2 ); +"dw-mshc-ddr-timing" , timing,2 );if (ret)return ret;Then we can move functions related with clksel from
dw-mmc-exynos.ctodw-mmc.c, isn't it?
I think so, but I figure we can agree on some common bindings for the Exynos and SoCFPGA platforms first?
Thanks,
Dinh
Quoted 7 lines
Best Regards,
Jaehoon ChungQuoted 2 lines
PATCH 1/1 mmc: dw_mmc-exynos: Common bindings for dw-mshc timing
In reply to dinguyen at altera.comQuoted 5 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
Remove the "samsung" in "samsung,dw-mshc-ciu-div", "samsung,dw-mshc-sdr-timing", and "samsung,dw-mshc-ddr-timing". These characteristics are not applicable to just Samsung platforms, but to any platform that uses the Synopsis SD/MMC IP.
But the properties aren't globally standard; they apply specifically anywhere that this particular Synopsis IP is present. As such, I think at least a "synopsis," prefix is warranted.
And the driver should probably support both the old and new property names for backwards-compatibility?
PATCH 1/1 mmc: dw_mmc-exynos: Common bindings for dw-mshc timing
Quoted 10 lines · Stephen Warren
Quoted 5 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
Remove the "samsung" in "samsung,dw-mshc-ciu-div", "samsung,dw-mshc-sdr-timing", and "samsung,dw-mshc-ddr-timing". These characteristics are not applicable to just Samsung platforms, but to any platform that uses the Synopsis SD/MMC IP.
But the properties aren't globally standard; they apply specifically anywhere that this particular Synopsis IP is present. As such, I think at least a "synopsis," prefix is warranted.
A prefix is only really needed when a vendor is making a vendor-specific extension on a shared binding. Since the whole binding is synopsis-specific, I don't think there's need for a prefix here.
Quoted 2 lines
And the driver should probably support both the old and new property names for backwards-compatibility?
Yes, that sounds appropriate if the binding is considered stable and otherwise good.
The alternative is to have everybody just use the samsung,* properties. There's nothing wrong with that per se, besides the fact that if it had been caught when creating the binding, there should have been no prefix and the properties should have been common.
-Olof
PATCH 1/1 mmc: dw_mmc-exynos: Common bindings for dw-mshc timing
Quoted 8 lines · Olof Johansson
Quoted 7 lines · Stephen Warren
Quoted 5 lines · dinguyen at altera.com
From: Dinh Nguyen <[email protected]>
Remove the "samsung" in "samsung,dw-mshc-ciu-div", "samsung,dw-mshc-sdr-timing", and "samsung,dw-mshc-ddr-timing". These characteristics are not applicable to just Samsung platforms, but to any platform that uses the Synopsis SD/MMC IP.
Quoted 7 lines
Quoted 3 lines
But the properties aren't globally standard; they apply specifically anywhere that this particular Synopsis IP is present. As such, I think at least a "synopsis," prefix is warranted.
A prefix is only really needed when a vendor is making a vendor-specific extension on a shared binding. Since the whole binding is synopsis-specific, I don't think there's need for a prefix here.
Oh! That definitely isn't the rule that's been applied before; I've been asked to add "nvidia," prefixes to properties in entirely custom bindings...