Netlogic updates for 3.12

PATCH Superseded Jayachandran C 1 participant 13 messages Aug 11, 2013 – Aug 21, 2013 MIPS

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Jayachandran C

author

2013-08-11 09:14 UTC #0 lore raw

cover Netlogic updates for 3.12

The main update is adding support for XLP 2XX SoCs
https://www.broadcom.com/products/Processors/Data-Center/XLP200-Series

The first few patches are minor updates.

JC.

Ganesan Ramalingam (4):
MIPS: Netlogic: XLP2XX CPU and PIC frequency
MIPS: Netlogic: XLP2xx update for I2C controller
MIPS: Netlogic: Add support for USB on XLP2xx
MIPS: Netlogic: built-in DTB for XLP2xx SoC boards

Jayachandran C (6):
MIPS: Netlogic: Read memory from DRAM BARs
MIPS: Netlogic: Remove memory section from built-in DT
MIPS: Netlogic: Fix DT flash size parameter
MIPS: Netlogic: Add support for XLP2XX
MIPS: Netlogic: Call xlp_mmu_init on all threads
MIPS: Netlogic: Core wakeup changes for XLP2XX

 arch/mips/include/asm/cpu.h                     |    1 +
 arch/mips/include/asm/netlogic/xlp-hal/bridge.h |    4 +
 arch/mips/include/asm/netlogic/xlp-hal/iomap.h  |   10 +
 arch/mips/include/asm/netlogic/xlp-hal/pic.h    |    5 +-
 arch/mips/include/asm/netlogic/xlp-hal/sys.h    |   31 +++
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h    |   17 ++
 arch/mips/include/asm/netlogic/xlr/pic.h        |    2 +
 arch/mips/kernel/cpu-probe.c                    |    5 +
 arch/mips/netlogic/Kconfig                      |    9 +
 arch/mips/netlogic/common/smp.c                 |    4 +-
 arch/mips/netlogic/common/time.c                |    3 +-
 arch/mips/netlogic/dts/Makefile                 |    1 +
 arch/mips/netlogic/dts/xlp_evp.dts              |    9 +-
 arch/mips/netlogic/dts/xlp_fvp.dts              |  118 +++++++++++
 arch/mips/netlogic/dts/xlp_svp.dts              |    9 +-
 arch/mips/netlogic/xlp/Makefile                 |    1 +
 arch/mips/netlogic/xlp/dt.c                     |    8 +-
 arch/mips/netlogic/xlp/nlm_hal.c                |  237 +++++++++++++++++++----
 arch/mips/netlogic/xlp/setup.c                  |   50 ++++-
 arch/mips/netlogic/xlp/usb-init-xlp2.c          |  218 +++++++++++++++++++++
 arch/mips/netlogic/xlp/usb-init.c               |    3 +
 arch/mips/netlogic/xlp/wakeup.c                 |   10 +-
 22 files changed, 686 insertions(+), 69 deletions(-)
 create mode 100644 arch/mips/netlogic/dts/xlp_fvp.dts
 create mode 100644 arch/mips/netlogic/xlp/usb-init-xlp2.c

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-08-11 09:18 UTC #1 lore raw

PATCH 1/10 MIPS: Netlogic: Read memory from DRAM BARs

Read the memory from the Bridge DRAM BARs if it is not passed in from the device tree. This will allow us to remove memory configuration from built in device trees.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/netlogic/xlp-hal/bridge.h |    4 +++
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h    |    3 ++
 arch/mips/netlogic/xlp/nlm_hal.c                |   35 +++++++++++++++++++++++
 arch/mips/netlogic/xlp/setup.c                  |   23 +++++++++++++++
 4 files changed, 65 insertions(+)

arch/mips/include/asm/netlogic/xlp-hal/bridge.h +4 -0

index 790f0f1..4e8eacb 100644
@@ -88,6 +88,7 @@
 #define BRIDGE_DRAM_LIMIT6		0x22
 #define BRIDGE_DRAM_LIMIT7		0x23
 
+#define BRIDGE_DRAM_NODE_TRANSLN(i)	(0x24 + (i))
 #define BRIDGE_DRAM_NODE_TRANSLN0	0x24
 #define BRIDGE_DRAM_NODE_TRANSLN1	0x25
 #define BRIDGE_DRAM_NODE_TRANSLN2	0x26

@@ -96,6 +97,8 @@
 #define BRIDGE_DRAM_NODE_TRANSLN5	0x29
 #define BRIDGE_DRAM_NODE_TRANSLN6	0x2a
 #define BRIDGE_DRAM_NODE_TRANSLN7	0x2b
+
+#define BRIDGE_DRAM_CHNL_TRANSLN(i)	(0x2c + (i))
 #define BRIDGE_DRAM_CHNL_TRANSLN0	0x2c
 #define BRIDGE_DRAM_CHNL_TRANSLN1	0x2d
 #define BRIDGE_DRAM_CHNL_TRANSLN2	0x2e

@@ -104,6 +107,7 @@
 #define BRIDGE_DRAM_CHNL_TRANSLN5	0x31
 #define BRIDGE_DRAM_CHNL_TRANSLN6	0x32
 #define BRIDGE_DRAM_CHNL_TRANSLN7	0x33
+
 #define BRIDGE_PCIEMEM_BASE0		0x34
 #define BRIDGE_PCIEMEM_BASE1		0x35
 #define BRIDGE_PCIEMEM_BASE2		0x36

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +3 -0

index f4ea0f7..d59cdd6 100644
@@ -59,6 +59,9 @@ void xlp_wakeup_secondary_cpus(void);
 
 void xlp_mmu_init(void);
 void nlm_hal_init(void);
+int xlp_get_dram_map(int n, uint64_t *dram_map);
+
+/* Device tree related */
 void *xlp_dt_init(void *fdtp);
 
 #endif /* !__ASSEMBLY__ */

arch/mips/netlogic/xlp/nlm_hal.c +35 -0

index 87560e4..6f2c210 100644
@@ -44,6 +44,7 @@
 #include <asm/netlogic/haldefs.h>
 #include <asm/netlogic/xlp-hal/iomap.h>
 #include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/bridge.h>
 #include <asm/netlogic/xlp-hal/pic.h>
 #include <asm/netlogic/xlp-hal/sys.h>

@@ -142,3 +143,37 @@ unsigned int nlm_get_cpu_frequency(void)
 {
 	return nlm_get_core_frequency(0, 0);
 }
+
+/*
+ * Fills upto 8 pairs of entries containing the DRAM map of a node
+ * if n < 0, get dram map for all nodes
+ */
+int xlp_get_dram_map(int n, uint64_t *dram_map)
+{
+	uint64_t bridgebase, base, lim;
+	uint32_t val;
+	int i, node, rv;
+
+	/* Look only at mapping on Node 0, we don't handle crazy configs */
+	bridgebase = nlm_get_bridge_regbase(0);
+	rv = 0;
+	for (i = 0; i < 8; i++) {
+		val = nlm_read_bridge_reg(bridgebase,
+					BRIDGE_DRAM_NODE_TRANSLN(i));
+		node = (val >> 1) & 0x3;
+		if (n >= 0 && n != node)
+			continue;
+		val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
+		val = (val >>  12) & 0xfffff;
+		base = (uint64_t) val << 20;
+		val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
+		val = (val >>  12) & 0xfffff;
+		if (val == 0)   /* BAR not used */
+			continue;
+		lim = ((uint64_t)val + 1) << 20;
+		dram_map[rv] = base;
+		dram_map[rv + 1] = lim;
+		rv += 2;
+	}
+	return rv;
+}

arch/mips/netlogic/xlp/setup.c +23 -0

index 7b638f7..0c6e300 100644
@@ -73,6 +73,23 @@ static void nlm_fixup_mem(void)
 	}
 }
 
+static void __int xlp_init_mem_from_bars(void)
+{
+	uint64_t map[16];
+	int i, n;
+
+	n = xlp_get_dram_map(-1, map);	/* -1: info for all nodes */
+	for (i = 0; i < n; i += 2) {
+		/* exclude 0x1000_0000-0x2000_0000, u-boot device */
+		if (map[i] <= 0x10000000 && map[i+1] > 0x10000000)
+			map[i+1] = 0x10000000;
+		if (map[i] > 0x10000000 && map[i] < 0x20000000)
+			map[i] = 0x20000000;
+
+		add_memory_region(map[i], map[i+1] - map[i], BOOT_MEM_RAM);
+	}
+}
+
 void __init plat_mem_setup(void)
 {
 	panic_timeout	= 5;

@@ -82,6 +99,12 @@ void __init plat_mem_setup(void)
 
 	/* memory and bootargs from DT */
 	early_init_devtree(initial_boot_params);
+
+	if (boot_mem_map.nr_map == 0) {
+		pr_info("Using DRAM BARs for memory map.\n");
+		xlp_init_mem_from_bars();
+	}
+	/* Calculate and setup wired entries for mapped kernel */
 	nlm_fixup_mem();
 }

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-08-21 14:00 UTC #2 lore raw

PATCH v2 1/10 MIPS: Netlogic: Read memory from DRAM BARs

Read the memory from the Bridge DRAM BARs, if it is not passed in from the device tree. This will allow us to remove memory configuration from built in device trees.

Signed-off-by Jayachandran C <[email protected]>

---
[Updated to fix a deleted character in the patch, which caused a compile error]

 arch/mips/include/asm/netlogic/xlp-hal/bridge.h |    4 +++
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h    |    3 ++
 arch/mips/netlogic/xlp/nlm_hal.c                |   35 +++++++++++++++++++++++
 arch/mips/netlogic/xlp/setup.c                  |   23 +++++++++++++++
 4 files changed, 65 insertions(+)

arch/mips/include/asm/netlogic/xlp-hal/bridge.h +4 -0

index 790f0f1..4e8eacb 100644
@@ -88,6 +88,7 @@
 #define BRIDGE_DRAM_LIMIT6		0x22
 #define BRIDGE_DRAM_LIMIT7		0x23
 
+#define BRIDGE_DRAM_NODE_TRANSLN(i)	(0x24 + (i))
 #define BRIDGE_DRAM_NODE_TRANSLN0	0x24
 #define BRIDGE_DRAM_NODE_TRANSLN1	0x25
 #define BRIDGE_DRAM_NODE_TRANSLN2	0x26

@@ -96,6 +97,8 @@
 #define BRIDGE_DRAM_NODE_TRANSLN5	0x29
 #define BRIDGE_DRAM_NODE_TRANSLN6	0x2a
 #define BRIDGE_DRAM_NODE_TRANSLN7	0x2b
+
+#define BRIDGE_DRAM_CHNL_TRANSLN(i)	(0x2c + (i))
 #define BRIDGE_DRAM_CHNL_TRANSLN0	0x2c
 #define BRIDGE_DRAM_CHNL_TRANSLN1	0x2d
 #define BRIDGE_DRAM_CHNL_TRANSLN2	0x2e

@@ -104,6 +107,7 @@
 #define BRIDGE_DRAM_CHNL_TRANSLN5	0x31
 #define BRIDGE_DRAM_CHNL_TRANSLN6	0x32
 #define BRIDGE_DRAM_CHNL_TRANSLN7	0x33
+
 #define BRIDGE_PCIEMEM_BASE0		0x34
 #define BRIDGE_PCIEMEM_BASE1		0x35
 #define BRIDGE_PCIEMEM_BASE2		0x36

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +3 -0

index f4ea0f7..d59cdd6 100644
@@ -59,6 +59,9 @@ void xlp_wakeup_secondary_cpus(void);
 
 void xlp_mmu_init(void);
 void nlm_hal_init(void);
+int xlp_get_dram_map(int n, uint64_t *dram_map);
+
+/* Device tree related */
 void *xlp_dt_init(void *fdtp);
 
 #endif /* !__ASSEMBLY__ */

arch/mips/netlogic/xlp/nlm_hal.c +35 -0

index 87560e4..6f2c210 100644
@@ -44,6 +44,7 @@
 #include <asm/netlogic/haldefs.h>
 #include <asm/netlogic/xlp-hal/iomap.h>
 #include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/bridge.h>
 #include <asm/netlogic/xlp-hal/pic.h>
 #include <asm/netlogic/xlp-hal/sys.h>

@@ -142,3 +143,37 @@ unsigned int nlm_get_cpu_frequency(void)
 {
 	return nlm_get_core_frequency(0, 0);
 }
+
+/*
+ * Fills upto 8 pairs of entries containing the DRAM map of a node
+ * if n < 0, get dram map for all nodes
+ */
+int xlp_get_dram_map(int n, uint64_t *dram_map)
+{
+	uint64_t bridgebase, base, lim;
+	uint32_t val;
+	int i, node, rv;
+
+	/* Look only at mapping on Node 0, we don't handle crazy configs */
+	bridgebase = nlm_get_bridge_regbase(0);
+	rv = 0;
+	for (i = 0; i < 8; i++) {
+		val = nlm_read_bridge_reg(bridgebase,
+					BRIDGE_DRAM_NODE_TRANSLN(i));
+		node = (val >> 1) & 0x3;
+		if (n >= 0 && n != node)
+			continue;
+		val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
+		val = (val >>  12) & 0xfffff;
+		base = (uint64_t) val << 20;
+		val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
+		val = (val >>  12) & 0xfffff;
+		if (val == 0)   /* BAR not used */
+			continue;
+		lim = ((uint64_t)val + 1) << 20;
+		dram_map[rv] = base;
+		dram_map[rv + 1] = lim;
+		rv += 2;
+	}
+	return rv;
+}

arch/mips/netlogic/xlp/setup.c +23 -0

index 7b638f7..7718368 100644
@@ -73,6 +73,23 @@ static void nlm_fixup_mem(void)
 	}
 }
 
+static void __init xlp_init_mem_from_bars(void)
+{
+	uint64_t map[16];
+	int i, n;
+
+	n = xlp_get_dram_map(-1, map);	/* -1: info for all nodes */
+	for (i = 0; i < n; i += 2) {
+		/* exclude 0x1000_0000-0x2000_0000, u-boot device */
+		if (map[i] <= 0x10000000 && map[i+1] > 0x10000000)
+			map[i+1] = 0x10000000;
+		if (map[i] > 0x10000000 && map[i] < 0x20000000)
+			map[i] = 0x20000000;
+
+		add_memory_region(map[i], map[i+1] - map[i], BOOT_MEM_RAM);
+	}
+}
+
 void __init plat_mem_setup(void)
 {
 	panic_timeout	= 5;

@@ -82,6 +99,12 @@ void __init plat_mem_setup(void)
 
 	/* memory and bootargs from DT */
 	early_init_devtree(initial_boot_params);
+
+	if (boot_mem_map.nr_map == 0) {
+		pr_info("Using DRAM BARs for memory map.\n");
+		xlp_init_mem_from_bars();
+	}
+	/* Calculate and setup wired entries for mapped kernel */
 	nlm_fixup_mem();
 }

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-08-11 09:15 UTC #3 lore raw

PATCH 2/10 MIPS: Netlogic: Remove memory section from built-in DT

In reply to Jayachandran C

Do not pass a memory section in the built-in DTB, and let the boot code use the values from the DRAM BARs.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/dts/xlp_evp.dts |    7 -------
 arch/mips/netlogic/dts/xlp_svp.dts |    7 -------
 2 files changed, 14 deletions(-)

arch/mips/netlogic/dts/xlp_evp.dts +0 -7

index 0640703..7862a6f 100644
@@ -9,13 +9,6 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
-	memory {
-		device_type = "memory";
-		reg =  <0 0x00100000 0 0x0FF00000	// 255M at 1M
-			0 0x20000000 0 0xa0000000	// 2560M at 512M
-			0 0xe0000000 1 0x00000000>;
-	};
-
 	soc {
 		#address-cells = <2>;
 		#size-cells = <1>;

arch/mips/netlogic/dts/xlp_svp.dts +0 -7

index 9c5db10..5aba17e 100644
@@ -9,13 +9,6 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
-	memory {
-		device_type = "memory";
-		reg =  <0 0x00100000 0 0x0FF00000	// 255M at 1M
-			0 0x20000000 0 0xa0000000	// 2560M at 512M
-			0 0xe0000000 0 0x40000000>;
-	};
-
 	soc {
 		#address-cells = <2>;
 		#size-cells = <1>;

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-08-11 09:19 UTC #4 lore raw

PATCH 3/10 MIPS: Netlogic: Fix DT flash size parameter

In reply to Jayachandran C

The flash chipselects can span 32MB, fix this in the built-in device tree.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/dts/xlp_evp.dts |    2 +-
 arch/mips/netlogic/dts/xlp_svp.dts |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

arch/mips/netlogic/dts/xlp_evp.dts +1 -1

index 7862a6f..89ad048 100644
@@ -14,7 +14,7 @@
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
-			  1 0  0 0x16000000  0x01000000>; // GBU chipselects
+			  1 0  0 0x16000000  0x02000000>; // GBU chipselects
 
 		serial0: serial@30000 {
 			device_type = "serial";

arch/mips/netlogic/dts/xlp_svp.dts +1 -1

index 5aba17e..1ebd00ed 100644
@@ -14,7 +14,7 @@
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
-			  1 0  0 0x16000000  0x01000000>; // GBU chipselects
+			  1 0  0 0x16000000  0x02000000>; // GBU chipselects
 
 		serial0: serial@30000 {
 			device_type = "serial";

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-08-11 09:13 UTC #5 lore raw

PATCH 4/10 MIPS: Netlogic: Add support for XLP2XX

In reply to Jayachandran C

XLP2XX is first in the series of 28nm XLPII processors.

The changes are to:
* Add processor ID for XLP2XX to asm/cpu.h and kernel/cpu-probe.c.
* Add a cpu_is_xlpii() function to check for XLPII processors.
* Update xlp_mmu_init() to use config4 to enable extended TLB.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/cpu.h                  |    1 +
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h |    7 +++++++
 arch/mips/kernel/cpu-probe.c                 |    5 +++++
 arch/mips/netlogic/xlp/setup.c               |   27 +++++++++++++++++++-------
 4 files changed, 33 insertions(+), 7 deletions(-)

arch/mips/include/asm/cpu.h +1 -0

index 632bbe5..7c8d15d 100644
@@ -176,6 +176,7 @@
 
 #define PRID_IMP_NETLOGIC_XLP8XX	0x1000
 #define PRID_IMP_NETLOGIC_XLP3XX	0x1100
+#define PRID_IMP_NETLOGIC_XLP2XX	0x1200
 
 /*
  * Definitions for 7:0 on legacy processors

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +7 -0

index d59cdd6..7a4a514 100644
@@ -64,5 +64,12 @@ int xlp_get_dram_map(int n, uint64_t *dram_map);
 /* Device tree related */
 void *xlp_dt_init(void *fdtp);
 
+static inline int cpu_is_xlpii(void)
+{
+	int chip = read_c0_prid() & 0xff00;
+
+	return chip == PRID_IMP_NETLOGIC_XLP2XX;
+}
+
 #endif /* !__ASSEMBLY__ */
 #endif /* _ASM_NLM_XLP_H */

arch/mips/kernel/cpu-probe.c +5 -0

index 4c6167a..bfd5acb 100644
@@ -899,6 +899,11 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
 			MIPS_CPU_LLSC);
 
 	switch (c->processor_id & 0xff00) {
+	case PRID_IMP_NETLOGIC_XLP2XX:
+		c->cputype = CPU_XLP;
+		__cpu_name[cpu] = "Broadcom XLPII";
+		break;
+
 	case PRID_IMP_NETLOGIC_XLP8XX:
 	case PRID_IMP_NETLOGIC_XLP3XX:
 		c->cputype = CPU_XLP;

arch/mips/netlogic/xlp/setup.c +20 -7

index 0c6e300..0a99cd5 100644
@@ -110,7 +110,12 @@ void __init plat_mem_setup(void)
 
 const char *get_system_type(void)
 {
-	return "Netlogic XLP Series";
+	switch (read_c0_prid() & 0xff00) {
+	case PRID_IMP_NETLOGIC_XLP2XX:
+		return "Broadcom XLPII Series";
+	default:
+		return "Netlogic XLP Series";
+	}
 }
 
 void __init prom_free_prom_memory(void)

@@ -120,12 +125,20 @@ void __init prom_free_prom_memory(void)
 
 void xlp_mmu_init(void)
 {
-	/* enable extended TLB and Large Fixed TLB */
-	write_c0_config6(read_c0_config6() | 0x24);
-
-	/* set page mask of Fixed TLB in config7 */
-	write_c0_config7(PM_DEFAULT_MASK >>
-		(13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
+	u32 conf4;
+
+	if (cpu_is_xlpii()) {
+		/* XLPII series has extended pagesize in config 4 */
+		conf4 = read_c0_config4() & ~0x1f00u;
+		write_c0_config4(conf4 | ((PAGE_SHIFT - 10) / 2 << 8));
+	} else {
+		/* enable extended TLB and Large Fixed TLB */
+		write_c0_config6(read_c0_config6() | 0x24);
+
+		/* set page mask of extended Fixed TLB in config7 */
+		write_c0_config7(PM_DEFAULT_MASK >>
+			(13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
+	}
 }
 
 void nlm_percpu_init(int hwcpuid)

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-08-11 09:16 UTC #6 lore raw

PATCH 5/10 MIPS: Netlogic: Call xlp_mmu_init on all threads

In reply to Jayachandran C

The config7/config4 register has to be written on all the threads. This does not cause any problems in XLP, but is needed for XLPII

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/common/smp.c |    4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

arch/mips/netlogic/common/smp.c +1 -3

index 4e35d9c..6f8feb9 100644
@@ -106,9 +106,7 @@ void nlm_early_init_secondary(int cpu)
 {
 	change_c0_config(CONF_CM_CMASK, 0x3);
 #ifdef CONFIG_CPU_XLP
-	/* mmu init, once per core */
-	if (cpu % NLM_THREADS_PER_CORE == 0)
-		xlp_mmu_init();
+	xlp_mmu_init();
 #endif
 	write_c0_ebase(nlm_current_node()->ebase);
 }

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-08-11 09:17 UTC #7 lore raw

PATCH 6/10 MIPS: Netlogic: XLP2XX CPU and PIC frequency

In reply to Jayachandran C

From: Ganesan Ramalingam <[email protected]>

Add code to calculate the CPU and PIC frequency for XLP2XX SoCs.

Since the PIC frequency on XLP2XX can be configured, add a new macro pic_timer_freq() to be used in netlogic/common/time.c.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/netlogic/xlp-hal/pic.h |    5 +-
 arch/mips/include/asm/netlogic/xlp-hal/sys.h |   31 +++++++
 arch/mips/include/asm/netlogic/xlr/pic.h     |    2 +
 arch/mips/netlogic/common/time.c             |    3 +-
 arch/mips/netlogic/xlp/nlm_hal.c             |  123 ++++++++++++++++++++++++--
 5 files changed, 153 insertions(+), 11 deletions(-)

arch/mips/include/asm/netlogic/xlp-hal/pic.h +3 -2

index 4b5108d..105389b 100644
@@ -208,13 +208,14 @@
 #define PIC_LOCAL_SCHEDULING		1
 #define PIC_GLOBAL_SCHEDULING		0
 
-#define PIC_CLK_HZ			133333333
-
 #define nlm_read_pic_reg(b, r)	nlm_read_reg64(b, r)
 #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
 #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
 #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
+/* We use PIC on node 0 as a timer */
+#define pic_timer_freq()		nlm_get_pic_frequency(0)
+
 /* IRT and h/w interrupt routines */
 static inline int
 nlm_pic_read_irt(uint64_t base, int irt_index)

arch/mips/include/asm/netlogic/xlp-hal/sys.h +31 -0

index 470e52b..fcf2833 100644
@@ -117,6 +117,36 @@
 #define SYS_SCRTCH2				0x4b
 #define SYS_SCRTCH3				0x4c
 
+/* PLL registers XLP2XX */
+#define SYS_PLL_CTRL0				0x240
+#define SYS_PLL_CTRL1				0x241
+#define SYS_PLL_CTRL2				0x242
+#define SYS_PLL_CTRL3				0x243
+#define SYS_DMC_PLL_CTRL0			0x244
+#define SYS_DMC_PLL_CTRL1			0x245
+#define SYS_DMC_PLL_CTRL2			0x246
+#define SYS_DMC_PLL_CTRL3			0x247
+
+#define SYS_PLL_CTRL0_DEVX(x)			(0x248 + (x) * 4)
+#define SYS_PLL_CTRL1_DEVX(x)			(0x249 + (x) * 4)
+#define SYS_PLL_CTRL2_DEVX(x)			(0x24a + (x) * 4)
+#define SYS_PLL_CTRL3_DEVX(x)			(0x24b + (x) * 4)
+
+#define SYS_CPU_PLL_CHG_CTRL			0x288
+#define SYS_PLL_CHG_CTRL			0x289
+#define SYS_CLK_DEV_DIS				0x28a
+#define SYS_CLK_DEV_SEL				0x28b
+#define SYS_CLK_DEV_DIV				0x28c
+#define SYS_CLK_DEV_CHG				0x28d
+#define SYS_CLK_DEV_SEL_REG			0x28e
+#define SYS_CLK_DEV_DIV_REG			0x28f
+#define SYS_CPU_PLL_LOCK			0x29f
+#define SYS_SYS_PLL_LOCK			0x2a0
+#define SYS_PLL_MEM_CMD				0x2a1
+#define SYS_CPU_PLL_MEM_REQ			0x2a2
+#define SYS_SYS_PLL_MEM_REQ			0x2a3
+#define SYS_PLL_MEM_STAT			0x2a4
+
 #ifndef __ASSEMBLY__
 
 #define nlm_read_sys_reg(b, r)		nlm_read_reg(b, r)

@@ -124,5 +154,6 @@
 #define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
 #define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
+unsigned int nlm_get_pic_frequency(int node);
 #endif
 #endif

arch/mips/include/asm/netlogic/xlr/pic.h +2 -0

index 63c9917..3c80a75 100644
@@ -36,6 +36,8 @@
 #define _ASM_NLM_XLR_PIC_H
 
 #define PIC_CLK_HZ			66666666
+#define pic_timer_freq()		PIC_CLK_HZ
+
 /* PIC hardware interrupt numbers */
 #define PIC_IRT_WD_INDEX		0
 #define PIC_IRT_TIMER_0_INDEX		1

arch/mips/netlogic/common/time.c +2 -1

index 045a396..13391b8 100644
@@ -45,6 +45,7 @@
 #if defined(CONFIG_CPU_XLP)
 #include <asm/netlogic/xlp-hal/iomap.h>
 #include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/sys.h>
 #include <asm/netlogic/xlp-hal/pic.h>
 #elif defined(CONFIG_CPU_XLR)
 #include <asm/netlogic/xlr/iomap.h>

@@ -91,7 +92,7 @@ static void nlm_init_pic_timer(void)
 		csrc_pic.read	= nlm_get_pic_timer;
 	}
 	csrc_pic.rating = 1000;
-	clocksource_register_hz(&csrc_pic, PIC_CLK_HZ);
+	clocksource_register_hz(&csrc_pic, pic_timer_freq());
 }
 
 void __init plat_time_init(void)

arch/mips/netlogic/xlp/nlm_hal.c +115 -8

133 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-08-11 09:18 UTC #8 lore raw

PATCH 7/10 MIPS: Netlogic: Core wakeup changes for XLP2XX

In reply to Jayachandran C

On XLP2xx, wakeup code does not need to enable clock on the core. Update xlp/wakeup.c to handle this.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/xlp/wakeup.c |   10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

arch/mips/netlogic/xlp/wakeup.c +6 -4

index 0cce37c..682d563 100644
@@ -58,10 +58,12 @@ static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
 
 	coremask = (1 << core);
 
-	/* Enable CPU clock */
-	value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
-	value &= ~coremask;
-	nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
+	/* Enable CPU clock in case of 8xx/3xx */
+	if (!cpu_is_xlpii()) {
+		value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
+		value &= ~coremask;
+		nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
+	}
 
 	/* Remove CPU Reset */
 	value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-08-11 09:20 UTC #9 lore raw

PATCH 8/10 MIPS: Netlogic: XLP2xx update for I2C controller

In reply to Jayachandran C

From: Ganesan Ramalingam <[email protected]>

XLP2xx has a new I2C controller which has 4 buses connected to it. Update the IO offset and IRQ mapping code to reflect this.

Signed-off-by Ganesan Ramalingam <[email protected]>

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/netlogic/xlp-hal/iomap.h |    3 +++
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h   |    2 ++
 arch/mips/netlogic/xlp/nlm_hal.c               |   23 ++++++++++++++++-------
 3 files changed, 21 insertions(+), 7 deletions(-)

arch/mips/include/asm/netlogic/xlp-hal/iomap.h +3 -0

index 9fac46f..61c84de 100644
@@ -88,6 +88,9 @@
 #define XLP_IO_I2C0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 2)
 #define XLP_IO_I2C1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 3)
 #define XLP_IO_GPIO_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 4)
+/* on 2XX, all I2C busses are on the same block */
+#define XLP2XX_IO_I2C_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 7)
+
 /* system management */
 #define XLP_IO_SYS_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 6, 5)
 #define XLP_IO_JTAG_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 6)

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +2 -0

index 7a4a514..4950ea5 100644
@@ -50,6 +50,8 @@
 #define PIC_MMC_IRQ			29
 #define PIC_I2C_0_IRQ			30
 #define PIC_I2C_1_IRQ			31
+#define PIC_I2C_2_IRQ			32
+#define PIC_I2C_3_IRQ			33
 
 #ifndef __ASSEMBLY__

arch/mips/netlogic/xlp/nlm_hal.c +16 -7

index 22e2e02..04adb75 100644
@@ -93,11 +93,14 @@ int nlm_irq_to_irt(int irq)
 	case PIC_MMC_IRQ:
 		devoff = XLP_IO_SD_OFFSET(0);
 		break;
-	case PIC_I2C_0_IRQ:
-		devoff = XLP_IO_I2C0_OFFSET(0);
-		break;
+	case PIC_I2C_0_IRQ:	/* I2C will be fixed up */
 	case PIC_I2C_1_IRQ:
-		devoff = XLP_IO_I2C1_OFFSET(0);
+	case PIC_I2C_2_IRQ:
+	case PIC_I2C_3_IRQ:
+		if (cpu_is_xlpii())
+			devoff = XLP2XX_IO_I2C_OFFSET(0);
+		else
+			devoff = XLP_IO_I2C0_OFFSET(0);
 		break;
 	default:
 		devoff = 0;

@@ -107,9 +110,15 @@ int nlm_irq_to_irt(int irq)
 	if (devoff != 0) {
 		pcibase = nlm_pcicfg_base(devoff);
 		irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
-		/* HW bug, I2C 1 irt entry is off by one */
-		if (irq == PIC_I2C_1_IRQ)
-			irt = irt + 1;
+		/* HW weirdness, I2C IRT entry has to be fixed up */
+		switch (irq) {
+		case PIC_I2C_1_IRQ:
+			irt = irt + 1; break;
+		case PIC_I2C_2_IRQ:
+			irt = irt + 2; break;
+		case PIC_I2C_3_IRQ:
+			irt = irt + 3; break;
+		}
 	} else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) {
 		/* HW bug, PCI IRT entries are bad on early silicon, fix */
 		irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ);

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-08-11 09:20 UTC #10 lore raw

PATCH 9/10 MIPS: Netlogic: Add support for USB on XLP2xx

In reply to Jayachandran C

From: Ganesan Ramalingam <[email protected]>

Add USB intialization code to handle the new XLP2XX USB 3.0 block. This adds xlp/usb-init-xlp2.c initialize the XLP2XX USB glue logic for the XHCI and EHCI. Interrupt and IO offset code in xlp-hal/iomap.h and xlp/nlm_hal.c is updated to handle the new USB block and interrupts.

Signed-off-by Ganesan Ramalingam <[email protected]>

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/netlogic/xlp-hal/iomap.h |    7 +
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h   |    5 +
 arch/mips/netlogic/xlp/Makefile                |    1 +
 arch/mips/netlogic/xlp/nlm_hal.c               |   56 +++---
 arch/mips/netlogic/xlp/usb-init-xlp2.c         |  218 ++++++++++++++++++++++++
 arch/mips/netlogic/xlp/usb-init.c              |    3 +
 6 files changed, 270 insertions(+), 20 deletions(-)
 create mode 100644 arch/mips/netlogic/xlp/usb-init-xlp2.c

arch/mips/include/asm/netlogic/xlp-hal/iomap.h +7 -0

index 61c84de..55eee77 100644
@@ -72,6 +72,12 @@
 #define XLP_IO_USB_OHCI2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 4)
 #define XLP_IO_USB_OHCI3_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 5)
 
+/* XLP2xx has an updated USB block */
+#define XLP2XX_IO_USB_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 4, i)
+#define XLP2XX_IO_USB_XHCI0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 4, 1)
+#define XLP2XX_IO_USB_XHCI1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 4, 2)
+#define XLP2XX_IO_USB_XHCI2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 4, 3)
+
 #define XLP_IO_NAE_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 3, 0)
 #define XLP_IO_POE_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 3, 1)

@@ -148,6 +154,7 @@
 #define PCI_DEVICE_ID_NLM_NOR		0x1015
 #define PCI_DEVICE_ID_NLM_NAND		0x1016
 #define PCI_DEVICE_ID_NLM_MMC		0x1018
+#define PCI_DEVICE_ID_NLM_XHCI		0x101d
 
 #ifndef __ASSEMBLY__

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +5 -0

index 4950ea5..17daffb2 100644
@@ -41,12 +41,17 @@
 #define PIC_PCIE_LINK_1_IRQ		20
 #define PIC_PCIE_LINK_2_IRQ		21
 #define PIC_PCIE_LINK_3_IRQ		22
+
 #define PIC_EHCI_0_IRQ			23
 #define PIC_EHCI_1_IRQ			24
 #define PIC_OHCI_0_IRQ			25
 #define PIC_OHCI_1_IRQ			26
 #define PIC_OHCI_2_IRQ			27
 #define PIC_OHCI_3_IRQ			28
+#define PIC_2XX_XHCI_0_IRQ		23
+#define PIC_2XX_XHCI_1_IRQ		24
+#define PIC_2XX_XHCI_2_IRQ		25
+
 #define PIC_MMC_IRQ			29
 #define PIC_I2C_0_IRQ			30
 #define PIC_I2C_1_IRQ			31

arch/mips/netlogic/xlp/Makefile +1 -0

index 85ac4a8..ed9a93c 100644
@@ -1,3 +1,4 @@
 obj-y				+= setup.o nlm_hal.o cop2-ex.o dt.o
 obj-$(CONFIG_SMP)		+= wakeup.o
 obj-$(CONFIG_USB)		+= usb-init.o
+obj-$(CONFIG_USB)		+= usb-init-xlp2.o

arch/mips/netlogic/xlp/nlm_hal.c +36 ~~-20~~

74 lines not on this page · raw message

arch/mips/netlogic/xlp/usb-init-xlp2.c new file +218 -0

218 lines not on this page · raw message

arch/mips/netlogic/xlp/usb-init.c +3 -0

index ef3897e..61bc303 100644
@@ -100,6 +100,9 @@ static void nlm_usb_hw_reset(int node, int port)
 
 static int __init nlm_platform_usb_init(void)
 {
+	if (cpu_is_xlpii())
+		return 0;
+
 	pr_info("Initializing USB Interface\n");
 	nlm_usb_hw_reset(0, 0);
 	nlm_usb_hw_reset(0, 3);

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-08-21 14:01 UTC #11 lore raw

PATCH v2 9/10 MIPS: Netlogic: Add support for USB on XLP2xx

From: Ganesan Ramalingam <[email protected]>

Add USB intialization code to handle the new XLP2XX USB 3.0 block. This adds xlp/usb-init-xlp2.c to initialize the XLP2XX USB glue-logic for XHCI and EHCI. Interrupt and IO offset code in xlp-hal/iomap.h and xlp/nlm_hal.c is also updated for the new USB block.

Signed-off-by Ganesan Ramalingam <[email protected]>

Signed-off-by Jayachandran C <[email protected]>

---
[Updated to use xlpii instead of xlp2xx, since the upcoming xlp9xx also
uses the same USB block, also update interrupt mask to correct value]

 arch/mips/include/asm/netlogic/xlp-hal/iomap.h |    7 +
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h   |    5 +
 arch/mips/netlogic/xlp/Makefile                |    1 +
 arch/mips/netlogic/xlp/nlm_hal.c               |   56 +++---
 arch/mips/netlogic/xlp/usb-init-xlp2.c         |  218 ++++++++++++++++++++++++
 arch/mips/netlogic/xlp/usb-init.c              |    3 +
 6 files changed, 270 insertions(+), 20 deletions(-)
 create mode 100644 arch/mips/netlogic/xlp/usb-init-xlp2.c

arch/mips/include/asm/netlogic/xlp-hal/iomap.h +7 -0

index 61c84de..55eee77 100644
@@ -72,6 +72,12 @@
 #define XLP_IO_USB_OHCI2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 4)
 #define XLP_IO_USB_OHCI3_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 5)
 
+/* XLP2xx has an updated USB block */
+#define XLP2XX_IO_USB_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 4, i)
+#define XLP2XX_IO_USB_XHCI0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 4, 1)
+#define XLP2XX_IO_USB_XHCI1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 4, 2)
+#define XLP2XX_IO_USB_XHCI2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 4, 3)
+
 #define XLP_IO_NAE_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 3, 0)
 #define XLP_IO_POE_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 3, 1)

@@ -148,6 +154,7 @@
 #define PCI_DEVICE_ID_NLM_NOR		0x1015
 #define PCI_DEVICE_ID_NLM_NAND		0x1016
 #define PCI_DEVICE_ID_NLM_MMC		0x1018
+#define PCI_DEVICE_ID_NLM_XHCI		0x101d
 
 #ifndef __ASSEMBLY__

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +5 -0

index 4950ea5..17daffb2 100644
@@ -41,12 +41,17 @@
 #define PIC_PCIE_LINK_1_IRQ		20
 #define PIC_PCIE_LINK_2_IRQ		21
 #define PIC_PCIE_LINK_3_IRQ		22
+
 #define PIC_EHCI_0_IRQ			23
 #define PIC_EHCI_1_IRQ			24
 #define PIC_OHCI_0_IRQ			25
 #define PIC_OHCI_1_IRQ			26
 #define PIC_OHCI_2_IRQ			27
 #define PIC_OHCI_3_IRQ			28
+#define PIC_2XX_XHCI_0_IRQ		23
+#define PIC_2XX_XHCI_1_IRQ		24
+#define PIC_2XX_XHCI_2_IRQ		25
+
 #define PIC_MMC_IRQ			29
 #define PIC_I2C_0_IRQ			30
 #define PIC_I2C_1_IRQ			31

arch/mips/netlogic/xlp/Makefile +1 -0

index 85ac4a8..ed9a93c 100644
@@ -1,3 +1,4 @@
 obj-y				+= setup.o nlm_hal.o cop2-ex.o dt.o
 obj-$(CONFIG_SMP)		+= wakeup.o
 obj-$(CONFIG_USB)		+= usb-init.o
+obj-$(CONFIG_USB)		+= usb-init-xlp2.o

arch/mips/netlogic/xlp/nlm_hal.c +36 ~~-20~~

74 lines not on this page · raw message

arch/mips/netlogic/xlp/usb-init-xlp2.c new file +218 -0

218 lines not on this page · raw message

arch/mips/netlogic/xlp/usb-init.c +3 -0

index ef3897e..61bc303 100644
@@ -100,6 +100,9 @@ static void nlm_usb_hw_reset(int node, int port)
 
 static int __init nlm_platform_usb_init(void)
 {
+	if (cpu_is_xlpii())
+		return 0;
+
 	pr_info("Initializing USB Interface\n");
 	nlm_usb_hw_reset(0, 0);
 	nlm_usb_hw_reset(0, 3);

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-08-11 09:19 UTC #12 lore raw

PATCH 10/10 MIPS: Netlogic: built-in DTB for XLP2xx SoC boards

In reply to Jayachandran C

From: Ganesan Ramalingam <[email protected]>

Add a default built-in device tree for XLP2xx SoC. The new file xlp_fvp.dts has updated entries for I2C and memory.

Signed-off-by Ganesan Ramalingam <[email protected]>

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/Kconfig         |    9 +++
 arch/mips/netlogic/dts/Makefile    |    1 +
 arch/mips/netlogic/dts/xlp_fvp.dts |  118 ++++++++++++++++++++++++++++++++++++
 arch/mips/netlogic/xlp/dt.c        |    8 ++-
 4 files changed, 135 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/netlogic/dts/xlp_fvp.dts

arch/mips/netlogic/Kconfig +9 -0

index 2447bf9..852a4ee 100644
@@ -19,6 +19,15 @@ config DT_XLP_SVP
 	  pointer to the kernel.  The corresponding DTS file is at
 	  arch/mips/netlogic/dts/xlp_svp.dts
 
+config DT_XLP_FVP
+	bool "Built-in device tree for XLP FVP boards"
+	default y
+	help
+	  Add an FDT blob for XLP FVP board into the kernel.
+	  This DTB will be used if the firmware does not pass in a DTB
+	  pointer to the kernel.  The corresponding DTS file is at
+	  arch/mips/netlogic/dts/xlp_fvp.dts
+
 config NLM_MULTINODE
 	bool "Support for multi-chip boards"
 	depends on NLM_XLP_BOARD

arch/mips/netlogic/dts/Makefile +1 -0

index aecb6fa..0b9be5f 100644
@@ -1,2 +1,3 @@
 obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o
 obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o
+obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o

arch/mips/netlogic/dts/xlp_fvp.dts new file +118 -0

118 lines not on this page · raw message

arch/mips/netlogic/xlp/dt.c +7 -1

index a15cdbb..88df445 100644
@@ -39,12 +39,18 @@
 #include <linux/of_platform.h>
 #include <linux/of_device.h>
 
-extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_start[];
+extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[],
+	__dtb_xlp_fvp_begin[], __dtb_start[];
 
 void __init *xlp_dt_init(void *fdtp)
 {
 	if (!fdtp) {
 		switch (current_cpu_data.processor_id & 0xff00) {
+#ifdef CONFIG_DT_XLP_FVP
+		case PRID_IMP_NETLOGIC_XLP2XX:
+			fdtp = __dtb_xlp_fvp_begin;
+			break;
+#endif
 #ifdef CONFIG_DT_XLP_SVP
 		case PRID_IMP_NETLOGIC_XLP3XX:
 			fdtp = __dtb_xlp_svp_begin;

Signature · 1 line

1.7.9.5