Skip to contentSkip to conversation

am335x:Handle worst case scenario for Errata 1.0.24

PATCH New Tom Rini 1 participant 1 message Aug 14, 2013 Arm (32-bit)

lore
Share & tools
lore

Tom Rini

author
#0 lore raw

PATCH v2 1/1 am335x:Handle worst case scenario for Errata 1.0.24

From: Steve Kipisz <[email protected]>

In Errata 1.0.24, if the board is running at OPP50 and has a warm reset, the boot ROM sets the frequencies for OPP100. This patch attempts to drop the frequencies back to OPP50 as soon as possible in the SPL. Then later the voltages and frequencies up set higher.

Cc Enric Balletbo i Serra <[email protected]>
Cc Lars Poeschel <[email protected]>
Signed-off-by Steve Kipisz <[email protected]>
[trini: Adapt to current framework]
Signed-off-by Tom Rini <[email protected]>

---
Changes in v2:
- Address Dan Murphy's comments

---
 arch/arm/cpu/armv7/am33xx/board.c                |    2 +
 arch/arm/cpu/armv7/am33xx/clock_am33xx.c         |   72 ++++++++++++++--------
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |    3 +
 arch/arm/include/asm/arch-am33xx/sys_proto.h     |    1 +
 board/ti/am335x/board.c                          |   12 ++++
 include/configs/pcm051.h                         |    1 +
 include/power/tps65217.h                         |    1 +
 7 files changed, 68 insertions(+), 24 deletions(-)
arch/arm/cpu/armv7/am33xx/board.c +2 -0
index 88e2093..e94b038 100644
@@ -150,6 +150,8 @@ int arch_misc_init(void)
  */
 __weak void am33xx_spl_board_init(void)
 {
+	mpu_pll_config_val(CONFIG_SYS_MPUCLK);
+	core_pll_config(OPP_100);
 }
 
 void rtc32k_enable(void)
arch/arm/cpu/armv7/am33xx/clock_am33xx.c +48 -24

109 lines not on this page · raw message

arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +3 -0
index 789188b..9a480d9 100644
@@ -11,6 +11,9 @@
 #ifndef _CLOCKS_AM33XX_H_
 #define _CLOCKS_AM33XX_H_
 
+#define OPP_50	50
+#define OPP_100	100
+
 /* MAIN PLL Fdll = 550 MHz, by default */
 #ifndef CONFIG_SYS_MPUCLK
 #define CONFIG_SYS_MPUCLK	550
arch/arm/include/asm/arch-am33xx/sys_proto.h +1 -0
index 1340f83..9c7647b 100644
@@ -27,6 +27,7 @@ void save_omap_boot_params(void);
 void setup_clocks_for_console(void);
 void mpu_pll_config_val(int mpull_m);
 void ddr_pll_config(unsigned int ddrpll_M);
+void core_pll_config(int opp);
 
 void sdelay(unsigned long);
board/ti/am335x/board.c +12 -0
index e7f14db..b0fa4b2 100644
@@ -337,6 +337,15 @@ void am33xx_spl_board_init(void)
 				       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 			puts("tps65217_reg_write failure\n");
 
+		/* Set DCDC3 (CORE) voltage to 1.125V */
+		if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+					    TPS65217_DCDC_VOLT_SEL_1125MV)) {
+			puts("tps65217_voltage_update failure\n");
+			return;
+		}
+
+		/* Set CORE Frequencies to OPP100 */
+		core_pll_config(OPP_100);
 
 		/* Set DCDC2 (MPU) voltage */
 		if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {

@@ -395,6 +404,9 @@ void am33xx_spl_board_init(void)
 		/* Second, update the CORE voltage. */
 		if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 			return;
+
+		/* Set CORE Frequencies to OPP100 */
+		core_pll_config(OPP_100);
 	}
 
 	/* Set MPU Frequency to what we detected now that voltages are set */
include/configs/pcm051.h +1 -0
index 9b16c47..f4b4d62 100644
@@ -204,6 +204,7 @@
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
 /*
  * Place the image at the start of the ROM defined image space.
  * We limit our size to the ROM-defined downloaded image area, and use the
include/power/tps65217.h +1 -0
index f4c7a2b..f3e067d 100644
@@ -62,6 +62,7 @@
 #define TPS65217_USB_INPUT_CUR_LIMIT_1300MA	0x02
 #define TPS65217_USB_INPUT_CUR_LIMIT_1800MA	0x03
 
+#define TPS65217_DCDC_VOLT_SEL_1125MV		0x09
 #define TPS65217_DCDC_VOLT_SEL_1275MV		0x0F
 #define TPS65217_DCDC_VOLT_SEL_1325MV		0x11
Signature · 1 line
1.7.9.5