Specific mapping for dom0, smp kick cpus and hyp mode switch for OMAP5

I rework my previous 2 patches into this series.

First, I reorder the sequence, which the io memory mapping patch could be applied before the others.

Second, I split the "Support kick cpus and switch to hypervisor for the OMAP5" into 2 seperated patches. Although Julien suggested adding the kick cpus (in C code) after we move to we move to new implementation rather than in assembly and leave the hyp mode switch to firmware, I just post these 2 patches here for someone who may need it before the new implementation.

Third, just fix the hard tabs problem that Tim pointed out.

Chen Baozi (3):
xen/arm: Specific mapping for dom0 on OMAP5 platform xen/arm: Support kick_cpus for OMAP5 xen/arm: Enable switch to hyp mode for OMAP5432

 xen/arch/arm/arm32/mode_switch.S      | 36 +++++++++++++++++++++++++++++++----
 xen/arch/arm/platforms/omap5.c        | 31 ++++++++++++++++++++++++++++++
 xen/include/asm-arm/platforms/omap5.h | 21 ++++++++++++++++++++
 3 files changed, 84 insertions(+), 4 deletions(-)

1.8.1.4

---
 xen/arch/arm/platforms/omap5.c        | 31 +++++++++++++++++++++++++++++++
 xen/include/asm-arm/platforms/omap5.h |  4 ++++
 2 files changed, 35 insertions(+)

index 402dddd..c10cf00 100644
@@ -17,6 +17,7 @@
  * GNU General Public License for more details.
  */
 
+#include <asm/p2m.h>
 #include <xen/config.h>
 #include <asm/platform.h>
 #include <asm/platforms/omap5.h>

@@ -96,6 +97,34 @@ static int omap5_init_time(void)
     return 0;
 }
 
+/* Additional mappings for dom0 (not in the DTS) */
+static int omap5_specific_mapping(struct domain *d)
+{
+    /* Map the PRM module */
+    map_mmio_regions(d, OMAP5_PRM_BASE, OMAP5_PRM_BASE + (PAGE_SIZE * 2) - 1,
+                     OMAP5_PRM_BASE);
+
+    /* Map the PRM_MPU */
+    map_mmio_regions(d, OMAP5_PRCM_MPU_BASE,
+                     OMAP5_PRCM_MPU_BASE + PAGE_SIZE - 1,
+                     OMAP5_PRCM_MPU_BASE);
+
+    /* Map the Wakeup Gen */
+    map_mmio_regions(d, OMAP5_WKUPGEN_BASE, OMAP5_WKUPGEN_BASE + PAGE_SIZE - 1,
+                     OMAP5_WKUPGEN_BASE);
+
+    /* Map the on-chip SRAM */
+    map_mmio_regions(d, OMAP5_SRAM_PA, OMAP5_SRAM_PA + (PAGE_SIZE * 32) - 1,
+                     OMAP5_SRAM_PA);
+
+    return 0;
+}
+
+static uint32_t omap5_quirks(void)
+{
+    return PLATFORM_QUIRK_DOM0_MAPPING_11;
+}
+
 static const char const *omap5_dt_compat[] __initdata =
 {
     "ti,omap5",

@@ -105,6 +134,8 @@ static const char const *omap5_dt_compat[] __initdata =
 PLATFORM_START(omap5, "TI OMAP5")
     .compatible = omap5_dt_compat,
     .init_time = omap5_init_time,
+    .specific_mapping = omap5_specific_mapping,
+    .quirks = omap5_quirks,
 PLATFORM_END
 
 /*

index 092f340..dd8c6ca 100644
@@ -13,6 +13,10 @@
 #define OMAP5_CM_CLKSEL_SYS                     0x10
 #define SYS_CLKSEL_MASK                         0xfffffff8
 
+#define OMAP5_PRCM_MPU_BASE                     0x48243000
+#define OMAP5_WKUPGEN_BASE                      0x48281000
+#define OMAP5_SRAM_PA                           0x40300000
+
 #endif /* __ASM_ARM_PLATFORMS_OMAP5_H */
 
 /*

1.8.1.4

And applied.

I don't intend to apply #2 or #3. Hopefully you can get a newer u-boot with Andre's fixes onto this platform. If not then we can look at solving this using boot-wrapper.

Since I also just applied the UART and platform patches, I think this is everything which you have outstanding, please ping me if not.

Ian.

Actually, my firmware works very well which the secondary CPU would also boot in Hyp mode.

So for #3, I think it is not necessary on my board now. And for #2, do you mean we don't have to support SMP before the new C implementation of kicking cpus have done?

BTW, it is a little busy week for me. Sorry for all delayed reply.

Cheers,

Baozi

---
 xen/arch/arm/arm32/mode_switch.S      | 22 +++++++++++++++++++++-
 xen/include/asm-arm/platforms/omap5.h | 14 ++++++++++++++
 2 files changed, 35 insertions(+), 1 deletion(-)

index 3500eb0..ba2a462 100644
@@ -21,11 +21,13 @@
 #include <asm/page.h>
 #include <asm/platforms/vexpress.h>
 #include <asm/platforms/exynos5.h>
+#include <asm/platforms/omap5.h>
 #include <asm/asm_defns.h>
 #include <asm/gic.h>
 
 /* Wake up secondary cpus
- * This code relies on Machine ID and only works for Vexpress and the Arndale
+ * This code relies on Machine ID and only works for Vexpress, the Arndale
+ * and the OMAP5 uEVM.
  * TODO: Move this code either later (via platform specific desc) or in a bootwrapper
  * r5: Machine ID
  * Clobber r0 r2 */

@@ -34,6 +36,10 @@ kick_cpus:
         ldr   r0, =MACH_TYPE_SMDK5250
         teq   r5, r0                          /* Are we running on the arndale? */
         beq   kick_cpus_arndale
+        /* for OMAP5432 */
+        ldr   r0, =MACH_TYPE_OMAP5_SEVM
+        teq   r5, r0
+        beq   kick_cpus_omap5
         /* otherwise versatile express */
         /* write start paddr to v2m sysreg FLAGSSET register */
         ldr   r0, =(V2M_SYS_MMIO_BASE)        /* base V2M sysreg MMIO address */

@@ -55,6 +61,20 @@ kick_cpus_arndale:
         str   r2, [r0]
         dsb
         ldr   r2, =EXYNOS5_GIC_BASE_ADDRESS   /* r2 := Exynos5 gic base address */
+        b     kick_cpus_sgi
+kick_cpus_omap5:
+	/* write start paddr to AuxCoreBoot1 where ROM code will jump */
+        ldr   r0, =(OMAP_AUX_CORE_BOOT_1)
+        ldr   r2, =start
+        add   r2, r2, r10
+        str   r2, [r0]
+        ldr   r0, =(OMAP_AUX_CORE_BOOT_0)
+        mov   r2, #0x20
+        str   r2, [r0]
+        dsb
+        sev
+        ldr   r2, =OMAP5_GIC_BASE_ADDRESS     /* r2 := OMAP5 gic base address */
+        b     kick_cpus_sgi
 kick_cpus_sgi:
         /* send an interrupt */
         ldr   r0, =GIC_DR_OFFSET              /* GIC distributor offset */

index dd8c6ca..6657af6 100644
@@ -17,6 +17,20 @@
 #define OMAP5_WKUPGEN_BASE                      0x48281000
 #define OMAP5_SRAM_PA                           0x40300000
 
+#define OMAP_AUX_CORE_BOOT_0                    0x48281800
+#define OMAP_AUX_CORE_BOOT_1                    0x48281804
+
+/* Constants below is only used in assembly because the DTS is not yet parsed */
+#ifdef __ASSEMBLY__
+
+/* GIC Base Address */
+#define OMAP5_GIC_BASE_ADDRESS                  0x48210000
+
+/* OMAP5432 uEVM machine ID */
+#define MACH_TYPE_OMAP5_SEVM                    3777
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* __ASM_ARM_PLATFORMS_OMAP5_H */
 
 /*

1.8.1.4

You don't  need following call of kick_cpus_sgi:
> +        ldr   r2, =OMAP5_GIC_BASE_ADDRESS     /* r2 := OMAP5 gic base address */
> +        b     kick_cpus_sgi

Once CPU1 get an event it will check OMAP_AUX_CORE_BOOT_0 and, if it is ok, jump to OMAP_AUX_CORE_BOOT_1 address.

Sincerely,
Andrii Anisov.

Actually, Linux does the same thing that I just followed it.

Cheers,

Baozi

---
 xen/arch/arm/arm32/mode_switch.S      | 14 +++++++++++---
 xen/include/asm-arm/platforms/omap5.h |  3 +++
 2 files changed, 14 insertions(+), 3 deletions(-)

index ba2a462..52358b4 100644
@@ -93,7 +93,7 @@ kick_cpus_sgi:
  * r5: Machine ID
  * r12: CPU number
  *
- * This code is specific to the VE model/Arndale, and not intended to be used
+ * This code is specific to the VE model/Arndale/OMAP5, and not intended to be used
  * on production systems.  As such it's a bit hackier than the main
  * boot code in head.S.  In future it will be replaced by better
  * integration with the bootloader/firmware so that Xen always starts

@@ -110,15 +110,23 @@ enter_hyp_mode:
         bic   r0, r0, #0xe           /* Clear EA, FIQ and IRQ */
         mcr   CP32(r0, SCR)
 
-        ldr   r2, =MACH_TYPE_SMDK5250   /* r4 := Arndale machine ID */
         /* By default load Arndale defaults values */
+        ldr   r2, =MACH_TYPE_SMDK5250       /* r2 := Arndale machine ID */
         ldr   r0, =EXYNOS5_TIMER_FREQUENCY  /* r0 := timer's frequency */
         ldr   r1, =EXYNOS5_GIC_BASE_ADDRESS /* r1 := GIC base address */
-        /* If it's not the Arndale machine ID, load VE values */
         teq   r5, r2
+        beq   1f
+        /* If it's not the Arndale machine ID, try OMAP5 uEVM */
+        ldr   r2, =MACH_TYPE_OMAP5_SEVM     /* r2 := OMAP5 uEVM machine ID */
+        ldr   r0, =OMAP5_TIMER_FREQUENCY    /* r0 := timer's frequency */
+        ldr   r1, =OMAP5_GIC_BASE_ADDRESS   /* r1 := GIC base address */
+        teq   r5, r2
+        beq   1f
+        /* If it's not the OMAP5432 machine ID, load VE values */
         ldrne r0, =V2M_TIMER_FREQUENCY
         ldrne r1, =V2M_GIC_BASE_ADDRESS
 
+1:
         /* Ugly: the system timer's frequency register is only
          * programmable in Secure state.  Since we don't know where its
          * memory-mapped control registers live, we can't find out the

index 6657af6..a001c6a 100644
@@ -26,6 +26,9 @@
 /* GIC Base Address */
 #define OMAP5_GIC_BASE_ADDRESS                  0x48210000
 
+/* Timer's frequency */
+#define OMAP5_TIMER_FREQUENCY                   6144000 /*  6.144 Mhz */
+
 /* OMAP5432 uEVM machine ID */
 #define MACH_TYPE_OMAP5_SEVM                    3777
 

1.8.1.4

Chen,

Your changes will not work on OMAP5. You could have a quick check - just don't switch to hyp in u-boot.
Changes should look like following:

index 0588d54..b6ccd6a 100644
@@ -21,6 +21,8 @@
 #include <asm/page.h>
 #include <asm/processor-ca15.h>
 #include <asm/asm_defns.h>
+#include <asm/platforms/omap5.h>
+
 
 #define ZIMAGE_MAGIC_NUMBER 0x016f2818
 

@@ -137,7 +139,6 @@ boot_cpu:
         mov   r0, r5
         bl    putn
         PRINT(" -\r\n")
-
         /* Check that this CPU has Hyp mode */
         mrc   CP32(r0, ID_PFR1)
         and   r0, r0, #0xf000        /* Bits 12-15 define virt extensions */

@@ -155,6 +156,9 @@ boot_cpu:
         b     hyp
 1:
         /* Otherwise, it must have been Secure Supervisor mode */
+        ldr   r0, =MACH_TYPE_PANDA_NG
+        teq   r5, r0                          /* Are we running on

the panda omap5? */
+ beq 1f /* do not access SCR
from nonsecure state */

         mrc   CP32(r0, SCR)
         tst   r0, #0x1               /* Not-Secure bit set? */
         beq   1f
@@ -166,7 +170,6 @@ boot_cpu:
         ldr   r0, =enter_hyp_mode    /* VA of function */
         adr   lr, hyp                /* Set return address for call */
         add   pc, r0, r10            /* Call PA of function */

-
hyp:

         /* Zero BSS On the boot CPU to avoid nasty surprises */

index c92a1cf..7a44e67 100644
@@ -21,6 +21,7 @@
 #include <asm/page.h>
 #include <asm/platforms/vexpress.h>
 #include <asm/platforms/exynos5.h>
+#include <asm/platforms/omap5.h>
 #include <asm/asm_defns.h>
 #include <asm/gic.h>
 

@@ -34,6 +35,9 @@ kick_cpus:
         ldr   r0, =MACH_TYPE_SMDK5250
         teq   r5, r0                          /* Are we running on

the arndale? */

         beq   kick_cpus_arndale
+        ldr   r0, =MACH_TYPE_PANDA_NG
+        teq   r5, r0                          /* Are we running on
the panda omap5? */
+        beq   kick_cpus_omap5
         /* otherwise versatile express */
         /* write start paddr to v2m sysreg FLAGSSET register */
         ldr   r0, =(V2M_SYS_MMIO_BASE)        /* base V2M sysreg MMIO

address */
@@ -47,6 +51,17 @@ kick_cpus:
dsb
ldr r2, =V2M_GIC_BASE_ADDRESS /* r2 := VE gic base address */
b kick_cpus_sgi
+kick_cpus_omap5:

+        ldr   r0, =OMAP_AUX_CORE_BOOT_0
+        ldr   r2, =0x20
+        str   r2, [r0], #4  /*Update the AuxCoreBoot0 with boot state
for secondary core.*/
+        dsb
+        ldr   r2, =start
+        add   r2, r2, r10
+        str   r2, [r0]    /* Write the address of secondary startup
to the AuxCoreBoot1 */
+        dsb
+        sev
+        mov   pc, lr
 kick_cpus_arndale:
         /* write start paddr to CPU 1 sysreg register */
         ldr   r0, =(S5P_PA_SYSRAM)

@@ -82,6 +97,10 @@ kick_cpus_sgi:

.globl enter_hyp_mode
enter_hyp_mode:

+        ldr   r0, =MACH_TYPE_PANDA_NG
+        teq   r5, r0                          /* Are we running on
the panda omap5? */
+        beq   start_hypervisor_gp
+
         mov   r3, lr                 /* Put return address in non-banked reg */
         cpsid aif, #0x16             /* Enter Monitor mode */
         mrc   CP32(r0, SCR)
@@ -152,6 +171,23 @@ skip_spis:
         msr   spsr_cxsf, r0          /* into the SPSR */
         movs  pc, r3                 /* Exception-return into Hyp mode */

+start_hypervisor_gp:

+        adr   r0, save
+        stmea r0, {r4-r13,lr}
+        ldr   r12, =0x102
+        adr   r0, hyp_return
+        dsb
+        isb
+        dmb
+        smc   #0

+hyp_return:
+ adr r0, save
+ ldmfd r0, {r4-r13,pc}
+save:

+        .rept 11
+        .word 0
+        .endr

+
/*
* Local variables:
* mode: ASM

Sincerely,
Andrii Anisov.

Chen,

I have got a clue what's going on in u-boot. You can see it in arch/arm/lib/bootm.c, functions hyp_enable, __hyp_init_sec. U-boot running on CPU0, kicks CPU1, switches from SVC32 came from ROM code to HYP on CPU0 (using smc API).
Code CPU1 is kicked to, does switch to HYP, and executes what ROM normally does: wait for event, checks AUX_CORE_BOOT_0 if ok - jumps to AUX_CORE_BOOT_1. The only difference from waiting in ROM code is that CPU1 is already in HYP.

Sincerely,
Andrii Anisov.

Well,

Providing mode_switch.c going to be removed, this discussion is just theorization ;)

Sincerely,
Andrii Anisov.

Well,

My colleague just gave me a nasty hint.

Code CPU1 is kicked to, does switch to HYP, and executes what ROM

Another difference is that executed wait/check code is placed not in ROM but in RAM. And, theoretically, could be corrupted.
Taking in account existing plans to move CPU kicking to later stages, f.e. while xen parses dt.

*Sincerely,*
*Andrii Anisov.*

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Have you tried the latest upstream u-boot?

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Yes, sure.

Sincerely,
Andrii Anisov.

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