ath9k: Enable PLL fix only for AR9340/AR9330

PATCH New Sujith Manoharan 1 participant 1 message Aug 20, 2013 Qualcomm Atheros ATH9K wireless driver

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Sujith Manoharan

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2013-08-20 04:39 UTC #0 lore raw

PATCH 1/1 ath9k: Enable PLL fix only for AR9340/AR9330

From: Sujith Manoharan <[email protected]>

The PLL hang workaround is required only for AR9330 and AR9340. This issue was first observed on an AP121 and the WAR is enabled for AR9340 also (DB120 etc.), since it uses a PLL design identical to AR9330. This is not required for AR9485 and AR9550.

Various bugs have been reported regarding this:

https://bugzilla.redhat.com/show_bug.cgi?id=997217
https://bugzilla.redhat.com/show_bug.cgi?id=994648

Cc [email protected]

Signed-off-by Sujith Manoharan <[email protected]>

---
 drivers/net/wireless/ath/ath9k/main.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

drivers/net/wireless/ath/ath9k/main.c +1 -2

index ac9f18f..e4f6590 100644
@@ -173,8 +173,7 @@ static void ath_restart_work(struct ath_softc *sc)
 {
 	ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
 
-	if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
-	    AR_SREV_9550(sc->sc_ah))
+	if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
 		ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
 				     msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));

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