Add support for MSM's mmio clock/reset controller

The first two patches fix a clock framework bug and break a reset-controller include ordering requirement.

The next 3 patches are generic clock framework patches. They add support for regmap and for setting the rate and the parent at the same time based on patches from James Hogan's remuxing set_rate series.

After that we add MSM clock hardware support and SoC specific drivers. The DT node additions will be sent through the MSM maintainers once these patches are accepted.

Some questions:

1) The clock controller is also a power domain controller. Should we put that code in the drivers under drivers/clk/msm?

2) Should the directory be renamed to qcom to match the binding? (I will probably do this for the next spin)

3) What is the right place for clock dt binding #defines? clk/ or clock/?

Changes since v2:

* Completed 8960 and 8974 GCC data & dt-bindings
* Added support for reset controllers
* Squashed some bugs in 8974 gcc clocks
* New patch to fix clk NULL pointer deref
* New patch to fix #include requirement for reset-controller.h

Changes since v1:

* Rewrote binding to use #clock-cells=1
* Reworked library components (pll, rcg, branch) to use regmap
* Dropped common clock framework patches that did DT parsing
* New patches for regmap support in common clock framework

Stephen Boyd (12):
clk: Fix debugfs reparenting NULL pointer dereference
reset: Silence warning in reset-controller.h
clk: Allow drivers to pass in a regmap
clk: Add regmap core helpers for enable/disable/is_enabled
clk: Add set_rate_and_parent() op
clk: msm: Add support for phase locked loops (PLLs)
clk: msm: Add support for root clock generators (RCGs)
clk: msm: Add support for branches/gate clocks
clk: msm: Add reset controller support
clk: msm: Add support for MSM8960's global clock controller (GCC)
clk: msm: Add support for MSM8960's multimedia clock controller (MMCC)
clk: msm: Add support for MSM8974's global clock controller (GCC)

 Documentation/clk.txt                              |    3 +
 .../devicetree/bindings/clock/qcom,gcc.txt         |   22 +
 .../devicetree/bindings/clock/qcom,mmcc.txt        |   21 +
 drivers/clk/Kconfig                                |    2 +
 drivers/clk/Makefile                               |    1 +
 drivers/clk/clk.c                                  |  159 +-
 drivers/clk/msm/Kconfig                            |   30 +
 drivers/clk/msm/Makefile                           |   11 +
 drivers/clk/msm/clk-branch.c                       |  152 +
 drivers/clk/msm/clk-branch.h                       |   52 +
 drivers/clk/msm/clk-pll.c                          |  145 +
 drivers/clk/msm/clk-pll.h                          |   47 +
 drivers/clk/msm/clk-rcg.c                          |  517 ++++
 drivers/clk/msm/clk-rcg.h                          |  157 ++
 drivers/clk/msm/clk-rcg2.c                         |  270 ++
 drivers/clk/msm/gcc-8960.c                         | 2929 ++++++++++++++++++++
 drivers/clk/msm/gcc-8974.c                         | 2453 ++++++++++++++++
 drivers/clk/msm/mmcc-8960.c                        | 2129 ++++++++++++++
 drivers/clk/msm/reset.c                            |   63 +
 drivers/clk/msm/reset.h                            |   37 +
 include/dt-bindings/clk/msm-gcc-8960.h             |  313 +++
 include/dt-bindings/clk/msm-gcc-8974.h             |  320 +++
 include/dt-bindings/clk/msm-mmcc-8960.h            |  137 +
 include/dt-bindings/reset/msm-gcc-8960.h           |   63 +
 include/dt-bindings/reset/msm-gcc-8974.h           |   96 +
 include/dt-bindings/reset/msm-mmcc-8960.h          |   93 +
 include/linux/clk-provider.h                       |   35 +
 include/linux/reset-controller.h                   |    1 +
 28 files changed, 10237 insertions(+), 21 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.txt
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,mmcc.txt
 create mode 100644 drivers/clk/msm/Kconfig
 create mode 100644 drivers/clk/msm/Makefile
 create mode 100644 drivers/clk/msm/clk-branch.c
 create mode 100644 drivers/clk/msm/clk-branch.h
 create mode 100644 drivers/clk/msm/clk-pll.c
 create mode 100644 drivers/clk/msm/clk-pll.h
 create mode 100644 drivers/clk/msm/clk-rcg.c
 create mode 100644 drivers/clk/msm/clk-rcg.h
 create mode 100644 drivers/clk/msm/clk-rcg2.c
 create mode 100644 drivers/clk/msm/gcc-8960.c
 create mode 100644 drivers/clk/msm/gcc-8974.c
 create mode 100644 drivers/clk/msm/mmcc-8960.c
 create mode 100644 drivers/clk/msm/reset.c
 create mode 100644 drivers/clk/msm/reset.h
 create mode 100644 include/dt-bindings/clk/msm-gcc-8960.h
 create mode 100644 include/dt-bindings/clk/msm-gcc-8974.h
 create mode 100644 include/dt-bindings/clk/msm-mmcc-8960.h
 create mode 100644 include/dt-bindings/reset/msm-gcc-8960.h
 create mode 100644 include/dt-bindings/reset/msm-gcc-8974.h
 create mode 100644 include/dt-bindings/reset/msm-mmcc-8960.h

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

Adding clocks from a kernel module can cause a NULL pointer dereference if the parent of a clock is added after the clock is added. This happens because __clk_init() iterates over the list of orphans and reparents the orphans to the clock being registered before creating the debugfs entry for the clock. Create the debugfs entry first before reparenting the orphans.

Unable to handle kernel NULL pointer dereference at virtual address 00000028
pgd = ef3e4000
[00000028] *pgd=bf810831
Internal error: Oops: 17 [#1] PREEMPT SMP ARM
Modules linked in: mmcc_8960(+)
CPU: 0 PID: 52 Comm: modprobe Not tainted 3.12.0-rc2-00023-g1021a28-dirty #659
task: ef319200 ti: ef3a6000 task.ti: ef3a6000
PC is at lock_rename+0x24/0xc4
LR is at debugfs_rename+0x34/0x208
pc : [<c0317238>]    lr : [<c047dfe4>]    psr: 00000013

sp : ef3a7b88 ip : ef3a7ba8 fp : ef3a7ba4
r10: ef3d51cc r9 : ef3bc680 r8 : ef3d5210
r7 : ef3bc640 r6 : eee287e0 r5 : eee287e0 r4 : 00000000 r3 : ef3bc640 r2 : 00000000 r1 : eee287e0 r0 : 00000000
Flags: nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c5787d Table: af3e406a DAC: 00000015 Process modprobe (pid: 52, stack limit = 0xef3a6240)

Stack: (0xef3a7b88 to 0xef3a8000)

7b80: ef3bc640 ee4047e0 00000000 eee287e0 ef3a7bec ef3a7ba8
7ba0: c047dfe4 c0317220 ef3bc680 ef3d51cc ef3a7bdc ef3a7bc0 c06e29d0 c0268784
7bc0: c08946e8 ef3d5210 00000000 ef3bc700 ef3d5290 ef3d5210 ef3bc680 ef3d51cc
7be0: ef3a7c0c ef3a7bf0 c05b9e9c c047dfbc 00000000 00000000 ef3d5210 ef3d5290
7c00: ef3a7c24 ef3a7c10 c05baebc c05b9e30 00000001 00000001 ef3a7c64 ef3a7c28
7c20: c05bb124 c05bae9c bf000cd8 ef3bc7c0 000000d0 c0ff129c bf001774 00000002
7c40: ef3bc740 ef3d5290 ef0f9a10 bf001774 bf00042c 00000061 ef3a7c8c ef3a7c68
7c60: c05bb480 c05baed8 bf001774 ef3d5290 ef0f9a10 bf001774 ef38bc10 ef0f9a00
7c80: ef3a7cac ef3a7c90 c05bb5a8 c05bb3a0 bf001774 00000062 ef0f9a10 ef38bc18
7ca0: ef3a7cec ef3a7cb0 bf00010c c05bb56c 00000000 ef38ba00 00000000 ef3d60d0
7cc0: ef3a7cdc c0fefc24 ef0f9a10 c0a091c0 bf000d24 00000000 bf0029f0 bf006000
7ce0: ef3a7cfc ef3a7cf0 c05156c0 bf000040 ef3a7d2c ef3a7d00 c0513f5c c05156a8
7d00: ef3a7d2c ef0f9a10 ef0f9a10 bf000d24 ef0f9a44 c09ca588 00000000 bf006000
7d20: ef3a7d4c ef3a7d30 c05142b8 c0513ecc ef0fd25c 00000000 bf000d24 c0514214
7d40: ef3a7d74 ef3a7d50 c0512030 c0514220 ef0050a8 ef0fd250 ef0050f8 bf000d24
7d60: ef37c100 c09ed150 ef3a7d84 ef3a7d78 c05139c8 c0511fd8 ef3a7
7d80: c051344c c05139a8 bf000864 c09ca588 ef3a7db4 bf000d24 bf002
7da0: c09ca588 00000000 ef3a7dcc ef3a7db8 c05149dc c0513360 ef3a7
7dc0: ef3a7ddc ef3a7dd0 c0515914 c0514960 ef3a7dec ef3a7de0 bf006
7de0: ef3a7e74 ef3a7df0 c0208800 bf00600c ef3a7e1c ef3a7e00 c04c5
7e00: ffffffff c09d46c4 00000000 bf0029a8 ef3a7e34 ef3a7e20 c024c
7e20: ffffffff c09d46c4 ef3a7e5c ef3a7e38 c024e2fc c024ce40 00000
7e40: ef3a7f48 bf0029b4 bf0029a8 271aeb1c ef3a7f48 bf0029a8 00000001 ef383c00
7e60: bf0029f0 00000001 ef3a7f3c ef3a7e78 c028fac4 c0208718 bf0029b4 00007fff
7e80: c028cd58 000000d2 f0065000 00000000 ef3a7ebc 00000000 00000000 bf0029b4
7ea0: 00000000 bf0029ac bf0029b4 ef3a6000 ef3a7efc c08bf128 00000000 00000000
7ec0: 00000000 00000000 00000000 00000000 6e72656b 00006c65 00000000 00000000
7ee0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
7f00: 00000000 00000000 00000000 271aeb1c ef3a7f2c 00016376 b6f38008 001d3774
7f20: 00000080 c020f968 ef3a6000 00000000 ef3a7fa4 ef3a7f40 c02904dc c028e178
7f40: c020f898 010ccfa8 f0065000 00016376 f0073f60 f0073d7d f007a1e8 00002b24
7f60: 000039e4 00000000 00000000 00000000 0000002f 00000030 00000019 00000016
7f80: 00000012 00000000 00000000 010de1b2 b6f38008 010ccfa8 00000000 ef3a7fa8
7fa0: c020f6c0 c0290434 010de1b2 b6f38008 b6f38008 00016376 001d3774 00000000
7fc0: 010de1b2 b6f38008 010ccfa8 00000080 010de1b2 bedb6f90 010de1c9 0001d8dc
7fe0: 0000000c bedb674c 0001ce30 000094c4 60000010 b6f38008 00000008 0000001d
[<c0317238>] (lock_rename+0x24/0xc4) from [<c047dfe4>] (debugfs_rename+0x34/0x208)
[<c047dfe4>] (debugfs_rename+0x34/0x208) from [<c05b9e9c>] (clk_debug_reparent+0x78/0xc0) [<c05baebc>] (__clk_reparent+0x2c/0x3c) from [<c05bb124>] (__clk_init+0x258/0x4c8)
[<c05bb124>] (__clk_init+0x258/0x4c8) from [<c05bb480>] (_clk_register+0xec/0x1cc)
[<c05bb480>] (_clk_register+0xec/0x1cc) from [<c05bb5a8>] (devm_clk_register+0x48/0x7c)
[<c05bb5a8>] (devm_clk_register+0x48/0x7c) from [<bf00010c>] (msm_mmcc_8960_probe+0xd8/0x190 [mmcc_8960]) [<bf00010c>] (msm_mmcc_8960_probe+0xd8/0x190 [mmcc_8960]) from [<c05156c0>] (platform_drv_probe+0x24/0x28) [<c05156c0>] (platform_drv_probe+0x24/0x28) from [<c0513f5c>] (driver_probe_device+0x9c/0x354) [<c0513f5c>] (driver_probe_device+0x9c/0x354) from [<c05142b8>] (__driver_attach+0xa4/0xa8) [<c05142b8>] (__driver_attach+0xa4/0xa8) from [<c0512030>] (bus_for_each_dev+0x64/0x98)
[<c0512030>] (bus_for_each_dev+0x64/0x98) from [<c05139c8>] (driver_attach+0x2c/0x30)
[<c05139c8>] (driver_attach+0x2c/0x30) from [<c051344c>] (bus_add_driver+0xf8/0x2a8)
[<c051344c>] (bus_add_driver+0xf8/0x2a8) from [<c05149dc>] (driver_register+0x88/0x104)
[<c05149dc>] (driver_register+0x88/0x104) from [<c0515914>] (__platform_driver_register+0x58/0x6c) [<c0515914>] (__platform_driver_register+0x58/0x6c) from [<bf006018>] (msm_mmcc_8960_driver_init+0x18/0x24 [mmcc_8960]) [<bf006018>] (msm_mmcc_8960_driver_init+0x18/0x24 [mmcc_8960]) from [<c0208800>] (do_one_initcall+0xf4/0x1b8) [<c0208800>] (do_one_initcall+0xf4/0x1b8) from [<c028fac4>] (load_module+0x1958/0x22bc)
[<c028fac4>] (load_module+0x1958/0x22bc) from [<c02904dc>] (SyS_init_module+0xb4/0x120)
[<c02904dc>] (SyS_init_module+0xb4/0x120) from [<c020f6c0>] (ret_fast_syscall+0x0/0x48)

Code: e1500001 e1a04000 e1a05001 0a000021 (e5903028)

---
 drivers/clk/clk.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

index a004769..fbb5d59 100644
@@ -1737,6 +1737,7 @@ int __clk_init(struct device *dev, struct clk *clk)
 	else
 		clk->rate = 0;
 
+	clk_debug_register(clk);
 	/*
 	 * walk the list of orphan clocks and reparent any that are children of
 	 * this clock

@@ -1767,8 +1768,6 @@ int __clk_init(struct device *dev, struct clk *clk)
 	if (clk->ops->init)
 		clk->ops->init(clk->hw);
 
-	clk_debug_register(clk);
-
 out:
 	clk_prepare_unlock();
 

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

Quoting Stephen Boyd (2013-10-16 00:40:03)

Taken into clk-next. Thanks!

Mike

If a user of <linux/reset-controller.h> doesn't include <linux/of.h> before including reset-controller.h they'll get a warning as follows:

include/linux/reset-controller.h:44:17:
warning: 'struct of_phandle_args' declared inside parameter list

This is because of_phandle_args is not forward declared. Add the declaration to silence this warning.

---
 include/linux/reset-controller.h | 1 +
 1 file changed, 1 insertion(+)

index 2f61311..41a4695 100644
@@ -21,6 +21,7 @@ struct reset_control_ops {
 
 struct module;
 struct device_node;
+struct of_phandle_args;
 
 /**
  * struct reset_controller_dev - reset controller entity that might

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

Add support to the clock core so that drivers can pass in a regmap. If no regmap is specified try to query the device that's registering the clock for its regmap. This should allow drivers to use the core regmap helpers.

---
 drivers/clk/clk.c            | 8 ++++++++
 include/linux/clk-provider.h | 7 +++++++
 2 files changed, 15 insertions(+)

index fbb5d59..8042c00 100644
@@ -20,6 +20,7 @@
 #include <linux/device.h>
 #include <linux/init.h>
 #include <linux/sched.h>
+#include <linux/regmap.h>
 
 static DEFINE_SPINLOCK(enable_lock);
 static DEFINE_MUTEX(prepare_lock);

@@ -1828,6 +1829,13 @@ static int _clk_register(struct device *dev, struct clk_hw *hw, struct clk *clk)
 	clk->num_parents = hw->init->num_parents;
 	hw->clk = clk;
 
+	if (hw->init->regmap)
+		hw->regmap = hw->init->regmap;
+	else if (dev && dev_get_regmap(dev, NULL))
+		hw->regmap = dev_get_regmap(dev, NULL);
+	else if (dev->parent)
+		hw->regmap = dev_get_regmap(dev->parent, NULL);
+
 	/* allocate local copy in case parent_names is __initdata */
 	clk->parent_names = kzalloc((sizeof(char*) * clk->num_parents),
 			GFP_KERNEL);

index 73bdb69..6ed62f1 100644
@@ -142,6 +142,8 @@ struct clk_ops {
 	void		(*init)(struct clk_hw *hw);
 };
 
+struct regmap;
+
 /**
  * struct clk_init_data - holds init data that's common to all clocks and is
  * shared between the clock provider and the common clock framework.

@@ -151,6 +153,7 @@ struct clk_ops {
  * @parent_names: array of string names for all possible parents
  * @num_parents: number of possible parents
  * @flags: framework-level hints and quirks
+ * @regmap: regmap to use for regmap helpers and/or by providers
  */
 struct clk_init_data {
 	const char		*name;

@@ -158,6 +161,7 @@ struct clk_init_data {
 	const char		**parent_names;
 	u8			num_parents;
 	unsigned long		flags;
+	struct regmap		*regmap;
 };
 
 /**

@@ -171,10 +175,13 @@ struct clk_init_data {
  *
  * @init: pointer to struct clk_init_data that contains the init data shared
  * with the common clock framework.
+ *
+ * @regmap: regmap to use for regmap helpers and/or by providers
  */
 struct clk_hw {
 	struct clk *clk;
 	const struct clk_init_data *init;
+	struct regmap *regmap;
 };
 
 /*

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

The clock framework already has support for simple gate clocks but if drivers want to use the gate clock functionality they need to wrap the gate clock in another struct and chain the ops by calling the gate ops from their own custom ops. Plus the gate clock implementation only supports MMIO accessors so other bus type clocks don't benefit from the potential code reuse. Add some simple regmap helpers for enable/disable/is_enabled that drivers can use as drop in replacements for their clock ops or as simple functions they call from their own custom ops.

---
 drivers/clk/clk.c            | 70 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-provider.h | 13 ++++++++
 2 files changed, 83 insertions(+)

index 8042c00..7cc8cb0 100644
@@ -742,6 +742,76 @@ out:
 	return best;
 }
 
+/**
+ * clk_is_enabled_regmap - standard is_enabled() for regmap users
+ *
+ * @hw: clk to operate on
+ *
+ * Clocks that use regmap for their register I/O can set the
+ * enable_reg and enable_mask fields in their struct clk_hw and then use
+ * this as their is_enabled operation, saving some code.
+ */
+int clk_is_enabled_regmap(struct clk_hw *hw)
+{
+	unsigned int val;
+	int ret;
+
+	ret = regmap_read(hw->regmap, hw->enable_reg, &val);
+	if (ret != 0)
+		return ret;
+
+	if (hw->enable_is_inverted)
+		return (val & hw->enable_mask) == 0;
+	else
+		return (val & hw->enable_mask) != 0;
+}
+EXPORT_SYMBOL_GPL(clk_is_enabled_regmap);
+
+/**
+ * clk_enable_regmap - standard enable() for regmap users
+ *
+ * @hw: clk to operate on
+ *
+ * Clocks that use regmap for their register I/O can set the
+ * enable_reg and enable_mask fields in their struct clk_hw and then use
+ * this as their enable() operation, saving some code.
+ */
+int clk_enable_regmap(struct clk_hw *hw)
+{
+	unsigned int val;
+
+	if (hw->enable_is_inverted)
+		val = 0;
+	else
+		val = hw->enable_mask;
+
+	return regmap_update_bits(hw->regmap, hw->enable_reg,
+				  hw->enable_mask, val);
+}
+EXPORT_SYMBOL_GPL(clk_enable_regmap);
+
+/**
+ * clk_disable_regmap - standard disable() for regmap users
+ *
+ * @hw: clk to operate on
+ *
+ * Clocks that use regmap for their register I/O can set the
+ * enable_reg and enable_mask fields in their struct clk_hw and then use
+ * this as their disable() operation, saving some code.
+ */
+void clk_disable_regmap(struct clk_hw *hw)
+{
+	unsigned int val;
+
+	if (hw->enable_is_inverted)
+		val = hw->enable_mask;
+	else
+		val = 0;
+
+	regmap_update_bits(hw->regmap, hw->enable_reg, hw->enable_mask, val);
+}
+EXPORT_SYMBOL_GPL(clk_disable_regmap);
+
 /***        clk api        ***/
 
 void __clk_unprepare(struct clk *clk)

index 6ed62f1..4087a9b 100644
@@ -177,11 +177,21 @@ struct clk_init_data {
  * with the common clock framework.
  *
  * @regmap: regmap to use for regmap helpers and/or by providers
+ *
+ * @enable_reg: register when using regmap enable/disable ops
+ *
+ * @enable_mask: mask when using regmap enable/disable ops
+ *
+ * @enable_is_inverted: flag to indicate set enable_mask bits to disable
+ *                      when using clock_enable_regmap and friends APIs.
  */
 struct clk_hw {
 	struct clk *clk;
 	const struct clk_init_data *init;
 	struct regmap *regmap;
+	unsigned int enable_reg;
+	unsigned int enable_mask;
+	bool enable_is_inverted;
 };
 
 /*

@@ -447,6 +457,9 @@ struct clk *__clk_lookup(const char *name);
 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
 			      unsigned long *best_parent_rate,
 			      struct clk **best_parent_p);
+int clk_is_enabled_regmap(struct clk_hw *hw);
+int clk_enable_regmap(struct clk_hw *hw);
+void clk_disable_regmap(struct clk_hw *hw);
 
 /*
  * FIXME clock api without lock protection

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

Quoting Stephen Boyd (2013-10-16 00:40:06)

Wasn't the idea to extend the set of register accessor routines in <linux/clk-provider.h> such that memory mapped I/O as well as regmap style becomes possible? This is what I understood from past iterations of discussing this approach.

I agree that duplicating the clock gate's implementation just to access the register in a different way feels strange and somehow unfortunate.

There still may be the issue of expensive operations only being allowed within prepare and unprepare, while enable and disable are supposed to be "cheap and straight forward", and should not block and thus may not use external communication. But that appears to be orthogonal to the API which wraps register access.

virtually yours
Gerhard Sittig

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

Just FYI and to have the pointer in some archive: Had a look at recent threads because it appears that several pending changes have similar needs to adjust the kind of hardware access, while sharing common code to handle the actual clock item logic would be desirable.

Please check "[PATCHv12 00/49] ARM: TI SoC clock DT conversion" from Tero Kristo as of 2013-12-20, which "in bypassing" introduces low level ops for register access (patches 06 and following). I suggested to separate this hardware access aspect out of the "TI SoC clock" series (almost missed the fact that it changes behaviour in common code), and to add regmap support or at least allow to do regmap on top of the ll_ops infrastructure.

With the proposed generic approach all of us should be happy. The vast amount of ARM code should not experience any change, the queued PowerPC support can keep working, new TI SoC clocks can get implemented, Steven you can get regmap access, and more platforms may use the common code even if readl()/writel() won't fit them. Let's followup in Tero's v12 feedback thread to make that happen.

virtually yours
Gerhard Sittig

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

These new members aren't exclusively for use by the regmap code. For example, we could extend the gate clock implementation to store the enable bit in the 'enable_mask' member. They also aren't used exclusively by simple gates. If you look at this patch series you'll see that I call the helpers from hardware specific ops when I want to do the gate operation in addition to something else like polling a status bit.

What is the concern though? I can only guess that perhaps not every clock type will have a bit to toggle and so putting the information here would unnecessarily penalize those clocks? How many clocks in a particular system don't have an on/off capability? On MSM hardware I can only count 5 or so out of 200 that don't have on/off capabilities so it didn't seem worth the effort to have a struct inside a struct inside a struct just to save a 100 bytes of data.

If I understand you, I could make clk-regmap.c and struct clk_regmap like so:

	struct clk_regmap {
		struct regmap *regmap;
		unsigned int enable_reg;
		unsigned int enable_mask;
		bool enable_is_inverted;
		struct clk_hw hw;
	};

	int clk_is_enabled_regmap(struct clk_hw *hw)
	{
		...

That certainly avoids adding members to struct clk_hw, but it also means that if we want to use this structure and augment it with something like a status bit poll we need to make a third structure to wrap the clk_regmap struct. That makes me a sad panda.

The reason is because we'll need to add a registration function like clk_regmap_register(). I would like to just have an array of clk_hw pointers that I iterate through and call clk_register() on, without having to think/worry that this clock is a basic clock that doesn't use a regmap so I should call clk_register() and this other clock is wrapping a clk_regmap struct so I need to call clk_regmap_register(). I guess I could have more arrays or pair the clk_hw pointers with some registration function pointer, but that doesn't make me feel much better.

In the regulator framework we have helpers.c. I could make a similar file for these very similar helpers.

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hosted by The Linux Foundation

Some of Qualcomm's clocks can change their parent and rate at the same time with a single register write. Add support for this hardware to the common clock framework by adding a new set_rate_and_parent() op. When the clock framework determines that both the parent and the rate are going to change during clk_set_rate() it will call the .set_rate_and_parent() op if available and fall back to calling .set_parent() followed by .set_rate() otherwise.

---
 Documentation/clk.txt        |  3 ++
 drivers/clk/clk.c            | 78 +++++++++++++++++++++++++++++++++-----------
 include/linux/clk-provider.h | 15 +++++++++
 3 files changed, 77 insertions(+), 19 deletions(-)

index 3aeb5c4..79700ea 100644
@@ -77,6 +77,9 @@ the operations defined in clk.h:
 		int		(*set_parent)(struct clk_hw *hw, u8 index);
 		u8		(*get_parent)(struct clk_hw *hw);
 		int		(*set_rate)(struct clk_hw *hw, unsigned long);
+		int		(*set_rate_and_parent)(struct clk_hw *hw,
+					    unsigned long rate,
+					    unsigned long parent_rate, u8 index);
 		void		(*init)(struct clk_hw *hw);
 	};
 

index 4087a9b..2bd6617 100644
@@ -108,6 +108,18 @@ struct clk_hw;
  *		which is likely helpful for most .set_rate implementation.
  *		Returns 0 on success, -EERROR otherwise.
  *
+ * @set_rate_and_parent: Change the rate and the parent of this clock. The
+ *		requested rate is specified by the second argument, which
+ *		should typically be the return of .round_rate call.  The
+ *		third argument gives the parent rate which is likely helpful
+ *		for most .set_rate_and_parent implementation. The fourth
+ *		argument gives the parent index. This callback is optional (and
+ *		unnecessary) for clocks with 0 or 1 parents as well as
+ *		for clocks that can tolerate switching the rate and the parent
+ *		separately via calls to .set_parent and .set_rate.
+ *		Returns 0 on success, -EERROR otherwise.
+ *
+ *
  * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
  * implementations to split any work between atomic (enable) and sleepable
  * (prepare) contexts.  If enabling a clock requires code that might sleep,

@@ -139,6 +151,9 @@ struct clk_ops {
 	u8		(*get_parent)(struct clk_hw *hw);
 	int		(*set_rate)(struct clk_hw *hw, unsigned long,
 				    unsigned long);
+	int		(*set_rate_and_parent)(struct clk_hw *hw,
+				    unsigned long rate,
+				    unsigned long parent_rate, u8 index);
 	void		(*init)(struct clk_hw *hw);
 };
 

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hosted by The Linux Foundation

Add support for MSM's PLLs (phase locked loops). This is sufficient enough to be able to determine the rate the PLL is running at. We can add rate setting support later when it's needed.

---
 drivers/clk/Kconfig       |   2 +
 drivers/clk/Makefile      |   1 +
 drivers/clk/msm/Kconfig   |   5 ++
 drivers/clk/msm/Makefile  |   3 +
 drivers/clk/msm/clk-pll.c | 145 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/msm/clk-pll.h |  47 +++++++++++++++
 6 files changed, 203 insertions(+)
 create mode 100644 drivers/clk/msm/Kconfig
 create mode 100644 drivers/clk/msm/Makefile
 create mode 100644 drivers/clk/msm/clk-pll.c
 create mode 100644 drivers/clk/msm/clk-pll.h

index 279407a..efb7606 100644
@@ -93,6 +93,8 @@ config CLK_PPC_CORENET
 	  This adds the clock driver support for Freescale PowerPC corenet
 	  platforms using common clock framework.
 
+source "drivers/clk/msm/Kconfig"
+
 endmenu
 
 source "drivers/clk/mvebu/Kconfig"

index 7b11106..6838b07 100644
@@ -20,6 +20,7 @@ obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
 obj-$(CONFIG_ARCH_SIRF)		+= clk-prima2.o
+obj-$(CONFIG_COMMON_CLK_MSM)	+= msm/
 obj-$(CONFIG_PLAT_ORION)	+= mvebu/
 ifeq ($(CONFIG_COMMON_CLK), y)
 obj-$(CONFIG_ARCH_MMP)		+= mmp/

new file mode 100644
index 0000000..91558ce
@@ -0,0 +1,5 @@
+config COMMON_CLK_MSM
+	tristate "Support for Qualcomm's MSM designs"
+	depends on OF
+	select REGMAP_MMIO
+

new file mode 100644
index 0000000..16b750f
@@ -0,0 +1,3 @@
+obj-$(CONFIG_COMMON_CLK_MSM) += clk-msm.o
+
+clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-pll.o

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hosted by The Linux Foundation

Add support for the root clock generators on MSM devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate.

---
 drivers/clk/msm/Makefile   |   2 +
 drivers/clk/msm/clk-rcg.c  | 517 +++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/msm/clk-rcg.h  | 157 ++++++++++++++
 drivers/clk/msm/clk-rcg2.c | 270 +++++++++++++++++++++++
 4 files changed, 946 insertions(+)
 create mode 100644 drivers/clk/msm/clk-rcg.c
 create mode 100644 drivers/clk/msm/clk-rcg.h
 create mode 100644 drivers/clk/msm/clk-rcg2.c

index 16b750f..fb78ac9 100644
@@ -1,3 +1,5 @@
 obj-$(CONFIG_COMMON_CLK_MSM) += clk-msm.o
 
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-pll.o
+clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg.o
+clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg2.o

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hosted by The Linux Foundation

---
 drivers/clk/msm/Makefile     |   1 +
 drivers/clk/msm/clk-branch.c | 152 +++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/msm/clk-branch.h |  52 +++++++++++++++
 3 files changed, 205 insertions(+)
 create mode 100644 drivers/clk/msm/clk-branch.c
 create mode 100644 drivers/clk/msm/clk-branch.h

index fb78ac9..e1cee29 100644
@@ -3,3 +3,4 @@ obj-$(CONFIG_COMMON_CLK_MSM) += clk-msm.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-pll.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg2.o
+clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-branch.o

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hosted by The Linux Foundation

Reset controllers and clock controllers are combined into one IP block on qualcomm chipsets. Usually a reset signal is associated with each clock branch but sometimes a reset signal is associated with a handful of clocks. Either way the register interface is the same; set a bit to assert a reset and clear a bit to deassert a reset. Add support for these types of resets signals.

---
 drivers/clk/msm/Kconfig  |  1 +
 drivers/clk/msm/Makefile |  1 +
 drivers/clk/msm/reset.c  | 63 ++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/msm/reset.h  | 37 ++++++++++++++++++++++++++++
 4 files changed, 102 insertions(+)
 create mode 100644 drivers/clk/msm/reset.c
 create mode 100644 drivers/clk/msm/reset.h

index 91558ce..5229c7e 100644
@@ -2,4 +2,5 @@ config COMMON_CLK_MSM
 	tristate "Support for Qualcomm's MSM designs"
 	depends on OF
 	select REGMAP_MMIO
+	select RESET_CONTROLLER
 

index e1cee29..8e4c799 100644
@@ -4,3 +4,4 @@ clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-pll.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg2.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-branch.o
+clk-msm-$(CONFIG_COMMON_CLK_MSM) += reset.o

new file mode 100644
index 0000000..09de265
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MSM_CLK_RESET_H__
+#define __MSM_CLK_RESET_H__
+
+#include <linux/reset-controller.h>
+
+struct msm_reset_map {
+	unsigned int reg;
+	u8 bit;
+};
+
+struct regmap;
+
+struct msm_reset_controller {
+	const struct msm_reset_map *reset_map;
+	struct regmap *regmap;
+	struct reset_controller_dev rcdev;
+};
+
+#define to_msm_reset_controller(r) \
+	container_of(r, struct msm_reset_controller, rcdev);
+
+extern struct reset_control_ops msm_reset_ops;
+
+#endif

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hosted by The Linux Foundation

Add a driver for the global clock controller found on MSM8960 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks.

---
 .../devicetree/bindings/clock/qcom,gcc.txt         |   21 +
 drivers/clk/msm/Kconfig                            |    7 +
 drivers/clk/msm/Makefile                           |    2 +
 drivers/clk/msm/gcc-8960.c                         | 2929 ++++++++++++++++++++
 include/dt-bindings/clk/msm-gcc-8960.h             |  313 +++
 include/dt-bindings/reset/msm-gcc-8960.h           |   63 +
 6 files changed, 3335 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.txt
 create mode 100644 drivers/clk/msm/gcc-8960.c
 create mode 100644 include/dt-bindings/clk/msm-gcc-8960.h
 create mode 100644 include/dt-bindings/reset/msm-gcc-8960.h

new file mode 100644
index 0000000..66d2fcd
@@ -0,0 +1,21 @@
+MSM Global Clock & Reset Controller Binding
+-------------------------------------------
+
+Required properties :
+- compatible : shall contain at least "qcom,gcc" and only one of the
+	       following:
+
+			"qcom,gcc-8660"
+			"qcom,gcc-8960"
+
+- reg : shall contain base register location and length
+- #clock-cells : shall contain 1
+- #reset-cells : shall contain 1
+
+Example:
+	clock-controller at 900000 {
+		compatible = "qcom,gcc-8960", "qcom,gcc";
+		reg = <0x900000 0x4000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};

index 5229c7e..d44e171 100644
@@ -4,3 +4,10 @@ config COMMON_CLK_MSM
 	select REGMAP_MMIO
 	select RESET_CONTROLLER
 
+config MSM_GCC_8960
+	tristate "MSM8960 Global Clock Controller"
+	depends on COMMON_CLK_MSM
+	help
+	  Support for the global clock controller on msm8960 devices.
+	  Say Y if you want to use peripheral devices such as UART, SPI,
+	  i2c, USB, SD/eMMC, SATA, PCIe, etc.

index 8e4c799..f41bf023 100644
@@ -5,3 +5,5 @@ clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-rcg2.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-branch.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += reset.o
+
+obj-$(CONFIG_MSM_GCC_8960) += gcc-8960.o

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hosted by The Linux Foundation

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Add a driver for the multimedia clock controller found on MSM 8960 based platforms. This should allow multimedia device drivers to probe and control their clocks.

---
 .../devicetree/bindings/clock/qcom,mmcc.txt        |   21 +
 drivers/clk/msm/Kconfig                            |    9 +
 drivers/clk/msm/Makefile                           |    1 +
 drivers/clk/msm/mmcc-8960.c                        | 2129 ++++++++++++++++++++
 include/dt-bindings/clk/msm-mmcc-8960.h            |  137 ++
 include/dt-bindings/reset/msm-mmcc-8960.h          |   93 +
 6 files changed, 2390 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,mmcc.txt
 create mode 100644 drivers/clk/msm/mmcc-8960.c
 create mode 100644 include/dt-bindings/clk/msm-mmcc-8960.h
 create mode 100644 include/dt-bindings/reset/msm-mmcc-8960.h

new file mode 100644
index 0000000..928fdd3
@@ -0,0 +1,21 @@
+MSM Multimedia Clock Controller Binding
+-----------------------------------------
+
+Required properties :
+- compatible : shall contain at least "qcom,mmcc" and only one of the
+	       following:
+
+			"qcom,mmcc-8660"
+			"qcom,mmcc-8960"
+
+- reg : shall contain base register location and length
+- #clock-cells : shall contain 1
+- #reset-cells : shall contain 1
+
+Example:
+	clock-controller at 4000000 {
+		compatible = "qcom,mmcc-8960", "qcom,mmcc";
+		reg = <0x4000000 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};

index d44e171..c3b35ca 100644
@@ -11,3 +11,12 @@ config MSM_GCC_8960
 	  Support for the global clock controller on msm8960 devices.
 	  Say Y if you want to use peripheral devices such as UART, SPI,
 	  i2c, USB, SD/eMMC, SATA, PCIe, etc.
+
+config MSM_MMCC_8960
+	tristate "MSM8960 Multimedia Clock Controller"
+	select MSM_GCC_8960
+	depends on COMMON_CLK_MSM
+	help
+	  Support for the multimedia clock controller on msm8960 devices.
+	  Say Y if you want to support multimedia devices such as display,
+	  graphics, video encode/decode, camera, etc.

index f41bf023..c3b4a31 100644
@@ -7,3 +7,4 @@ clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-branch.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += reset.o
 
 obj-$(CONFIG_MSM_GCC_8960) += gcc-8960.o
+obj-$(CONFIG_MSM_MMCC_8960) += mmcc-8960.o

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hosted by The Linux Foundation

Add a driver for the global clock controller found on MSM 8974 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks.

---
 .../devicetree/bindings/clock/qcom,gcc.txt         |    1 +
 drivers/clk/msm/Kconfig                            |    8 +
 drivers/clk/msm/Makefile                           |    1 +
 drivers/clk/msm/gcc-8974.c                         | 2453 ++++++++++++++++++++
 include/dt-bindings/clk/msm-gcc-8974.h             |  320 +++
 include/dt-bindings/reset/msm-gcc-8974.h           |   96 +
 6 files changed, 2879 insertions(+)
 create mode 100644 drivers/clk/msm/gcc-8974.c
 create mode 100644 include/dt-bindings/clk/msm-gcc-8974.h
 create mode 100644 include/dt-bindings/reset/msm-gcc-8974.h

index 66d2fcd..9aa7347 100644
@@ -7,6 +7,7 @@ Required properties :
 
 			"qcom,gcc-8660"
 			"qcom,gcc-8960"
+			"qcom,gcc-8974"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1

index c3b35ca..52f0722 100644
@@ -20,3 +20,11 @@ config MSM_MMCC_8960
 	  Support for the multimedia clock controller on msm8960 devices.
 	  Say Y if you want to support multimedia devices such as display,
 	  graphics, video encode/decode, camera, etc.
+
+config MSM_GCC_8974
+	tristate "MSM8974 Global Clock Controller"
+	depends on COMMON_CLK_MSM
+	help
+	  Support for the global clock controller on msm8974 devices.
+	  Say Y if you want to use peripheral devices such as UART, SPI,
+	  i2c, USB, SD/eMMC, SATA, PCIe, etc.

index c3b4a31..433490b 100644
@@ -7,4 +7,5 @@ clk-msm-$(CONFIG_COMMON_CLK_MSM) += clk-branch.o
 clk-msm-$(CONFIG_COMMON_CLK_MSM) += reset.o
 
 obj-$(CONFIG_MSM_GCC_8960) += gcc-8960.o
+obj-$(CONFIG_MSM_GCC_8974) += gcc-8974.o
 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-8960.o

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hosted by The Linux Foundation