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mx6: soc: Staticize set_vddsoc()

PATCH Superseded Fabio Estevam 2 participants 8 messages Dec 19, 2013 – Dec 26, 2013

Subsystems (2)
Arm (32-bit) Arm i.MX and Layerscape

v1 of 2 Superseded Latest is v2 →

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Fabio Estevam

author reviewer
#0 lore raw

PATCH 1/6 mx6: soc: Staticize set_vddsoc()

From: Fabio Estevam <[email protected]>

set_vddsoc() is not used anywhere else, so make it static.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c              | 2 +-
 arch/arm/include/asm/arch-mx6/sys_proto.h | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)
arch/arm/cpu/armv7/mx6/soc.c +1 -1
index a390296..6cbade7 100644
@@ -101,7 +101,7 @@ void init_aips(void)
  * Possible values are from 0.725V to 1.450V in steps of
  * 0.025V (25mV).
  */
-void set_vddsoc(u32 mv)
+static void set_vddsoc(u32 mv)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	u32 val, reg = readl(&anatop->reg_core);
arch/arm/include/asm/arch-mx6/sys_proto.h +0 -2
index 8c21364..17125a6 100644
@@ -29,8 +29,6 @@ u32 get_cpu_rev(void);
 const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
 
-void set_vddsoc(u32 mv);
-
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
Signature · 1 line
1.8.1.2
author reviewer
#1 lore raw

PATCH 2/6 mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltages

From: Fabio Estevam <[email protected]>

Since ROM may modify the LDO ramp up time according to fuse setting, it is safer to reset the ramp up field to its default value of 00:

00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;

Signed-off-by Anson Huang <[email protected]>
Signed-off-by Jason Liu <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
arch/arm/cpu/armv7/mx6/soc.c +16 -0
index 6cbade7..13b9e36 100644
@@ -93,6 +93,20 @@ void init_aips(void)
 	writel(0x00000000, &aips2->opacr4);
 }
 
+static void clear_ldo_ramp(void)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	int reg;
+
+	/* ROM may modify LDO ramp up time according to fuse setting, so in
+	 * order to be in the safe side we neeed to reset these settings to
+	 * match the reset value: 0'b00
+	 */
+	reg = readl(&anatop->ana_misc2);
+	reg &= ~(0x3f << 24);
+	writel(reg, &anatop->ana_misc2);
+}
+
 /*
  * Set the VDDSOC
  *

@@ -113,6 +127,8 @@ static void set_vddsoc(u32 mv)
 	else
 		val = (mv - 700) / 25;
 
+	clear_ldo_ramp();
+
 	/*
 	 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
 	 * and set them to the calculated value (0.7V + val * 0.25V)
Signature · 1 line
1.8.1.2
author reviewer
#2 lore raw

PATCH 3/6 mx6: soc: Set the VDDSOC at 1.175 V

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V. Add a 25 mV margin and set it to 1.175V.

This also matches the VDDSOC voltages for 792MHz operation that the kernel configures:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/cpu/armv7/mx6/soc.c +1 -1
index 13b9e36..0136eb0 100644
@@ -151,7 +151,7 @@ int arch_cpu_init(void)
 {
 	init_aips();
 
-	set_vddsoc(1200);	/* Set VDDSOC to 1.2V */
+	set_vddsoc(1175);	/* Set VDDSOC to 1.175V */
 
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
Signature · 1 line
1.8.1.2
author reviewer
#3 lore raw

PATCH 4/6 mx6: soc: Introduce set_ldo_voltage()

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

Introduce set_ldo_voltage() so that all three LDO regulators can be configured.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c | 33 ++++++++++++++++++++++++++-------
 1 file changed, 26 insertions(+), 7 deletions(-)
arch/arm/cpu/armv7/mx6/soc.c +26 -7
index 0136eb0..ee888ce 100644
@@ -19,6 +19,12 @@
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 
+enum ldo_reg {
+	LDO_ARM,
+	LDO_SOC,
+	LDO_PU,
+};
+
 struct scu_regs {
 	u32	ctrl;
 	u32	config;

@@ -115,10 +121,11 @@ static void clear_ldo_ramp(void)
  * Possible values are from 0.725V to 1.450V in steps of
  * 0.025V (25mV).
  */
-static void set_vddsoc(u32 mv)
+static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	u32 val, reg = readl(&anatop->reg_core);
+	u8 shift;
 
 	if (mv < 725)
 		val = 0x00;	/* Power gated off */

@@ -129,12 +136,24 @@ static void set_vddsoc(u32 mv)
 
 	clear_ldo_ramp();
 
-	/*
-	 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
-	 * and set them to the calculated value (0.7V + val * 0.25V)
-	 */
-	reg = (reg & ~(0x1F << 18)) | (val << 18);
+	switch (ldo) {
+	case LDO_SOC:
+		shift = 18;
+		break;
+	case LDO_PU:
+		shift = 9;
+		break;
+	case LDO_ARM:
+		shift = 0;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	reg = (reg & ~(0x1F << shift)) | (val << shift);
 	writel(reg, &anatop->reg_core);
+
+	return 0;
 }
 
 static void imx_set_wdog_powerdown(bool enable)

@@ -151,7 +170,7 @@ int arch_cpu_init(void)
 {
 	init_aips();
 
-	set_vddsoc(1175);	/* Set VDDSOC to 1.175V */
+	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */
 
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
Signature · 1 line
1.8.1.2
author reviewer
#4 lore raw

PATCH 5/6 mx6: soc: Add the required LDO ramp up delay

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

When changing LDO voltages we need to wait for the required amount of time for the voltage to settle.

Also, as the timer is still not available when arch_cpu_init() is called, we need to call it later at board_postclk_init() phase.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c | 22 +++++++++++++++++++---
 include/configs/mx6_common.h |  1 +
 2 files changed, 20 insertions(+), 3 deletions(-)
arch/arm/cpu/armv7/mx6/soc.c +19 -3
index ee888ce..3aa3bb0 100644
@@ -124,7 +124,7 @@ static void clear_ldo_ramp(void)
 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	u32 val, reg = readl(&anatop->reg_core);
+	u32 val, step, old, reg = readl(&anatop->reg_core);
 	u8 shift;
 
 	if (mv < 725)

@@ -150,9 +150,20 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 		return -EINVAL;
 	}
 
+	old = (reg & (0x1F << shift)) >> shift;
+	step = abs(val - old);
+	if (step == 0)
+		return 0;
+
 	reg = (reg & ~(0x1F << shift)) | (val << shift);
 	writel(reg, &anatop->reg_core);
 
+	/*
+	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
+	 * step
+	 */
+	udelay(3 * step);
+
 	return 0;
 }
 

@@ -170,8 +181,6 @@ int arch_cpu_init(void)
 {
 	init_aips();
 
-	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */
-
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 
 #ifdef CONFIG_APBH_DMA

@@ -182,6 +191,13 @@ int arch_cpu_init(void)
 	return 0;
 }
 
+int board_postclk_init(void)
+{
+	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */
+
+	return 0;
+}
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
include/configs/mx6_common.h +1 -0
index 674bcd3..514d634 100644
@@ -20,5 +20,6 @@
 #define CONFIG_ARM_ERRATA_742230
 #define CONFIG_ARM_ERRATA_743622
 #define CONFIG_ARM_ERRATA_751472
+#define CONFIG_BOARD_POSTCLK_INIT
 
 #endif
Signature · 1 line
1.8.1.2
author reviewer
#5 lore raw

PATCH 6/6 mx6: soc: Disable VDDPU regulator

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power.

Signed-off-by Anson Huang <[email protected]>
Signed-off-by Jason Liu <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c             | 23 +++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/imx-regs.h | 23 +++++++++++++++++++++++
 2 files changed, 46 insertions(+)
arch/arm/cpu/armv7/mx6/soc.c +23 -0
index 9dc30ba..243226e 100644
@@ -19,6 +19,8 @@
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 
+#define VDDPU_MASK	(0x1f << 9)
+
 enum ldo_reg {
 	LDO_ARM,
 	LDO_SOC,

@@ -177,11 +179,32 @@ static void imx_set_wdog_powerdown(bool enable)
 	writew(enable, &wdog2->wmcr);
 }
 
+static void imx_set_vddpu_power_down(void)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
+
+	u32 val;
+
+	/* need to power down xPU in GPC before turning off PU LDO */
+	val = readl(&gpc->gpu_ctrl);
+	writel(val | 0x1, &gpc->gpu_ctrl);
+
+	val = readl(&gpc->ctrl);
+	writel(val | 0x1, &gpc->ctrl);
+	while (readl(&gpc->ctrl) & 0x1)
+		;
+
+	/* disable VDDPU */
+	writel(VDDPU_MASK, &anatop->reg_core_clr);
+}
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+	imx_set_vddpu_power_down();
 
 #ifdef CONFIG_APBH_DMA
 	/* Start APBH DMA */
arch/arm/include/asm/arch-mx6/imx-regs.h +23 -0
index 7ef7152..fb0c4c7 100644
@@ -659,5 +659,28 @@ struct wdog_regs {
 	u16	wmcr;	/* Miscellaneous Control */
 };
 
+struct gpc_regs {
+	u32	ctrl;		/* 0x000 */
+	u32	pgr;		/* 0x004 */
+	u32	imr1;		/* 0x008 */
+	u32	imr2;		/* 0x00c */
+	u32	imr3;		/* 0x010 */
+	u32	imr4;		/* 0x014 */
+	u32	isr1;		/* 0x018 */
+	u32	isr2;		/* 0x01c */
+	u32	isr3;		/* 0x020 */
+	u32	isr4;		/* 0x024 */
+	u32	reserved1[0x86];
+	u32	gpu_ctrl;	/* 0x260 */
+	u32	gpu_pupscr;	/* 0x264 */
+	u32	gpu_pdnscr;	/* 0x268 */
+	u32	gpu_sr;		/* 0x26c */
+	u32	reserved2[0xc];
+	u32	cpu_ctrl;	/* 0x2a0 */
+	u32	cpu_pupscr;	/* 0x2a4 */
+	u32	cpu_pdnscr;	/* 0x2a8 */
+	u32	cpu_sr;		/* 0x2ac */
+};
+
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
Signature · 1 line
1.8.1.2
#6 lore raw

PATCH 6/6 mx6: soc: Disable VDDPU regulator

Hi Fabio,

The PU power-up/power-down sequence has specific steps, includes some clock management. Please refer to the kernel code for the sequence.

Thanks,
Ranjani

-----Original Message-----
From: Fabio Estevam [mailto:festevam at gmail.com]
Sent: Wednesday, December 18, 2013 9:16 PM
To: sbabic at denx.de
Cc: Huang Yongcai-B20788; Liu Hui-R64343; Vaidyanathan Ranjani-RA5478; eric.nelson at boundarydevices.com; troy.kisky at boundarydevices.com; u-boot at lists.denx.de; Estevam Fabio-R49496
Subject: [PATCH 6/6] mx6: soc: Disable VDDPU regulator

From: Fabio Estevam <[email protected]>

As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power.

Signed-off-by Anson Huang <[email protected]>
Signed-off-by Jason Liu <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c             | 23 +++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/imx-regs.h | 23 +++++++++++++++++++++++
 2 files changed, 46 insertions(+)
arch/arm/cpu/armv7/mx6/soc.c +21 -0
@@ -19,6 +19,8 @@
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 
+#define VDDPU_MASK	(0x1f << 9)
+
 enum ldo_reg {
 	LDO_ARM,
 	LDO_SOC,

@@ -177,11 +179,32 @@ static void imx_set_wdog_powerdown(bool enable)
 	writew(enable, &wdog2->wmcr);
 }
 
+static void imx_set_vddpu_power_down(void) {
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
+
+	u32 val;
+
+	/* need to power down xPU in GPC before turning off PU LDO */
+	val = readl(&gpc->gpu_ctrl);
+	writel(val | 0x1, &gpc->gpu_ctrl);
+
+	val = readl(&gpc->ctrl);
+	writel(val | 0x1, &gpc->ctrl);
+	while (readl(&gpc->ctrl) & 0x1)
+		;
+
+	/* disable VDDPU */
+	writel(VDDPU_MASK, &anatop->reg_core_clr); }
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+	imx_set_vddpu_power_down();
 
 #ifdef CONFIG_APBH_DMA
 	/* Start APBH DMA */
arch/arm/include/asm/arch-mx6/imx-regs.h +23 -0
index 7ef7152..fb0c4c7 100644
@@ -659,5 +659,28 @@ struct wdog_regs {
 	u16	wmcr;	/* Miscellaneous Control */
 };
 
+struct gpc_regs {
+	u32	ctrl;		/* 0x000 */
+	u32	pgr;		/* 0x004 */
+	u32	imr1;		/* 0x008 */
+	u32	imr2;		/* 0x00c */
+	u32	imr3;		/* 0x010 */
+	u32	imr4;		/* 0x014 */
+	u32	isr1;		/* 0x018 */
+	u32	isr2;		/* 0x01c */
+	u32	isr3;		/* 0x020 */
+	u32	isr4;		/* 0x024 */
+	u32	reserved1[0x86];
+	u32	gpu_ctrl;	/* 0x260 */
+	u32	gpu_pupscr;	/* 0x264 */
+	u32	gpu_pdnscr;	/* 0x268 */
+	u32	gpu_sr;		/* 0x26c */
+	u32	reserved2[0xc];
+	u32	cpu_ctrl;	/* 0x2a0 */
+	u32	cpu_pupscr;	/* 0x2a4 */
+	u32	cpu_pdnscr;	/* 0x2a8 */
+	u32	cpu_sr;		/* 0x2ac */
+};
+
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */

--
1.8.1.2

author reviewer
#7 lore raw

PATCH 6/6 mx6: soc: Disable VDDPU regulator

Quoted 3 lines · Ranjani.Vaidyanathan at freescale.com

Hi Fabio,

The PU power-up/power-down sequence has specific steps, includes some clock management. Please refer to the kernel code for the sequence.

Thanks for the review, Ranjani.

Just sent v2 that disables vddpu in the same way as in kernel.

Regards,

Fabio Estevam