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imx: Introduce a header for the imx cpu versions

PATCH Superseded Fabio Estevam 1 participant 2 messages Jan 26, 2014

Subsystems (2)
Arm (32-bit) Arm i.MX and Layerscape

v3 of 4 Superseded Latest is v4 →

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Fabio Estevam

author reviewer
#0 lore raw

PATCH v3 1/2 imx: Introduce a header for the imx cpu versions

From: Fabio Estevam <[email protected]>

Instead of duplicating the CPU definitions at mx5 and mx6 sys_proto.h header files, introduce a common header to centralize such definitions.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/include/asm/arch-imx/cpu.h       | 12 ++++++++++++
 arch/arm/include/asm/arch-mx5/sys_proto.h |  7 +------
 arch/arm/include/asm/arch-mx6/sys_proto.h |  8 +-------
 3 files changed, 14 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-imx/cpu.h
arch/arm/include/asm/arch-imx/cpu.h new file +12 -0
new file mode 100644
index 0000000..8c725e2
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define MXC_CPU_MX51		0x51
+#define MXC_CPU_MX53		0x53
+#define MXC_CPU_MX6SL		0x60
+#define MXC_CPU_MX6DL		0x61
+#define MXC_CPU_MX6SOLO		0x62
+#define MXC_CPU_MX6Q		0x63
arch/arm/include/asm/arch-mx5/sys_proto.h +1 -6
index 9949ad1..ac7705b 100644
@@ -8,12 +8,7 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-#define MXC_CPU_MX51		0x51
-#define MXC_CPU_MX53		0x53
-#define MXC_CPU_MX6SL		0x60
-#define MXC_CPU_MX6DL		0x61
-#define MXC_CPU_MX6SOLO		0x62
-#define MXC_CPU_MX6Q		0x63
+#include "../arch-imx/cpu.h"
 
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
arch/arm/include/asm/arch-mx6/sys_proto.h +1 -7
index 17125a6..38851a1 100644
@@ -9,13 +9,7 @@
 #define _SYS_PROTO_H_
 
 #include <asm/imx-common/regs-common.h>
-
-#define MXC_CPU_MX51		0x51
-#define MXC_CPU_MX53		0x53
-#define MXC_CPU_MX6SL		0x60
-#define MXC_CPU_MX6DL		0x61
-#define MXC_CPU_MX6SOLO		0x62
-#define MXC_CPU_MX6Q		0x63
+#include "../arch-imx/cpu.h"
 
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
Signature · 1 line
1.8.1.2
author reviewer
#1 lore raw

PATCH v3 2/2 mx6: Distinguish mx6dual from mx6quad

Currently when we boot a mx6dual U-boot reports that it is a mx6quad.

Report it as MX6D instead:

CPU: Freescale i.MX6D rev1.2 at 792 MHz

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c        | 14 +++++++++++---
 arch/arm/imx-common/cpu.c           |  2 ++
 arch/arm/include/asm/arch-imx/cpu.h |  1 +
 3 files changed, 14 insertions(+), 3 deletions(-)
arch/arm/cpu/armv7/mx6/soc.c +11 -3
index 0208cba..9acd8c9 100644
@@ -41,14 +41,19 @@ u32 get_cpu_rev(void)
 
 	if (type != MXC_CPU_MX6SL) {
 		reg = readl(&anatop->digprog);
+		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+		u32 cfg = readl(&scu->config) & 3;
 		type = ((reg >> 16) & 0xff);
 		if (type == MXC_CPU_MX6DL) {
-			struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
-			u32 cfg = readl(&scu->config) & 3;
-
 			if (!cfg)
 				type = MXC_CPU_MX6SOLO;
 		}
+
+		if (type == MXC_CPU_MX6Q) {
+			if (cfg == 1)
+				type = MXC_CPU_MX6D;
+		}
+
 	}
 	reg &= 0xff;		/* mx6 silicon revision */
 	return (type << 12) | (reg + 0x10);

@@ -62,6 +67,9 @@ u32 __weak get_board_rev(void)
 	if (type == MXC_CPU_MX6SOLO)
 		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
 
+	if (type == MXC_CPU_MX6D)
+		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
+
 	return cpurev;
 }
 #endif
arch/arm/imx-common/cpu.c +2 -0
index 9231649..a77c4de 100644
@@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype)
 	switch (imxtype) {
 	case MXC_CPU_MX6Q:
 		return "6Q";	/* Quad-core version of the mx6 */
+	case MXC_CPU_MX6D:
+		return "6D";	/* Dual-core version of the mx6 */
 	case MXC_CPU_MX6DL:
 		return "6DL";	/* Dual Lite version of the mx6 */
 	case MXC_CPU_MX6SOLO:
arch/arm/include/asm/arch-imx/cpu.h +1 -0
index 8c725e2..a35940e 100644
@@ -10,3 +10,4 @@
 #define MXC_CPU_MX6DL		0x61
 #define MXC_CPU_MX6SOLO		0x62
 #define MXC_CPU_MX6Q		0x63
+#define MXC_CPU_MX6D		0x64
Signature · 1 line
1.8.1.2