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drm/i915/vlv: WA to fix Voltage not getting dropped to Vmin when Gfx is power gated.

PATCH New [email protected] 1 participant 1 message Jan 31, 2014

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PATCH v7 1/1 drm/i915/vlv: WA to fix Voltage not getting dropped to Vmin when Gfx is power gated.

From: Deepak S <[email protected]>

When we enter RC6 and GFX Clocks are off, the voltage remains higher than Vmin. When we try to set the freq to RPn, it might fail since the Gfx clocks are down. So to fix this in Gfx idle, Bring the GFX clock up and set the freq to RPn then move GFx down.

v2: remove vlv_update_rps_cur_delay function. Update commit message (Daniel)

v3: Fix the timeout during wait for gfx clock (Jesse)

v4: addressed comments on set freq and punit wait (Ville)

v5: use wait_for while waiting for GFX clk to be up. (Daniel)
update cur_delay before requesting min_delay. (Ville)

v6: use wait_for while waiting for punit. (Ville)

v7: Correct reviewer's name (Ville)

Signed-off-by Deepak S <[email protected]>
Reviewed-by Ville Syrjälä <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/i915_irq.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h |  4 +++
 drivers/gpu/drm/i915/intel_pm.c | 55 ++++++++++++++++++++++++++++++++++++++++-
 4 files changed, 61 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +2 -0
index ac5cd7e..6f9108d 100644
@@ -1961,6 +1961,8 @@ extern void intel_console_resume(struct work_struct *work);
 void i915_queue_hangcheck(struct drm_device *dev);
 void i915_handle_error(struct drm_device *dev, bool wedged);
 
+void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
+							int new_delay);
 extern void intel_irq_init(struct drm_device *dev);
 extern void intel_hpd_init(struct drm_device *dev);
drivers/gpu/drm/i915/i915_irq.c +1 -1
index b226ae6..acbee73 100644
@@ -986,7 +986,7 @@ static void notify_ring(struct drm_device *dev,
 	i915_queue_hangcheck(dev);
 }
 
-static void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
+void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
 			     u32 pm_iir, int new_delay)
 {
 	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
drivers/gpu/drm/i915/i915_reg.h +4 -0
index cbbaf26..00d2f2d 100644
@@ -4949,6 +4949,10 @@
 						 GEN6_PM_RP_DOWN_THRESHOLD | \
 						 GEN6_PM_RP_DOWN_TIMEOUT)
 
+#define VLV_GTLC_SURVIVABILITY_REG              0x130098
+#define VLV_GFX_CLK_STATUS_BIT			(1<<3)
+#define VLV_GFX_CLK_FORCE_ON_BIT		(1<<2)
+
 #define GEN6_GT_GFX_RC6_LOCKED			0x138104
 #define VLV_COUNTER_CONTROL			0x138104
 #define   VLV_COUNT_RANGE_HIGH			(1<<15)
drivers/gpu/drm/i915/intel_pm.c +54 -1

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