Add Qualcomm BAM dmaengine driver
Subsystems (3)
v4 cover Add Qualcomm BAM dmaengine driver
This patch set introduces the dmaengine driver for the Qualcomm Bus Access Manager (BAM) DMA controller present on MSM 8x74 devices. A number of the on-chip devices have their own BAM DMA controller and use it to move data between system memory and peripherals or between two peripherals.
The initial version of this driver will only support slave DMA operations between system memory and peripherals.
Changes from v3:
- Remove unused bam_channel_dir.
- Remove incorrect write to BAM_IRQ_SRCS_EE (read only).
- Remove dma direction from DT binding and revise driver to use direction from prep_slave_sg.
- Remove unnecessary channel reset from channel_init. This could affect channels controlled from other execution environments.
- Change terminate_all to also take care of the current active descriptor.
- Rework .remove function to correctly mask interrupts and clean up resources and tasklets.
Changes from v2:
- Corrected Kconfig dependencies
- Moved execution environment ID to controller DT binding. The EE is a global setting across all of the channels on the controller.
- Combined header into source file.
- Corrected copyright date.
- Moved channel hardware initialization to occur when channel is used for the first time.
- Converted dma_alloc_coherent to dma_alloc_writecombine
- Removed unecessary reset of channel from the dma terminate_all
- Corrected usage of EE in irq handler and channel configuration functions.
- Changed resource functions inside probe to use correct APIs.
- Removed dma filter function and modified dma_xlate to use dma_get_slave_channel API
- Fixed various nit comments
Changes from v1:
- Converted driver to use virt-dma
- Reworked probe function per review comments
- tx_status function now computes and returns residuals
- Removed proprietary slave config. Removed associated include file.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy Gross (2):
dmaengine: add Qualcomm BAM dma driver
dmaengine: qcom_bam_dma: Add device tree binding
.../devicetree/bindings/dma/qcom_bam_dma.txt | 48 + drivers/dma/Kconfig | 9 + drivers/dma/Makefile | 1 + drivers/dma/qcom_bam_dma.c | 1059 ++++++++++++++++++++ 4 files changed, 1117 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt create mode 100644 drivers/dma/qcom_bam_dma.c
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PATCH v4 1/2 dmaengine: add Qualcomm BAM dma driver
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral. Each channel provides a uni-directional data transfer engine that is capable of transferring data between the peripheral and system memory (System mode), or between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between peripherals and system memory.
--- drivers/dma/Kconfig | 9 + drivers/dma/Makefile | 1 + drivers/dma/qcom_bam_dma.c | 1059 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1069 insertions(+) create mode 100644 drivers/dma/qcom_bam_dma.c
drivers/dma/Kconfig +9 -0
@@ -386,4 +386,13 @@ config DMATEST config DMA_ENGINE_RAID bool +config QCOM_BAM_DMA + tristate "QCOM BAM DMA support" + depends on ARCH_MSM_DT || (COMPILE_TEST && OF && ARM) + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + ---help--- + Enable support for the QCOM BAM DMA controller. This controller + provides DMA capabilities for a variety of on-chip devices. + endif
drivers/dma/Makefile +1 -0
@@ -42,3 +42,4 @@ obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o obj-$(CONFIG_TI_CPPI41) += cppi41.o obj-$(CONFIG_K3_DMA) += k3dma.o +obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o
drivers/dma/qcom_bam_dma.c new file +1059 -0
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Re: [Patch v4 1/2] dmaengine: add Qualcomm BAM dma driver
On 02/04/2014 12:04 AM, Andy Gross wrote:
[...]
drivers/dma/qcom_bam_dma.c line 1021
Quoted 7 lines
drivers/dma/qcom_bam_dma.c new file +7
-0+static int bam_dma_remove (struct platform_device *pdev) +{ +struct bam_device *bdev =platform_get_drvdata (pdev); +u32 i; + +dma_async_device_unregister (&bdev->common); +of_dma_controller_free (pdev->dev.of_node);
The controller should first be removed from the of lookup table, then free the device.
drivers/dma/qcom_bam_dma.c line 1024
Quoted 3 lines
drivers/dma/qcom_bam_dma.c new file +3
-0+ +/* mask all interrupts for this execution environment */ +writel_relaxed (0 , bdev->regs +BAM_IRQ_SRCS_MSK_EE (bdev->ee));
You still need to free the interrupt to make this race free, especially on a multi-processor system. free_irq() acts as a synchronization point that makes sure that interrupt handler has finished running and that no new interrupt handlers are being run after this point. Just masking the interrupt in the control register does not provide these guarantees.
Quoted 12 lines
drivers/dma/qcom_bam_dma.c new file +12
-0+ +for (i =0 ; i < bdev->num_channels; i++) { +bam_dma_terminate_all (&bdev->channels[i]); +tasklet_kill (&bdev->channels[i].vc.task); + } + +tasklet_kill (&bdev->task); + +clk_disable_unprepare (bdev->bamclk); + +return 0 ; +}
[...]
Re: [Patch v4 1/2] dmaengine: add Qualcomm BAM dma driver
Quoted 13 lines · Lars-Peter Clausen
On 02/04/2014 12:04 AM, Andy Gross wrote:
[...]drivers/dma/qcom_bam_dma.c line 1021
Quoted 7 lines
drivers/dma/qcom_bam_dma.c new file +7
-0+static int bam_dma_remove (struct platform_device *pdev) +{ +struct bam_device *bdev =platform_get_drvdata (pdev); +u32 i; + +dma_async_device_unregister (&bdev->common); +of_dma_controller_free (pdev->dev.of_node);The controller should first be removed from the of lookup table, then free the device.
Ah right, had this reversed.
Quoted 10 lines
drivers/dma/qcom_bam_dma.c line 1024
Quoted 3 lines
drivers/dma/qcom_bam_dma.c new file +3
-0+ +/* mask all interrupts for this execution environment */ +writel_relaxed (0 , bdev->regs +BAM_IRQ_SRCS_MSK_EE (bdev->ee));You still need to free the interrupt to make this race free, especially on a multi-processor system.
free_irq()acts as a synchronization point that makes sure that interrupt handler has finished running and that no new interrupt handlers are being run after this point. Just masking the interrupt in the control register does not provide these guarantees.
ok i'll just add in a devm_free_irq(). The only good thing then about using the devm_request_irq is the cleanup on error paths in the probe.
Quoted 14 lines
Quoted 12 lines
drivers/dma/qcom_bam_dma.c new file +12
-0+ +for (i =0 ; i < bdev->num_channels; i++) { +bam_dma_terminate_all (&bdev->channels[i]); +tasklet_kill (&bdev->channels[i].vc.task); + } + +tasklet_kill (&bdev->task); + +clk_disable_unprepare (bdev->bamclk); + +return 0 ; +}[...]
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PATCH v4 2/2 dmaengine: qcom_bam_dma: Add device tree binding
In reply to Andy GrossAdd device tree binding support for the QCOM BAM DMA driver.
--- .../devicetree/bindings/dma/qcom_bam_dma.txt | 48 ++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
Documentation/devicetree/bindings/dma/qcom_bam_dma.txt new file +48 -0
@@ -0,0 +1,48 @@ +QCOM BAM DMA controller + +Required properties: +- compatible: Must be "qcom,bam-v1.4.0" for MSM8974 V1 + Must be "qcom,bam-v1.4.1" for MSM8974 V2 +- reg: Address range for DMA registers +- interrupts: single interrupt for this controller +- #dma-cells: must be <1> +- clocks: required clock +- clock-names: name of clock +- qcom,ee : indicates the active Execution Environment identifier (0-7) + +Example: + + uart-bam: dma at f9984000 = { + compatible = "qcom,bam-v1.4.1"; + reg = <0xf9984000 0x15000>; + interrupts = <0 94 0>; + clocks = <&gcc GCC_BAM_DMA_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + +Client: +Required properties: +- dmas: List of dma channel requests +- dma-names: Names of aforementioned requested channels + +Clients must use the format described in the dma.txt file, using a two cell +specifier for each channel. + +The three cells in order are: + 1. A phandle pointing to the DMA controller + 2. The channel number + +Example: + serial at f991e000 { + compatible = "qcom,msm-uart"; + reg = <0xf991e000 0x1000> + <0xf9944000 0x19000>; + interrupts = <0 108 0>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + + dmas = <&uart-bam 0>, <&uart-bam 1>; + dma-names = "rx", "tx"; + };
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