x86/AVX-512: AVX-512 Feature Detection
PATCH 1/2 x86/AVX-512: AVX-512 Feature Detection
From: Fenghua Yu <[email protected]>
AVX-512 is an extention of AVX2. Its spec can be found at:
http://download-software.intel.com/sites/default/files/managed/71/2e/319433-017.pdf
This patch detects AVX-512 features by CPUID.
Signed-off-by Fenghua Yu <[email protected]>
--- arch/x86/include/asm/cpufeature.h | 4 ++++ 1 file changed, 4 insertions(+)
arch/x86/include/asm/cpufeature.h +4 -0
@@ -217,9 +217,13 @@#define X86_FEATURE_INVPCID (9*32+10)/* Invalidate Processor Context ID */ #define X86_FEATURE_RTM (9*32+11)/* Restricted Transactional Memory */ #define X86_FEATURE_MPX (9*32+14)/* Memory Protection Extension */ +#define X86_FEATURE_AVX512F (9*32+16)/* AVX-512 Foundation */ #define X86_FEATURE_RDSEED (9*32+18)/* The RDSEED instruction */ #define X86_FEATURE_ADX (9*32+19)/* The ADCX and ADOX instructions */ #define X86_FEATURE_SMAP (9*32+20)/* Supervisor Mode Access Prevention */ +#define X86_FEATURE_AVX512PF (9*32+26)/* AVX-512 Prefetch */ +#define X86_FEATURE_AVX512ER (9*32+27)/* AVX-512 Exponential and Reciprocal */ +#define X86_FEATURE_AVX512CD (9*32+28)/* AVX-512 Conflict Detection */ /* * BUG word(s)
Signature · 1 line
1.8.1.2
PATCH 2/2 x86/AVX-512: Enable AVX-512 States Context Switch
From: Fenghua Yu <[email protected]>
This patch enables Opmask, ZMM_Hi256, and Hi16_ZMM AVX-512 states for xstate context switch.
Signed-off-by Fenghua Yu <[email protected]>
--- arch/x86/include/asm/xsave.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-)
arch/x86/include/asm/xsave.h +10 -6
@@ -6,11 +6,14 @@#define XSTATE_CPUID 0x0000000d -#define XSTATE_FP 0x1 -#define XSTATE_SSE 0x2 -#define XSTATE_YMM 0x4 -#define XSTATE_BNDREGS 0x8 -#define XSTATE_BNDCSR 0x10 +#define XSTATE_FP 0x1 +#define XSTATE_SSE 0x2 +#define XSTATE_YMM 0x4 +#define XSTATE_BNDREGS 0x8 +#define XSTATE_BNDCSR 0x10 +#define XSTATE_OPMASK 0x20 +#define XSTATE_ZMM_Hi256 0x40 +#define XSTATE_Hi16_ZMM 0x80#define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
@@ -23,7 +26,8 @@#define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)/* Supported features which support lazy state saving */ -#define XSTATE_LAZY (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) +#define XSTATE_LAZY (XSTATE_FP | XSTATE_SSE | XSTATE_YMM \ + | XSTATE_OPMASK | XSTATE_ZMM_Hi256 | XSTATE_Hi16_ZMM)/* Supported features which require eager state saving */ #define XSTATE_EAGER (XSTATE_BNDREGS | XSTATE_BNDCSR)
Signature · 1 line
1.8.1.2
tip-bot for Fenghua Yu
merge bot[tip:x86/cpufeature] x86, AVX-512: Enable AVX-512 States Context Switch
x86, AVX-512: Enable AVX-512 States Context Switch
Commit-ID: c2bc11f10a39527cd1bb252097b5525664560956 Gitweb: http://git.kernel.org/tip/c2bc11f10a39527cd1bb252097b5525664560956 Author: Fenghua Yu <[email protected]> AuthorDate: Thu, 20 Feb 2014 13:24:51 -0800 Committer: H. Peter Anvin <[email protected]> CommitDate: Thu, 20 Feb 2014 13:56:55 -0800
x86, AVX-512: Enable AVX-512 States Context Switch
This patch enables Opmask, ZMM_Hi256, and Hi16_ZMM AVX-512 states for xstate context switch.
Signed-off-by Fenghua Yu <[email protected]>
Signed-off-by H. Peter Anvin <[email protected]>
Cc <[email protected]> # hw enabling
--- arch/x86/include/asm/xsave.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-)
arch/x86/include/asm/xsave.h +10 -6
@@ -6,11 +6,14 @@#define XSTATE_CPUID 0x0000000d -#define XSTATE_FP 0x1 -#define XSTATE_SSE 0x2 -#define XSTATE_YMM 0x4 -#define XSTATE_BNDREGS 0x8 -#define XSTATE_BNDCSR 0x10 +#define XSTATE_FP 0x1 +#define XSTATE_SSE 0x2 +#define XSTATE_YMM 0x4 +#define XSTATE_BNDREGS 0x8 +#define XSTATE_BNDCSR 0x10 +#define XSTATE_OPMASK 0x20 +#define XSTATE_ZMM_Hi256 0x40 +#define XSTATE_Hi16_ZMM 0x80#define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
@@ -23,7 +26,8 @@#define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)/* Supported features which support lazy state saving */ -#define XSTATE_LAZY (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) +#define XSTATE_LAZY (XSTATE_FP | XSTATE_SSE | XSTATE_YMM \ + | XSTATE_OPMASK | XSTATE_ZMM_Hi256 | XSTATE_Hi16_ZMM)/* Supported features which require eager state saving */ #define XSTATE_EAGER (XSTATE_BNDREGS | XSTATE_BNDCSR)
tip-bot for Fenghua Yu
merge bot[tip:x86/cpufeature] x86, AVX-512: AVX-512 Feature Detection
In reply to Fenghua Yux86, AVX-512: AVX-512 Feature Detection
Commit-ID: 8e5780fdeef7dc490b3f0b3a62704593721fa4f3 Gitweb: http://git.kernel.org/tip/8e5780fdeef7dc490b3f0b3a62704593721fa4f3 Author: Fenghua Yu <[email protected]> AuthorDate: Thu, 20 Feb 2014 13:24:50 -0800 Committer: H. Peter Anvin <[email protected]> CommitDate: Thu, 20 Feb 2014 13:56:55 -0800
x86, AVX-512: AVX-512 Feature Detection
AVX-512 is an extention of AVX2. Its spec can be found at:
http://download-software.intel.com/sites/default/files/managed/71/2e/319433-017.pdf
This patch detects AVX-512 features by CPUID.
Signed-off-by Fenghua Yu <[email protected]>
Signed-off-by H. Peter Anvin <[email protected]>
Cc <[email protected]> # hw enabling
--- arch/x86/include/asm/cpufeature.h | 4 ++++ 1 file changed, 4 insertions(+)
arch/x86/include/asm/cpufeature.h +4 -0
@@ -217,9 +217,13 @@#define X86_FEATURE_INVPCID (9*32+10)/* Invalidate Processor Context ID */ #define X86_FEATURE_RTM (9*32+11)/* Restricted Transactional Memory */ #define X86_FEATURE_MPX (9*32+14)/* Memory Protection Extension */ +#define X86_FEATURE_AVX512F (9*32+16)/* AVX-512 Foundation */ #define X86_FEATURE_RDSEED (9*32+18)/* The RDSEED instruction */ #define X86_FEATURE_ADX (9*32+19)/* The ADCX and ADOX instructions */ #define X86_FEATURE_SMAP (9*32+20)/* Supervisor Mode Access Prevention */ +#define X86_FEATURE_AVX512PF (9*32+26)/* AVX-512 Prefetch */ +#define X86_FEATURE_AVX512ER (9*32+27)/* AVX-512 Exponential and Reciprocal */ +#define X86_FEATURE_AVX512CD (9*32+28)/* AVX-512 Conflict Detection */ /* * BUG word(s)