socfpga: Adding Clock Manager driver
PATCH v2 1/1 socfpga: Adding Clock Manager driver
Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files
---
Changes for v2
- merge the handoff file and driver into single patch
--- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/clock_manager.c | 378 ++++++++++++++++++++ arch/arm/cpu/armv7/socfpga/spl.c | 90 +++++ arch/arm/include/asm/arch-socfpga/clock_manager.h | 205 +++++++++++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 + board/altera/socfpga/pll_config.h | 118 ++++++ include/configs/socfpga_cyclone5.h | 1 + 7 files changed, 794 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/clock_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/clock_manager.h create mode 100755 board/altera/socfpga/pll_config.h
arch/arm/cpu/armv7/socfpga/Makefile +1 -1
@@ -8,5 +8,5 @@ # obj-y := lowlevel_init.o -obj-y += misc.o timer.o reset_manager.o system_manager.o +obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
arch/arm/cpu/armv7/socfpga/clock_manager.c new file +378 -0
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arch/arm/cpu/armv7/socfpga/spl.c +90 -0
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arch/arm/include/asm/arch-socfpga/clock_manager.h new file +205 -0
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arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +1 -0
@@ -11,6 +11,7 @@#define SOCFPGA_UART0_ADDRESS 0xffc02000#define SOCFPGA_UART1_ADDRESS 0xffc03000#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
board/altera/socfpga/pll_config.h new file +118 -0
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include/configs/socfpga_cyclone5.h +1 -0
@@ -9,6 +9,7 @@#include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/pinmux_config.h" #include "../../board/altera/socfpga/iocsr_config.h" +#include "../../board/altera/socfpga/pll_config.h" /* * High level configuration
Signature · 1 line
1.7.9.5
PATCH v2 1/1 socfpga: Adding Clock Manager driver
Hi!
Quoted 19 lines
Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files
Signed-off-by Chin Liang See <[email protected]>Cc Albert Aribaud <[email protected]>Cc Tom Rini <[email protected]>Cc Wolfgang Denk <[email protected]>CC Pavel Machek <[email protected]>Cc Dinh Nguyen <[email protected]>---
Changes for v2
- merge the handoff file and driver into single patcharch/arm/cpu/armv7/socfpga/clock_manager.c new file +5
-0+#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock_manager.h> + +static const struct socfpga_clock_manager *clock_manager_base =
arch/arm/cpu/armv7/socfpga/clock_manager.c line 21
Quoted 10 lines
arch/arm/cpu/armv7/socfpga/clock_manager.c new file +10
-0+ (void *)SOCFPGA_CLKMGR_ADDRESS ; + +#define CLKMGR_BYPASS_ENUM_ENABLE 1 +#define CLKMGR_BYPASS_ENUM_DISABLE 0 +#define CLKMGR_STAT_BUSY_ENUM_IDLE 0x0 +#define CLKMGR_STAT_BUSY_ENUM_BUSY 0x1 +#define CLKMGR_BYPASS_PERPLLSRC_ENUM_SELECT_EOSC1 0x0 +#define CLKMGR_BYPASS_PERPLLSRC_ENUM_SELECT_INPUT_MUX 0x1 +#define CLKMGR_BYPASS_SDRPLLSRC_ENUM_SELECT_EOSC1 0x0 +#define CLKMGR_BYPASS_SDRPLLSRC_ENUM_SELECT_INPUT_MUX 0x1
This is not too consistent. I guess dropping the 0x here would help. And maybe CLKMGR_STAT_IDLE and CLKMGR_STAT_BUSY would be better define names? Dropping _ENUM would help, too.
Quoted 6 lines
arch/arm/cpu/armv7/socfpga/clock_manager.c new file +6
-0+static inline void cm_wait_for_lock (uint32_t mask) +{ + registeruint32_t inter_val; +do { + inter_val =readl (&clock_manager_base->inter) & mask; + }while (inter_val != mask);
arch/arm/cpu/armv7/socfpga/clock_manager.c line 48
Quoted 10 lines
arch/arm/cpu/armv7/socfpga/clock_manager.c new file +10
-0+} + +/* function to poll in the fsm busy bit */ +static inline void cm_wait4fsm (void ) +{ + registeruint32_t inter_val; +do { + inter_val =readl (&clock_manager_base->stat) &CLKMGR_STAT_BUSY_ENUM_BUSY ; + }while (inter_val); +}
wait4fsm vs. wait_for_lock. Pick one style...
And actually ... maybe
while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY_ENUM_BUSY) ;
is easier to read? No need for variable...
arch/arm/cpu/armv7/socfpga/clock_manager.c line 77
Quoted 11 lines
arch/arm/cpu/armv7/socfpga/clock_manager.c new file +11
-0+/* function to write a clock register that has phase information */ +static inline void cm_write_with_phase (uint32_t value, +uint32_t reg_address,uint32_t mask) +{ +/* poll until phase is zero */ +do {}while (readl (reg_address) & mask); + +writel (value, reg_address); + +do {}while (readl (reg_address) & mask); +}
drop do {} .
Quoted 3 lines
+/*
+ * Setup clocks while making no assumptions of the
+ * previous state of the clocks.
...no assumptions about...?
Quoted 26 lines
+ * Start by being paranoid and gate all sw managed clocks
+ *
+ * Put all plls in bypass
+ *
+ * Put all plls VCO registers back to reset value (bgpwr dwn).
+ *
+ * Put peripheral and main pll src to reset value to avoid glitch.
+ *
+ * Delay 5 us.
+ *
+ * Deassert bg pwr dn and set numerator and denominator
+ *
+ * Start 7 us timer.
+ *
+ * set internal dividers
+ *
+ * Wait for 7 us timer.
+ *
+ * Enable plls
+ *
+ * Set external dividers while plls are locking
+ *
+ * Wait for pll lock
+ *
+ * Assert/deassert outreset all.
+ *
Quoted 8 lines
+ * Take all pll's out of bypass
+ *
+ * Clear safe mode
+ *
+ * set source main and peripheral clocks
+ *
+ * Ungate clocks
+ */
Drop empty lines, add "." to end sentences, and spell out "bg pwr dn"?
arch/arm/cpu/armv7/socfpga/clock_manager.c line 119
Quoted 2 lines
arch/arm/cpu/armv7/socfpga/clock_manager.c new file +2
-0+void cm_basic_init (const cm_config_t *cfg) +{
Split to smaller functions? Then you will not need the summary comment...
arch/arm/cpu/armv7/socfpga/clock_manager.c line 249
Quoted 3 lines
arch/arm/cpu/armv7/socfpga/clock_manager.c new file +3
-0+/* 7 us must have elapsed before we can enable the VCO */ +for ( ;get_timer (start) < timeout ; ) + ;
while() ?
arch/arm/cpu/armv7/socfpga/spl.c u32 spl_boot_device(void) · line 34
Quoted 10 lines
arch/arm/cpu/armv7/socfpga/spl.c +4
-0@@ -28,10 +28,100 @@ u32 spl_boot_device(void)void spl_board_init (void ) {#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET + +cm_config_t cm_default_cfg = { +/* main group */ + MAIN_VCO_BASE,
This will generate pretty bad code, no? Should it be static?
arch/arm/cpu/armv7/socfpga/spl.c u32 spl_boot_device(void) · line 44
Quoted 10 lines
arch/arm/cpu/armv7/socfpga/spl.c +10
-0+CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET ( +CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT ), +CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET ( +CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT ), +CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET ( +CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT ), +CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET ( +CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT ), +CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET ( + CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
It would be good to somehow shorted identifiers so this fits to one line.
Quoted 1 line
arch/arm/cpu/armv7/socfpga/spl.c +1
-0+typedef struct {
...
arch/arm/cpu/armv7/socfpga/spl.c
Quoted 6 lines
arch/arm/cpu/armv7/socfpga/spl.c +6
-0+uint32_t sdram_vco_base; +uint32_t ddrdqsclk; +uint32_t ddr2xdqsclk; +uint32_t ddrdqclk; +uint32_t s2fuser2clk; +} cm_config_t;
typedefs for structs are usually not welcome...
Thanks,
Pavel
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html