xtensa xtfpga SPI controller driver
Subsystems (3)
Max Filippov
maintainerv2 cover xtensa xtfpga SPI controller driver
Hello,
this series adds driver for SPI controller used on xtfpga xtensa platform, device tree binding documentation and an entry to MAINTAINERS.
Changes v1 -> v2:
- support 8 bit transfers;
- busy-wait for maximum 100 usec (instead of 100 msec) polling BUSY register;
- use chipselect callback to check transfer size.
Max Filippov (3):
spi: add xtfpga SPI controller driver
spi/xtensa-xtfpga: add DT binding documentation
MAINTAINERS: add xtfpga platform section
.../devicetree/bindings/spi/spi-xtensa-xtfpga.txt | 9 + MAINTAINERS | 6 + drivers/spi/Kconfig | 13 ++ drivers/spi/Makefile | 1 + drivers/spi/spi-xtensa-xtfpga.c | 187 +++++++++++++++++++++ 5 files changed, 216 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt create mode 100644 drivers/spi/spi-xtensa-xtfpga.c
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Max Filippov
maintainerPATCH v2 1/3 spi: add xtfpga SPI controller driver
This simple SPI master controller is built into xtfpga bitstreams. It always transfers 16 bit words in SPI mode 0, automatically asserting CS on transfer start and deasserting on end.
---
Changes v1 -> v2:
- support 8 bit transfers;
- busy-wait for maximum 100 usec (instead of 100 msec) polling BUSY register;
- use chipselect callback to check transfer size.
drivers/spi/Kconfig | 13 +++ drivers/spi/Makefile | 1 + drivers/spi/spi-xtensa-xtfpga.c | 187 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 201 insertions(+) create mode 100644 drivers/spi/spi-xtensa-xtfpga.c
drivers/spi/Kconfig +13 -0
@@ -520,6 +520,19 @@ config SPI_XILINX Or for the DS570, see "XPS Serial Peripheral Interface (SPI) (v2.00b)" +config SPI_XTENSA_XTFPGA + tristate "Xtensa SPI controller for xtfpga" + depends on XTENSA && XTENSA_PLATFORM_XTFPGA + select SPI_BITBANG + help + SPI driver for xtfpga SPI master controller. + + This simple SPI master controller is built into xtfpga bitstreams + and is used to control daughterboard audio codec. It always transfers + 16 bit words in SPI mode 0, automatically asserting CS on transfer + start and deasserting on end. + + config SPI_NUC900 tristate "Nuvoton NUC900 series SPI" depends on ARCH_W90X900
drivers/spi/Makefile +1 -0
@@ -79,3 +79,4 @@ obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o obj-$(CONFIG_SPI_TXX9) += spi-txx9.o obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o +obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o
drivers/spi/spi-xtensa-xtfpga.c new file +187 -0
187 lines not on this page · raw message
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1.8.1.4
Mark Brown
maintainerRe: [PATCH v2 1/3] spi: add xtfpga SPI controller driver
drivers/spi/spi-xtensa-xtfpga.c line 73
Quoted 8 lines · Max Filippov
drivers/spi/spi-xtensa-xtfpga.c new file +8
-0+case 16 : +/* Bytes that should go out earlier have lower addresses, +* but the hardware operates with 16 bit words and transmits +* higher bits first. Thus data in memory is in BE order. +*/ + xspi->data = (xspi->data <<16 ) |be16_to_cpu (v); + xspi->data_sz +=2 ; +break ;
Are you sure you need to do this byte swap? SPI words are big endian so if you are running on a little endian processor if you are transmitting 16 bit words you should see the data getting swapped on the bus (this is why I say you should never have more than 8 bits per word for regmap).
Max Filippov
maintainerRe: [PATCH v2 1/3] spi: add xtfpga SPI controller driver
Quoted 11 lines · Mark Brown
drivers/spi/spi-xtensa-xtfpga.c line 73
Quoted 8 lines · Max Filippov
drivers/spi/spi-xtensa-xtfpga.c new file +8
-0+case 16 : +/* Bytes that should go out earlier have lower addresses, +* but the hardware operates with 16 bit words and transmits +* higher bits first. Thus data in memory is in BE order. +*/ + xspi->data = (xspi->data <<16 ) |be16_to_cpu (v); + xspi->data_sz +=2 ; +break ;
Quoted 4 lines
Are you sure you need to do this byte swap? SPI words are big endian so if you are running on a little endian processor if you are transmitting 16 bit words you should see the data getting swapped on the bus (this is why I say you should never have more than 8 bits per word for regmap).
Looks like this swap is not needed: I've looked at drivers that set bits_per_word = 16, they submit data in cpu endianness. Will fix in v3.
Signature · 6 lines
Thanks. -- Max -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
Max Filippov
maintainerPATCH v2 2/3 spi/xtensa-xtfpga: add DT binding documentation
In reply to Max Filippov--- Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt new file +9 -0
@@ -0,0 +1,9 @@ +Cadence Xtensa XTFPGA platform SPI controller. + +This simple SPI master controller is built into xtfpga bitstreams and is used +to control daughterboard audio codec. + +Required properties: +- compatible: should be "cdns,xtfpga-spi". +- reg: physical base address of the controller and length of memory mapped + region.
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Re: [PATCH v2 2/3] spi/xtensa-xtfpga: add DT binding documentation
Quoted 12 lines · Max Filippov
Signed-off-by Max Filippov <[email protected]>--- Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txtDocumentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt new file +0
-0
Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt line 7
Quoted 7 lines
Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt new file +7
-0@@ -0,0 +1,9 @@ +Cadence Xtensa XTFPGA platform SPI controller. + +This simple SPI master controller is built into xtfpga bitstreams and is used +to control daughterboard audio codec. + +Required properties: +- compatible: should be "cdns,xtfpga-spi".
Is that the official name of the block? Nothing more specific?
Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt line 9
Quoted 2 lines
Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt new file +2
-0+- reg: physical base address of the controller and length of memory mapped + region.
No interrupts?
Otherwise, this looks fine to me.
Cheers,
Mark.
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Max Filippov
maintainerRe: [PATCH v2 2/3] spi/xtensa-xtfpga: add DT binding documentation
Quoted 7 lines · Mark Rutland
Quoted 6 lines · Max Filippov
Signed-off-by Max Filippov <[email protected]>--- Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
Quoted 15 lines
Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt line 7
Quoted 13 lines
Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt new file +7
-0@@ -0,0 +1,9 @@ +Cadence Xtensa XTFPGA platform SPI controller. + +This simple SPI master controller is built into xtfpga bitstreams and is used +to control daughterboard audio codec. + +Required properties: +- compatible: should be "cdns,xtfpga-spi".Is that the official name of the block? Nothing more specific?
There's no official name, so I composed this from the official name of the platform + the block function. AFAIK there's single version of this IP block. Marc G., please correct me if I'm wrong.
Quoted 4 lines
Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt line 9
Quoted 2 lines
Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt new file +2
-0+- reg: physical base address of the controller and length of memory mapped + region.No interrupts?
Correct.
Quoted 1 line
Otherwise, this looks fine to me.
Signature · 2 lines
Thanks. -- Max
Max Filippov
maintainerPATCH v2 3/3 MAINTAINERS: add xtfpga platform section
In reply to Max FilippovThis section will list xtfpga platform-specific drivers.
--- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+)
MAINTAINERS +6 -0
@@ -9768,6 +9768,12 @@ L: [email protected] S: Maintained F: drivers/tty/serial/uartlite.c +XTENSA XTFPGA PLATFORM SUPPORT +M: Max Filippov <[email protected]> +L: [email protected] +S: Maintained +F: drivers/spi/spi-xtensa-xtfpga.c + YAM DRIVER FOR AX.25 M: Jean-Paul Roubelat <[email protected]> L: [email protected]
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