Add support for Cavium Thunder ARMv8 platform
v2 cover Add support for Cavium Thunder ARMv8 platform
From: Radha Mohan Chintakuntla <[email protected]>
This patch series adds preliminary support for Cavium's Thunder SoC which is based on ARMv8 core.
This patchset depends on following. They need to be applied before working.
1) Boot time configuration of IPA
http://www.spinics.net/lists/arm-kernel/msg313723.html
2) GICv3 driver from Marc Zyngier
http://www.spinics.net/lists/kvm-arm/msg08544.html
3) GICv3 devicetree bindings from Marc Zyngier
http://www.spinics.net/lists/kvm-arm/msg08545.html
Changes from v1:
---------------
- Added documentation for the devicetree bindings used.
- Changed the Thunder device tree as per documentation.
Radha Mohan Chintakuntla (3):
arm64: Add Kconfig option for Cavium Thunder SoC Family
arm64: dts: Add initial dts for Cavium Thunder SoC
Documentation: add devicetree bindings for Cavium Thunder SoC
.../devicetree/bindings/arm/cavium-thunder.txt | 9 + Documentation/devicetree/bindings/arm/cpus.txt | 1 + arch/arm64/Kconfig | 5 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/thunder.dts | 160 ++++++++++++++++++++ 5 files changed, 176 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder.txt create mode 100644 arch/arm64/boot/dts/thunder.dts
PATCH v2 1/3 arm64: Add Kconfig option for Cavium Thunder SoC Family
From: Radha Mohan Chintakuntla <[email protected]>
This patch adds support in Kconfig to select Cavium Thunder platform.
--- arch/arm64/Kconfig | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)
arch/arm64/Kconfig +5 -0
@@ -113,6 +113,11 @@ source "kernel/Kconfig.freezer" menu "Platform selection" +config ARCH_THUNDER + bool "Cavium Inc. Thunder SoC Family" + help + This enables support for Cavium's Thunder Family of SoCs + config ARCH_VEXPRESS bool "ARMv8 software model (Versatile Express)" select ARCH_REQUIRE_GPIOLIB
Signature · 1 line
1.7.1
PATCH v2 2/3 arm64: dts: Add initial dts for Cavium Thunder SoC
In reply to mohun106 at gmail.comFrom: Radha Mohan Chintakuntla <[email protected]>
--- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/thunder.dts | 160 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 161 insertions(+), 0 deletions(-)
arch/arm64/boot/dts/Makefile +1 -0
@@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_THUNDER) += thunder.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
arch/arm64/boot/dts/thunder.dts new file +160 -0
160 lines not on this page · raw message
Signature · 1 line
1.7.1
Arnd Bergmann
maintainerPATCH v2 2/3 arm64: dts: Add initial dts for Cavium Thunder SoC
Quoted 14 lines · On Monday 24 March 2014 14:39:38 mohun106 at gmail.com wrote:
arch/arm64/boot/dts/thunder.dts new file +14
-0+ soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>;
arch/arm64/boot/dts/thunder.dts line 135
Quoted 10 lines
arch/arm64/boot/dts/thunder.dts new file +10
-0+ clock-frequency = <50000000>; + clock-output-names = "refclk50mhz"; + }; + }; + + ahci0: host-bus-adapter at 810000000000 { + compatible = "snps,spear-ahci"; + reg = <0x8100 0x0 0x0 0x1100>; + interrupts = <1 32 4>; + };
The use of "snps,spear-ahci" by itself seems wrong here: that is the specific implementation used in the ST "spear" SoC. I don't know why we don't already have a "generic-ahci" binding, but please add one so you can match against that.
I would also recommend adding a more specific string for your soc. If you want to keep compatibility with older kernels, you can keep the spear string as well, but it would be nicer to drop that. If you can find out what version the synopsys macro has, that would be ideal.
You could end up for instance with
compatible = "cavium,thunder-123456-ahci", "snps,ahci-1.23.45", "snps,spear-ahci", "generic-ahci";
The driver only needs to match the last one of these, but if we find that we have to work around some bug, it's good to have the option of determining the exact version.
Quoted 11 lines
arch/arm64/boot/dts/thunder.dts new file +11
-0+ nic0: ethernet at 843000000000 { + compatible = "smsc,lan9115"; + reg-io-width = <4>; + reg = <0x8430 0x0 0x0 0x1000>; + interrupts = <1 31 4>; + }; + + uaa0: uart at 87e024000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x24000000 0x0 0x1000>; + interrupts = <1 21 4>;
arch/arm64/boot/dts/thunder.dts line 157
Quoted 10 lines
arch/arm64/boot/dts/thunder.dts new file +10
-0+ clocks = <&refclk50mhz>; + clock-names = "apb_pclk"; + }; + + uaa1: uart at 87e025000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x25000000 0x0 0x1000>; + interrupts = <1 22 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk";
The generic name for uarts in DT is "serial", not "uart" (yes, a lot of others get this wrong, too).
Arnd
PATCH v2 2/3 arm64: dts: Add initial dts for Cavium Thunder SoC
Hi Arnd
Quoted 38 lines · Arnd Bergmann
Quoted 14 lines · On Monday 24 March 2014 14:39:38 mohun106 at gmail.com wrote:
arch/arm64/boot/dts/thunder.dts new file +14
-0+ soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>;arch/arm64/boot/dts/thunder.dts line 135
Quoted 10 lines
arch/arm64/boot/dts/thunder.dts new file +10
-0+ clock-frequency = <50000000>; + clock-output-names = "refclk50mhz"; + }; + }; + + ahci0: host-bus-adapter at 810000000000 { + compatible = "snps,spear-ahci"; + reg = <0x8100 0x0 0x0 0x1100>; + interrupts = <1 32 4>; + };The use of "snps,spear-ahci" by itself seems wrong here: that is the specific implementation used in the ST "spear" SoC. I don't know why we don't already have a "generic-ahci" binding, but please add one so you can match against that.
I would also recommend adding a more specific string for your soc. If you want to keep compatibility with older kernels, you can keep the spear string as well, but it would be nicer to drop that. If you can find out what version the synopsys macro has, that would be ideal.
Quoted 8 lines
You could end up for instance with
compatible = "cavium,thunder-123456-ahci", "snps,ahci-1.23.45", "snps,spear-ahci", "generic-ahci";The driver only needs to match the last one of these, but if we find that we have to work around some bug, it's good to have the option of determining the exact version.
OK.
Quoted 17 lines
Quoted 17 lines
arch/arm64/boot/dts/thunder.dts new file +16
-0+ nic0: ethernet at 843000000000 { + compatible = "smsc,lan9115"; + reg-io-width = <4>; + reg = <0x8430 0x0 0x0 0x1000>; + interrupts = <1 31 4>; + }; + + uaa0: uart at 87e024000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x24000000 0x0 0x1000>; + interrupts = <1 21 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk"; + }; + + uaa1: uart at 87e025000000 {
Quoted 8 lines
arch/arm64/boot/dts/thunder.dts line 157
Quoted 5 lines
arch/arm64/boot/dts/thunder.dts new file +5
-0+ compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x25000000 0x0 0x1000>; + interrupts = <1 22 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk";The generic name for uarts in DT is "serial", not "uart" (yes, a lot of others get this wrong, too).
OK :)
But I think lack of consistency in DT among various ARM platforms is source of this confusion.
Quoted 6 lines
Arnd
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Mark Rutland
reviewerPATCH v2 2/3 arm64: dts: Add initial dts for Cavium Thunder SoC
In reply to mohun106 at gmail.comHi,
Quoted 26 lines · On Mon, Mar 24, 2014 at 09:09:38AM +0000, mohun106 at gmail.com wrote:
From: Radha Mohan Chintakuntla <[email protected]>
Signed-off-by Radha Mohan Chintakuntla <[email protected]>--- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/thunder.dts | 160 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 161 insertions(+), 0 deletions(-)arch/arm64/boot/dts/Makefile +1
-0@@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_THUNDER) += thunder.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtbarch/arm64/boot/dts/thunder.dts new file +3
-0@@ -0,0 +1,160 @@ +/* + * Cavium Thunder DTS file + *
arch/arm64/boot/dts/thunder.dts line 13
Quoted 10 lines
arch/arm64/boot/dts/thunder.dts new file +10
-0+ * Copyright (C) 2013, Cavium Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000;
Please add a comment as to what this is protecting (from the looks of it, the spinning CPUs and the cpu release address). We are admittedly lacking these on existing DTs (and I'll fix that up), but it would be good to get into the habit now given it has been a source of confusion for some.
Quoted 9 lines
arch/arm64/boot/dts/thunder.dts new file +9
-0+ +/ { + model = "Cavium Thunder"; + compatible = "cavium,thunder"; + interrupt-parent = <&gic0>; + #address-cells = <2>; + #size-cells = <2>; + + aliases {
arch/arm64/boot/dts/thunder.dts line 32
Quoted 10 lines
arch/arm64/boot/dts/thunder.dts new file +10
-0+ serial0 = &uaa0; + serial1 = &uaa1; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu at 0 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8";
This is the same as the compatible string for the SoC, which isn't a good idea. Compatible strings should be globally unique.
As far as I am aware, "Thunder" is the name of the SoC, not the CPU in the SoC. Is there a name for the CPU in the Thunder SoC?
Whatever name you have should be documented.
[...]
arch/arm64/boot/dts/thunder.dts line 94
Quoted 6 lines
arch/arm64/boot/dts/thunder.dts new file +6
-0+ memory at 0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + gic0: interrupt-controller at 801000000000 {
Please break the 32-bit halves of the unit-address with a comma (e.g. 8010,00000000); it makes it easier to read the address. If you could also do this on other unit-addresses it would be helpful.
arch/arm64/boot/dts/thunder.dts line 100
Quoted 6 lines
arch/arm64/boot/dts/thunder.dts new file +6
-0+ compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x8010 0x0 0x0 0x10000>, /* GICD */ + <0x8010 0x80000000 0x0 0x100000>; /* GICR */
For legibility it would be nice for list entries to be consistently padded to the same length.
Quoted 19 lines
arch/arm64/boot/dts/thunder.dts new file +19
-0+ interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks { + #address-cells = <2>;
arch/arm64/boot/dts/thunder.dts line 129
Quoted 10 lines
arch/arm64/boot/dts/thunder.dts new file +10
-0+ #size-cells = <2>; + ranges; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "refclk50mhz"; + }; + };
I don't think the clocks node adds anything here. It's missing a compatible string list, and as clocks isn't a special reserved node name, it and its children aren't supposed to be probed.
Why not just put the refclk50mhz directly under the parent node (the soc simple-bus)?
[...]
arch/arm64/boot/dts/thunder.dts line 149
Quoted 6 lines
arch/arm64/boot/dts/thunder.dts new file +6
-0+ uaa0: uart at 87e024000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x24000000 0x0 0x1000>; + interrupts = <1 21 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk";
Is this also feeding the UARTCLK?
arch/arm64/boot/dts/thunder.dts line 157
Quoted 8 lines
arch/arm64/boot/dts/thunder.dts new file +8
-0+ }; + + uaa1: uart at 87e025000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x25000000 0x0 0x1000>; + interrupts = <1 22 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk";
Likewise?
Cheers,
Mark.
PATCH v2 2/3 arm64: dts: Add initial dts for Cavium Thunder SoC
Hi Mark,
Quoted 37 lines · Mark Rutland
Hi,
Quoted 34 lines · On Mon, Mar 24, 2014 at 09:09:38AM +0000, mohun106 at gmail.com wrote:
From: Radha Mohan Chintakuntla <[email protected]>
Signed-off-by Radha Mohan Chintakuntla <[email protected]>--- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/thunder.dts | 160 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 161 insertions(+), 0 deletions(-)arch/arm64/boot/dts/Makefile +1
-0@@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_THUNDER) += thunder.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtbarch/arm64/boot/dts/thunder.dts new file +11
-0@@ -0,0 +1,160 @@ +/* + * Cavium Thunder DTS file + * + * Copyright (C) 2013, Cavium Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ +/dts-v1/;
Quoted 8 lines
arch/arm64/boot/dts/thunder.dts line 13
Quoted 2 lines
arch/arm64/boot/dts/thunder.dts new file +2
-0+ +/memreserve/ 0x80000000 0x00010000;Please add a comment as to what this is protecting (from the looks of it, the spinning CPUs and the cpu release address). We are admittedly lacking these on existing DTs (and I'll fix that up), but it would be good to get into the habit now given it has been a source of confusion for some.
OK.
Quoted 24 lines
Quoted 10 lines
arch/arm64/boot/dts/thunder.dts new file +9
-0+ +/ { + model = "Cavium Thunder"; + compatible = "cavium,thunder"; + interrupt-parent = <&gic0>; + #address-cells = <2>; + #size-cells = <2>; + + aliases {arch/arm64/boot/dts/thunder.dts line 32
Quoted 10 lines
arch/arm64/boot/dts/thunder.dts new file +10
-0+ serial0 = &uaa0; + serial1 = &uaa1; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu at 0 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8";This is the same as the compatible string for the SoC, which isn't a good idea. Compatible strings should be globally unique.
Quoted 4 lines
As far as I am aware, "Thunder" is the name of the SoC, not the CPU in the SoC. Is there a name for the CPU in the Thunder SoC?
Whatever name you have should be documented.
OK. I will change it to a specific name.
Quoted 10 lines
[...]
arch/arm64/boot/dts/thunder.dts line 94
Quoted 6 lines
arch/arm64/boot/dts/thunder.dts new file +6
-0+ memory at 0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + gic0: interrupt-controller at 801000000000 {
Quoted 3 lines
Please break the 32-bit halves of the unit-address with a comma (e.g. 8010,00000000); it makes it easier to read the address. If you could also do this on other unit-addresses it would be helpful.
OK.
Quoted 10 lines
arch/arm64/boot/dts/thunder.dts line 100
Quoted 7 lines
arch/arm64/boot/dts/thunder.dts new file +6
-0+ compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x8010 0x0 0x0 0x10000>, /* GICD */ + <0x8010 0x80000000 0x0 0x100000>; /* GICR */For legibility it would be nice for list entries to be consistently padded to the same length.
OK.
Quoted 35 lines
Quoted 20 lines
arch/arm64/boot/dts/thunder.dts new file +19
-0+ interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks { + #address-cells = <2>;arch/arm64/boot/dts/thunder.dts line 129
Quoted 10 lines
arch/arm64/boot/dts/thunder.dts new file +10
-0+ #size-cells = <2>; + ranges; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "refclk50mhz"; + }; + };I don't think the clocks node adds anything here. It's missing a compatible string list, and as clocks isn't a special reserved node name, it and its children aren't supposed to be probed.
Quoted 2 lines
Why not just put the refclk50mhz directly under the parent node (the soc simple-bus)?
OK.
Quoted 11 lines
[...]
arch/arm64/boot/dts/thunder.dts line 149
Quoted 6 lines
arch/arm64/boot/dts/thunder.dts new file +6
-0+ uaa0: uart at 87e024000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x24000000 0x0 0x1000>; + interrupts = <1 21 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk";Is this also feeding the UARTCLK?
Right now, this is for an internal emulation platform for our chip. So all these clock definitions are not applicable.
In real chip, there will be other clock definitions coming.
Quoted 14 lines
arch/arm64/boot/dts/thunder.dts line 157
Quoted 9 lines
arch/arm64/boot/dts/thunder.dts new file +8
-0+ }; + + uaa1: uart at 87e025000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x25000000 0x0 0x1000>; + interrupts = <1 22 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk";Likewise?
Cheers,
Mark.
PATCH v2 3/3 Documentation: add devicetree bindings for Cavium Thunder SoC
In reply to mohun106 at gmail.comFrom: Radha Mohan Chintakuntla <[email protected]>
This patch adds documentation for the devicetree bindings used by the DT files of Cavium Thunder SoC platforms.
--- .../devicetree/bindings/arm/cavium-thunder.txt | 9 +++++++++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + 2 files changed, 10 insertions(+), 0 deletions(-)
Documentation/devicetree/bindings/arm/cavium-thunder.txt new file +9 -0
@@ -0,0 +1,9 @@ +Cavium Thunder platform device tree bindings +--------------------------------------------- + +Boards with Cavium's Thunder SoC shall have following properties. + +Root Node +--------- +Required root node properties: + - compatible = "cavium,thunder";
Documentation/devicetree/bindings/arm/cpus.txt +1 -0
@@ -163,6 +163,7 @@ nodes to be present and contain the properties described below. "arm,cortex-r4" "arm,cortex-r5" "arm,cortex-r7" + "cavium,thunder" "faraday,fa526" "intel,sa110" "intel,sa1100"
Signature · 1 line
1.7.1
Arnd Bergmann
maintainerPATCH v2 3/3 Documentation: add devicetree bindings for Cavium Thunder SoC
Quoted 20 lines · On Monday 24 March 2014 14:39:39 mohun106 at gmail.com wrote:
Documentation/devicetree/bindings/arm/cavium-thunder.txt new file +9
-0@@ -0,0 +1,9 @@ +Cavium Thunder platform device tree bindings +--------------------------------------------- + +Boards with Cavium's Thunder SoC shall have following properties. + +Root Node +--------- +Required root node properties: + - compatible = "cavium,thunder";Documentation/devicetree/bindings/arm/cpus.txt +0
-0
Documentation/devicetree/bindings/arm/cpus.txt nodes to be present and contain the properties described below. · line 169
Quoted 7 lines
Documentation/devicetree/bindings/arm/cpus.txt +1
-0@@ -163,6 +163,7 @@ nodes to be present and contain the properties described below. "arm,cortex-r4" "arm,cortex-r5" "arm,cortex-r7" + "cavium,thunder" "faraday,fa526" "intel,sa110" "intel,sa1100"
It seems very confusing to use the same name for both the SoC and the CPU core. Can you guarantee that there will never be another SoC with the same core, or a different CPU core in a SoC with the same name?
If not, please be more specific here and use the exact model names rather than the product names.
Arnd
PATCH v2 3/3 Documentation: add devicetree bindings for Cavium Thunder SoC
Quoted 34 lines · Arnd Bergmann
Quoted 20 lines · On Monday 24 March 2014 14:39:39 mohun106 at gmail.com wrote:
Documentation/devicetree/bindings/arm/cavium-thunder.txt new file +9
-0@@ -0,0 +1,9 @@ +Cavium Thunder platform device tree bindings +--------------------------------------------- + +Boards with Cavium's Thunder SoC shall have following properties. + +Root Node +--------- +Required root node properties: + - compatible = "cavium,thunder";Documentation/devicetree/bindings/arm/cpus.txt +0
-0Documentation/devicetree/bindings/arm/cpus.txt nodes to be present and contain the properties described below. · line 169
Quoted 7 lines
Documentation/devicetree/bindings/arm/cpus.txt +1
-0@@ -163,6 +163,7 @@ nodes to be present and contain the properties described below. "arm,cortex-r4" "arm,cortex-r5" "arm,cortex-r7" + "cavium,thunder" "faraday,fa526" "intel,sa110" "intel,sa1100"It seems very confusing to use the same name for both the SoC and the CPU core. Can you guarantee that there will never be another SoC with the same core, or a different CPU core in a SoC with the same name?
Quoted 2 lines
If not, please be more specific here and use the exact model names rather than the product names.
OK, will fix this once I discuss this internally.
Quoted 2 lines
Arnd