target-arm: support AArch32 ID registers in AArch64 mode
PATCH 1/1 target-arm: support AArch32 ID registers in AArch64 mode
From: Rob Herring <[email protected]>
ARMv8 has both AArch32 and AArch64 versions of ID registers. Both sets of registers are accessible in AArch64 state, but only . Update the definitions to allow AArch64 access.
This fixes booting on recent (linux-next for 3.15) linux kernels which add access to ID_ISAR5.
Signed-off-by Rob Herring <[email protected]>
---
This belongs as part of Peter's series for AArch64 system emulation. Most of the necessary register values are already defined for the Cortex-A57.
target-arm/helper.c | 70 ++++++++++++++++++++++++++++++++--------------------- 1 file changed, 42 insertions(+), 28 deletions(-)
target-arm/helper.c +42 -28
@@ -1919,47 +1919,61 @@ void register_cp_regs_for_features(ARMCPU *cpu)if (arm_feature (env,ARM_FEATURE_V6 )) {/* The ID registers all have impdef reset values */ ARMCPRegInfo v6_idregs[] = { - { .name ="ID_PFR0" , .cp =15 , .crn =0 , .crm =1 , - .opc1 =0 , .opc2 =0 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_PFR0" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =1 , .opc1 =0 , .opc2 =0 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_pfr0 }, - { .name ="ID_PFR1" , .cp =15 , .crn =0 , .crm =1 , - .opc1 =0 , .opc2 =1 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_PFR1" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =1 , .opc1 =0 , .opc2 =1 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_pfr1 }, - { .name ="ID_DFR0" , .cp =15 , .crn =0 , .crm =1 , - .opc1 =0 , .opc2 =2 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_DFR0" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =1 , .opc1 =0 , .opc2 =2 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_dfr0 }, - { .name ="ID_AFR0" , .cp =15 , .crn =0 , .crm =1 , - .opc1 =0 , .opc2 =3 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_AFR0" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =1 , .opc1 =0 , .opc2 =3 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_afr0 }, - { .name ="ID_MMFR0" , .cp =15 , .crn =0 , .crm =1 , - .opc1 =0 , .opc2 =4 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_MMFR0" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =1 , .opc1 =0 , .opc2 =4 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_mmfr0 }, - { .name ="ID_MMFR1" , .cp =15 , .crn =0 , .crm =1 , - .opc1 =0 , .opc2 =5 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_MMFR1" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =1 , .opc1 =0 , .opc2 =5 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_mmfr1 }, - { .name ="ID_MMFR2" , .cp =15 , .crn =0 , .crm =1 , - .opc1 =0 , .opc2 =6 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_MMFR2" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =1 , .opc1 =0 , .opc2 =6 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_mmfr2 }, - { .name ="ID_MMFR3" , .cp =15 , .crn =0 , .crm =1 , - .opc1 =0 , .opc2 =7 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_MMFR3" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =1 , .opc1 =0 , .opc2 =7 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_mmfr3 }, - { .name ="ID_ISAR0" , .cp =15 , .crn =0 , .crm =2 , - .opc1 =0 , .opc2 =0 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_ISAR0" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =2 , .opc1 =0 , .opc2 =0 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_isar0 }, - { .name ="ID_ISAR1" , .cp =15 , .crn =0 , .crm =2 , - .opc1 =0 , .opc2 =1 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_ISAR1" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =2 , .opc1 =0 , .opc2 =1 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_isar1 }, - { .name ="ID_ISAR2" , .cp =15 , .crn =0 , .crm =2 , - .opc1 =0 , .opc2 =2 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_ISAR2" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =2 , .opc1 =0 , .opc2 =2 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_isar2 }, - { .name ="ID_ISAR3" , .cp =15 , .crn =0 , .crm =2 , - .opc1 =0 , .opc2 =3 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_ISAR3" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =2 , .opc1 =0 , .opc2 =3 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_isar3 }, - { .name ="ID_ISAR4" , .cp =15 , .crn =0 , .crm =2 , - .opc1 =0 , .opc2 =4 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_ISAR4" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =2 , .opc1 =0 , .opc2 =4 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_isar4 }, - { .name ="ID_ISAR5" , .cp =15 , .crn =0 , .crm =2 , - .opc1 =0 , .opc2 =5 , .access =PL1_R , .type =ARM_CP_CONST , + { .name ="ID_ISAR5" , .state =ARM_CP_STATE_BOTH , + .opc0 =3 , .crn =0 , .crm =2 , .opc1 =0 , .opc2 =5 , + .access =PL1_R , .type =ARM_CP_CONST , .resetvalue = cpu->id_isar5 },/* 6..7 are as yet unallocated and must RAZ */ { .name ="ID_ISAR6" , .cp =15 , .crn =0 , .crm =2 ,
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1.8.3.2