drm/i915/bdw: Add WT caching ability
Subsystems (2)
PATCH 1/2 drm/i915/bdw: Add WT caching ability
I don't have any insight on what parts can do what. The docs do seem to suggest WT caching works in at least the same manner as it doesn't on Haswell.
The addr = 0 is to shut up GCC:drivers/gpu/drm/i915/i915_gem_gtt.c:80:7: warning: 'addr' may be used uninitialized in this function [-Wmaybe-uninitialized]
Signed-off-by Ben Widawsky <[email protected]>
--- drivers/gpu/drm/i915/i915_drv.h | 11 ++++++----- drivers/gpu/drm/i915/i915_gem_gtt.c | 17 +++++++++++++---- 2 files changed, 19 insertions(+), 9 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +6 -5
@@ -1822,11 +1822,12 @@ struct drm_i915_cmd_table {#define BSD_RING (1<<VCS)#define BLT_RING (1<<BCS)#define VEBOX_RING (1<<VECS) -#define HAS_BSD (dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) -#define HAS_BLT (dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) -#define HAS_VEBOX (dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) -#define HAS_LLC (dev) (INTEL_INFO(dev)->has_llc) -#define HAS_WT (dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) +#define HAS_BSD (dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) +#define HAS_BLT (dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) +#define HAS_VEBOX (dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) +#define HAS_LLC (dev) (INTEL_INFO(dev)->has_llc) +#define HAS_WT (dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ + to_i915(dev)->ellc_size)#define I915_NEED_GFX_HWS (dev) (INTEL_INFO(dev)->need_gfx_hws)#define HAS_HW_CONTEXTS (dev) (INTEL_INFO(dev)->gen >= 6)
drivers/gpu/drm/i915/i915_gem_gtt.c +13 -4
@@ -68,10 +68,19 @@ static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, {gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW :0 ; pte |= addr; -if (level !=I915_CACHE_NONE ) - pte |=PPAT_CACHED_INDEX ; -else + +switch (level) { +case I915_CACHE_NONE : pte |=PPAT_UNCACHED_INDEX ; +break ; +case I915_CACHE_WT : + pte |=PPAT_DISPLAY_ELLC_INDEX ; +break ; +default : + pte |=PPAT_CACHED_INDEX ; +break ; + } +return pte; }
@@ -1367,7 +1376,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;int i =0 ;struct sg_page_iter sg_iter; -dma_addr_t addr; +dma_addr_t addr =0 ;for_each_sg_page (st->sgl, &sg_iter, st->nents,0 ) { addr = sg_dma_address(sg_iter.sg) +
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1.9.1
PATCH 2/2 drm/i915/bdw: enable eDRAM.
The same register exists for querying and programming eDRAM AKA eLLC. So we can simply use it. For now, use all the same defaults as we had for Haswell, since like Haswell, I have no further details.
I do not actually have a part with eDRAM, so I cannot test this.
Signed-off-by Ben Widawsky <[email protected]>
--- drivers/gpu/drm/i915/intel_uncore.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_uncore.c +1 -1
@@ -370,7 +370,7 @@ void intel_uncore_early_sanitize(struct drm_device *dev)if (HAS_FPGA_DBG_UNCLAIMED (dev))__raw_i915_write32 (dev_priv,FPGA_DBG ,FPGA_DBG_RM_NOCLAIM ); -if (IS_HASWELL (dev) && +if ((IS_HASWELL (dev) ||IS_BROADWELL (dev)) && (__raw_i915_read32 (dev_priv,HSW_EDRAM_PRESENT ) ==1 )) {/* The docs do not explain exactly how the calculation can be * made. It is somewhat guessable, but for now, it's always
Signature · 1 line
1.9.1
Quoted 4 lines · Ben Widawsky
I don't have any insight on what parts can do what. The docs do seem to suggest WT caching works in at least the same manner as it doesn't on Haswell.
That's a freudian slip... s/doesn't/does/
Quoted 75 lines
The addr = 0 is to shut up GCC:
drivers/gpu/drm/i915/i915_gem_gtt.c:80:7: warning: 'addr' may be used uninitialized in this function [-Wmaybe-uninitialized]Signed-off-by Ben Widawsky <[email protected]>--- drivers/gpu/drm/i915/i915_drv.h | 11 ++++++----- drivers/gpu/drm/i915/i915_gem_gtt.c | 17 +++++++++++++---- 2 files changed, 19 insertions(+), 9 deletions(-)drivers/gpu/drm/i915/i915_drv.h +6
-5@@ -1822,11 +1822,12 @@ struct drm_i915_cmd_table {#define BSD_RING (1<<VCS)#define BLT_RING (1<<BCS)#define VEBOX_RING (1<<VECS) -#define HAS_BSD (dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) -#define HAS_BLT (dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) -#define HAS_VEBOX (dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) -#define HAS_LLC (dev) (INTEL_INFO(dev)->has_llc) -#define HAS_WT (dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) +#define HAS_BSD (dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) +#define HAS_BLT (dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) +#define HAS_VEBOX (dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) +#define HAS_LLC (dev) (INTEL_INFO(dev)->has_llc) +#define HAS_WT (dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ + to_i915(dev)->ellc_size)#define I915_NEED_GFX_HWS (dev) (INTEL_INFO(dev)->need_gfx_hws)#define HAS_HW_CONTEXTS (dev) (INTEL_INFO(dev)->gen >= 6)drivers/gpu/drm/i915/i915_gem_gtt.c +13
-4@@ -68,10 +68,19 @@ static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, {gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW :0 ; pte |= addr; -if (level !=I915_CACHE_NONE ) - pte |=PPAT_CACHED_INDEX ; -else + +switch (level) { +case I915_CACHE_NONE : pte |=PPAT_UNCACHED_INDEX ; +break ; +case I915_CACHE_WT : + pte |=PPAT_DISPLAY_ELLC_INDEX ; +break ; +default : + pte |=PPAT_CACHED_INDEX ; +break ; + } +return pte; }@@ -1367,7 +1376,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;int i =0 ;struct sg_page_iter sg_iter; -dma_addr_t addr; +dma_addr_t addr =0 ;for_each_sg_page (st->sgl, &sg_iter, st->nents,0 ) { addr = sg_dma_address(sg_iter.sg) +Signature · 6 lines
1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Signature · 1 line
Ben Widawsky, Intel Open Source Technology Center