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ARM: socfpga: dts: fix pdma interrupt

PATCH Superseded Steffen Trumtrar 2 participants 10 messages Mar 31, 2014 – Apr 2, 2014

Subsystems (2)
Device tree bindings Arm and arm64 SoC sub-architectures (common parts)

v1 of 2 Superseded Latest is v2 →

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Steffen Trumtrar

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#0 lore raw

PATCH 1/6 ARM: socfpga: dts: fix pdma interrupt

The first interrupt is not at 180 but 104. Fix it.

Signed-off-by Steffen Trumtrar <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/socfpga.dtsi +1 -1
index 537f1a5..0c3344f 100644
@@ -75,7 +75,7 @@
 			pdma: pdma at ffe01000 {
 				compatible = "arm,pl330", "arm,primecell";
 				reg = <0xffe01000 0x1000>;
-				interrupts = <0 180 4>;
+				interrupts = <0 104 4>;
 				#dma-cells = <1>;
 				#dma-channels = <8>;
 				#dma-requests = <32>;
Signature · 1 line
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author
#1 lore raw

PATCH 2/6 ARM: socfpga: dts: add remaining interrupts for pdma

Signed-off-by Steffen Trumtrar <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)
arch/arm/boot/dts/socfpga.dtsi +8 -1
index 0c3344f..7867e7f 100644
@@ -75,7 +75,14 @@
 			pdma: pdma at ffe01000 {
 				compatible = "arm,pl330", "arm,primecell";
 				reg = <0xffe01000 0x1000>;
-				interrupts = <0 104 4>;
+				interrupts = <0 104 4>,
+					     <0 105 4>,
+					     <0 106 4>,
+					     <0 107 4>,
+					     <0 108 4>,
+					     <0 109 4>,
+					     <0 110 4>,
+					     <0 111 4>;
 				#dma-cells = <1>;
 				#dma-channels = <8>;
 				#dma-requests = <32>;
Signature · 1 line
1.9.1
author
#2 lore raw

PATCH 3/6 ARM: socfpga: dts: add i2c busses

In reply to Steffen Trumtrar

Add all 4 i2c busses.

Signed-off-by Steffen Trumtrar <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
arch/arm/boot/dts/socfpga.dtsi +44 -0
index 7867e7f..d0594c3 100644
@@ -470,6 +470,50 @@
 			status = "disabled";
 		};
 
+		i2c0: i2c at 0xffc04000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc04000 0x1000>;
+			clock-frequency = <400000000>;
+			clocks = <&l4_sp_clk>;
+			interrupts = <0 158 0x4>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 0xffc05000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc05000 0x1000>;
+			clock-frequency = <100000000>;
+			clocks = <&l4_sp_clk>;
+			interrupts = <0 159 0x4>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 0xffc06000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc06000 0x1000>;
+			clock-frequency = <100000000>;
+			clocks = <&l4_sp_clk>;
+			interrupts = <0 160 0x4>;
+			status = "disabled";
+		};
+
+		i2c3: i2c at 0xffc07000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc07000 0x1000>;
+			clock-frequency = <100000000>;
+			clocks = <&l4_sp_clk>;
+			interrupts = <0 161 0x4>;
+			status = "disabled";
+		};
+
 		L2: l2-cache at fffef000 {
 			compatible = "arm,pl310-cache";
 			reg = <0xfffef000 0x1000>;
Signature · 1 line
1.9.1
#3 lore raw

PATCH 3/6 ARM: socfpga: dts: add i2c busses

Quoted 12 lines · Steffen Trumtrar

Add all 4 i2c busses.

Signed-off-by Steffen Trumtrar <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
arch/arm/boot/dts/socfpga.dtsi +0 -0
index 7867e7f..d0594c3 100644

arch/arm/boot/dts/socfpga.dtsi line 478

Quoted 9 lines
arch/arm/boot/dts/socfpga.dtsi +6 -0
@@ -470,6 +470,50 @@
 			status = "disabled";
 		};
 
+		i2c0: i2c at 0xffc04000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc04000 0x1000>;
+			clock-frequency = <400000000>;

"clock-frequency" is not needed as the driver can get the clock frequency from the clock driver.

arch/arm/boot/dts/socfpga.dtsi line 489

Quoted 11 lines
arch/arm/boot/dts/socfpga.dtsi +11 -0
+			clocks = <&l4_sp_clk>;
+			interrupts = <0 158 0x4>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 0xffc05000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc05000 0x1000>;
+			clock-frequency = <100000000>;

Same..

arch/arm/boot/dts/socfpga.dtsi line 500

Quoted 11 lines
arch/arm/boot/dts/socfpga.dtsi +11 -0
+			clocks = <&l4_sp_clk>;
+			interrupts = <0 159 0x4>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 0xffc06000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc06000 0x1000>;
+			clock-frequency = <100000000>;

Same...

arch/arm/boot/dts/socfpga.dtsi line 511

Quoted 11 lines
arch/arm/boot/dts/socfpga.dtsi +11 -0
+			clocks = <&l4_sp_clk>;
+			interrupts = <0 160 0x4>;
+			status = "disabled";
+		};
+
+		i2c3: i2c at 0xffc07000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc07000 0x1000>;
+			clock-frequency = <100000000>;

Same..

thanks,
Dinh

Quoted 8 lines
arch/arm/boot/dts/socfpga.dtsi +5 -0
+			clocks = <&l4_sp_clk>;
+			interrupts = <0 161 0x4>;
+			status = "disabled";
+		};
+
 		L2: l2-cache at fffef000 {
 			compatible = "arm,pl310-cache";
 			reg = <0xfffef000 0x1000>;
author
#4 lore raw

PATCH 3/6 ARM: socfpga: dts: add i2c busses

Hi!

Quoted 16 lines · Dinh Nguyen
Quoted 15 lines · Steffen Trumtrar

Add all 4 i2c busses.

Signed-off-by Steffen Trumtrar <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
arch/arm/boot/dts/socfpga.dtsi +0 -0
index 7867e7f..d0594c3 100644
@@ -470,6 +470,50 @@
 			status = "disabled";
 		};
Quoted 10 lines

arch/arm/boot/dts/socfpga.dtsi line 478

Quoted 6 lines
arch/arm/boot/dts/socfpga.dtsi +6 -0
+		i2c0: i2c at 0xffc04000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc04000 0x1000>;
+			clock-frequency = <400000000>;

"clock-frequency" is not needed as the driver can get the clock frequency from the clock driver.

You are right of course. I will remove that.
Although, I think I remember seeing patches that add this functionality to the driver. So you can change the speed setting. But even than you are right, as something like that wouldn't belong here in the dtsi.

Quoted 44 lines

arch/arm/boot/dts/socfpga.dtsi line 489

Quoted 11 lines
arch/arm/boot/dts/socfpga.dtsi +11 -0
+			clocks = <&l4_sp_clk>;
+			interrupts = <0 158 0x4>;
+			status = "disabled";
+		};
+
+		i2c1: i2c at 0xffc05000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc05000 0x1000>;
+			clock-frequency = <100000000>;

Same..

arch/arm/boot/dts/socfpga.dtsi line 500

Quoted 11 lines
arch/arm/boot/dts/socfpga.dtsi +11 -0
+			clocks = <&l4_sp_clk>;
+			interrupts = <0 159 0x4>;
+			status = "disabled";
+		};
+
+		i2c2: i2c at 0xffc06000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc06000 0x1000>;
+			clock-frequency = <100000000>;

Same...

arch/arm/boot/dts/socfpga.dtsi line 511

Quoted 11 lines
arch/arm/boot/dts/socfpga.dtsi +11 -0
+			clocks = <&l4_sp_clk>;
+			interrupts = <0 160 0x4>;
+			status = "disabled";
+		};
+
+		i2c3: i2c at 0xffc07000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xffc07000 0x1000>;
+			clock-frequency = <100000000>;

Same..

thanks,
Dinh

Quoted 11 lines

arch/arm/boot/dts/socfpga.dtsi line 519

Quoted 8 lines
arch/arm/boot/dts/socfpga.dtsi +5 -0
+			clocks = <&l4_sp_clk>;
+			interrupts = <0 161 0x4>;
+			status = "disabled";
+		};
+
 		L2: l2-cache at fffef000 {
 			compatible = "arm,pl310-cache";
 			reg = <0xfffef000 0x1000>;

Thanks,
Steffen

Signature · 4 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
author
#5 lore raw

PATCH 4/6 ARM: socfpga: dts: add can0+1

In reply to Steffen Trumtrar

Add both can controllers to the dtsi.

Signed-off-by Steffen Trumtrar <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
arch/arm/boot/dts/socfpga.dtsi +16 -0
index d0594c3..51148b8 100644
@@ -470,6 +470,22 @@
 			status = "disabled";
 		};
 
+		can0: can at 0xffc00000 {
+			compatible = "bosch,d_can";
+			reg = <0xffc00000 0x1000>;
+			interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
+			clocks = <&can0_clk>;
+			status = "disabled";
+		};
+
+		can1: can at 0xffc01000 {
+			compatible = "bosch,d_can";
+			reg = <0xffc01000 0x1000>;
+			interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
+			clocks = <&can1_clk>;
+			status = "disabled";
+		};
+
 		i2c0: i2c at 0xffc04000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
Signature · 1 line
1.9.1
#6 lore raw

PATCH 4/6 ARM: socfpga: dts: add can0+1

Quoted 12 lines · Steffen Trumtrar

Add both can controllers to the dtsi.

Signed-off-by Steffen Trumtrar <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
arch/arm/boot/dts/socfpga.dtsi +0 -0
index d0594c3..51148b8 100644

arch/arm/boot/dts/socfpga.dtsi line 473

Quoted 4 lines
arch/arm/boot/dts/socfpga.dtsi +1 -0
@@ -470,6 +470,22 @@
 			status = "disabled";
 		};
 
+		can0: can at 0xffc00000 {

I've seen a comment from Rob Herring to remove the 0x here.

arch/arm/boot/dts/socfpga.dtsi line 481

Quoted 8 lines
arch/arm/boot/dts/socfpga.dtsi +8 -0
+			compatible = "bosch,d_can";
+			reg = <0xffc00000 0x1000>;
+			interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
+			clocks = <&can0_clk>;
+			status = "disabled";
+		};
+
+		can1: can at 0xffc01000 {

Same...

arch/arm/boot/dts/socfpga.dtsi line 489

Quoted 8 lines
arch/arm/boot/dts/socfpga.dtsi +7 -0
+			compatible = "bosch,d_can";
+			reg = <0xffc01000 0x1000>;
+			interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
+			clocks = <&can1_clk>;
+			status = "disabled";
+		};
+
 		i2c0: i2c at 0xffc04000 {

Same comment here..but would apply to patch 3/6.

Thanks,

Dinh

Quoted 2 lines
arch/arm/boot/dts/socfpga.dtsi +0 -0
 			#address-cells = <1>;
 			#size-cells = <0>;
author
#7 lore raw

PATCH 4/6 ARM: socfpga: dts: add can0+1

Hi Dinh!

Quoted 16 lines · Dinh Nguyen
Quoted 15 lines · Steffen Trumtrar

Add both can controllers to the dtsi.

Signed-off-by Steffen Trumtrar <[email protected]>
---
 arch/arm/boot/dts/socfpga.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
arch/arm/boot/dts/socfpga.dtsi +0 -0
index d0594c3..51148b8 100644
@@ -470,6 +470,22 @@
 			status = "disabled";
 		};
Quoted 3 lines

arch/arm/boot/dts/socfpga.dtsi line 473

Quoted 1 line
arch/arm/boot/dts/socfpga.dtsi +1 -0
+		can0: can at 0xffc00000 {

I've seen a comment from Rob Herring to remove the 0x here.

Yep, you are right. I missed this as it looks weird to me without the 0x, but common practice is without...

Quoted 11 lines

arch/arm/boot/dts/socfpga.dtsi line 481

Quoted 8 lines
arch/arm/boot/dts/socfpga.dtsi +8 -0
+			compatible = "bosch,d_can";
+			reg = <0xffc00000 0x1000>;
+			interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
+			clocks = <&can0_clk>;
+			status = "disabled";
+		};
+
+		can1: can at 0xffc01000 {

Same...

Quoted 11 lines

arch/arm/boot/dts/socfpga.dtsi line 489

Quoted 8 lines
arch/arm/boot/dts/socfpga.dtsi +7 -0
+			compatible = "bosch,d_can";
+			reg = <0xffc01000 0x1000>;
+			interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
+			clocks = <&can1_clk>;
+			status = "disabled";
+		};
+
 		i2c0: i2c at 0xffc04000 {

Same comment here..but would apply to patch 3/6.

I will fix all those.

Thanks,
Steffen

Signature · 4 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
author
#8 lore raw

PATCH 5/6 ARM: socfpga: dts: add support for EBV SOCrates

In reply to Steffen Trumtrar

The SOCrates is a SOCFpga-Cyclone5 based board from EBV. Add support for it.

Signed-off-by Steffen Trumtrar <[email protected]>
---
 arch/arm/boot/dts/Makefile                      |  1 +
 arch/arm/boot/dts/socfpga_cyclone5_socrates.dts | 41 +++++++++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
arch/arm/boot/dts/Makefile +1 -0
index 0320303..4308695 100644
@@ -267,6 +267,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
 	socfpga_cyclone5_socdk.dtb \
 	socfpga_cyclone5_sockit.dtb \
+	socfpga_cyclone5_socrates.dtb \
 	socfpga_vt.dtb
 dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
 	spear1340-evb.dtb
arch/arm/boot/dts/socfpga_cyclone5_socrates.dts new file +41 -0

41 lines not on this page · raw message

Signature · 1 line
1.9.1
author
#9 lore raw

PATCH 6/6 ARM: socfpga: dts: add rtc on i2c0 to socrates

In reply to Steffen Trumtrar

The SOCrates has an M41T82M RTC on i2c0. Add it.

Signed-off-by Steffen Trumtrar <[email protected]>
---
 arch/arm/boot/dts/socfpga_cyclone5_socrates.dts | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +9 -0
index 1e31f32..f8d17dc 100644
@@ -36,6 +36,15 @@
 	status = "okay";
 };
 
+&i2c0 {
+	status = "okay";
+
+	rtc: rtc at 68 {
+		compatible = "stm,m41t82";
+		reg = <0x68>;
+	};
+};
+
 &mmc {
 	status = "okay";
 };
Signature · 1 line
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