PCI: tegra: Overhaul regulator usage
Subsystems (5)
cover PCI: tegra: Overhaul regulator usage
The current device tree binding for the regulator setup on Tegra PCIe is not accurate. While it does work for current use-cases, that's likely by accident rather than design. This series replaces the existing set of power-supply properties with a new set that accurately describes the inputs of the IP block (depending on SoC generation).
As a heads-up, this breaks backwards compatibility with prior versions of the device tree bindings, but I don't see a reason why that should keep us from fixing this properly. Not many people are currently using these bindings and those who are are most likely tracking upstream development closely enough not to be impacted by this.
I've aimed to keep the series bisectible, which has the downside of interleaving patches to unrelated trees (ARM and PCI). I'm hoping that perhaps we can find a way to merge this as a whole to keep it possible to bisect across the series. Although again, I guess it wouldn't be all that bad if that wasn't the case, given how little PCIe is actually being used.
Thanks,
Thierry
Thierry Reding (5):
PCI: tegra: Overhaul regulator usage
ARM: tegra: Add new PCIe regulator properties
PCI: tegra: Implement accurate power supply scheme
PCI: tegra: Remove deprecated power supply properties
ARM: tegra: Remove legacy PCIe power supply properties
.../bindings/pci/nvidia,tegra20-pcie.txt | 30 ++++- arch/arm/boot/dts/tegra20-harmony.dts | 8 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 7 +- arch/arm/boot/dts/tegra20-trimslice.dts | 8 +- arch/arm/boot/dts/tegra30-beaver.dts | 12 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 11 +- drivers/pci/host/pci-tegra.c | 146 ++++++++++++--------- 7 files changed, 148 insertions(+), 74 deletions(-)
Signature · 1 line
1.9.1
RFC 1/5 PCI: tegra: Overhaul regulator usage
The current usage of regulators for the Tegra PCIe block is wrong. It doesn't accurately reflect the actual supply inputs of the IP block and therefore isn't as flexible as it should be. Rectify this by describing all possible supply inputs in the device tree binding documentation and deprecate the old supply properties.
--- .../bindings/pci/nvidia,tegra20-pcie.txt | 35 ++++++++++++++++++++-- 1 file changed, 32 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +32 -3
@@ -14,9 +14,6 @@ Required properties: - interrupt-names: Must include the following entries: "intr": The Tegra interrupt that is asserted for controller interrupts "msi": The Tegra interrupt that is asserted when an MSI is received -- pex-clk-supply: Supply voltage for internal reference clock -- vdd-supply: Power supply for controller (1.05V) -- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20) - bus-range: Range of bus numbers associated with this controller - #address-cells: Address representation for root ports (must be 3) - cell 0 specifies the bus and device numbers of the root port:
@@ -60,6 +57,38 @@ Required properties: - afi - pcie_x +Power supplies for Tegra20: +- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. +- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. +- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must + supply 1.05 V. +- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must + supply 1.05 V. +- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V. + +Power supplies for Tegra30: +- Required: + - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must + supply 1.05 V. + - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must + supply 1.05 V. + - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must + supply 1.8 V. + - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks. + Must supply 3.3 V. +- Optional: + - If port 0 is enabled: + - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V. + - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. + - If at least one of ports 1 and 2 is enabled: + - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V. + - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. + +Deprecated supplies: +- pex-clk-supply: Supply voltage for internal reference clock +- vdd-supply: Power supply for controller (1.05V) +- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20) + Root ports are defined as subnodes of the PCIe controller node. Required properties:
Signature · 1 line
1.9.1
RFC 1/5 PCI: tegra: Overhaul regulator usage
Quoted 9 lines · Thierry Reding
The current usage of regulators for the Tegra PCIe block is wrong. It doesn't accurately reflect the actual supply inputs of the IP block and therefore isn't as flexible as it should be. Rectify this by describing all possible supply inputs in the device tree binding documentation and deprecate the old supply properties.
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +1
-0+Power supplies for Tegra30:
...
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt Required properties: · line 85
Quoted 7 lines
+- Optional:
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +6
-0+ - If port 0 is enabled: + - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V. + - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. + - If at least one of ports 1 and 2 is enabled: + - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V. + - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
Did you get confirmation from HW/... that the mapping from pexa/b to PCIe ports you document above is correct? IIRC the two supplies might be related to lanes rather than ports?
RFC 1/5 PCI: tegra: Overhaul regulator usage
Quoted 19 lines · Stephen Warren
Quoted 9 lines · Thierry Reding
The current usage of regulators for the Tegra PCIe block is wrong. It doesn't accurately reflect the actual supply inputs of the IP block and therefore isn't as flexible as it should be. Rectify this by describing all possible supply inputs in the device tree binding documentation and deprecate the old supply properties.
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +1
-0+Power supplies for Tegra30:...
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt Required properties: · line 85
Quoted 7 lines
+- Optional:
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +6
-0+ - If port 0 is enabled: + - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V. + - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. + - If at least one of ports 1 and 2 is enabled: + - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V. + - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
Quoted 3 lines
Did you get confirmation from HW/... that the mapping from pexa/b to PCIe ports you document above is correct? IIRC the two supplies might be related to lanes rather than ports?
Not yet, which is the primary reason this is still RFC. Just wanted to get early feedback on the general direction of the series.
Thierry
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RFC 2/5 ARM: tegra: Add new PCIe regulator properties
In reply to Thierry RedingThese new properties more accurately reflect the real connections of the boards and therefore make it easier to match them up with schematics.
--- arch/arm/boot/dts/tegra20-harmony.dts | 10 +++++++++- arch/arm/boot/dts/tegra20-tamonten.dtsi | 7 +++++++ arch/arm/boot/dts/tegra20-trimslice.dts | 8 ++++++++ arch/arm/boot/dts/tegra30-beaver.dts | 11 +++++++++++ arch/arm/boot/dts/tegra30-cardhu.dtsi | 10 ++++++++++ 5 files changed, 45 insertions(+), 1 deletion(-)
arch/arm/boot/dts/tegra20-harmony.dts +9 -1
@@ -561,9 +561,17 @@ }; pcie-controller at 80003000 { + status = "okay"; + + avdd-pex-supply = <&pci_vdd_reg>; + vdd-pex-supply = <&pci_vdd_reg>; + avdd-pex-pll-supply = <&pci_vdd_reg>; + avdd-plle-supply = <&pci_vdd_reg>; + vddio-pex-clk-supply = <&pci_clk_reg>; + + /* deprecated */ pex-clk-supply = <&pci_clk_reg>; vdd-supply = <&pci_vdd_reg>; - status = "okay"; pci at 1,0 { status = "okay";
arch/arm/boot/dts/tegra20-tamonten.dtsi +7 -0
@@ -473,6 +473,13 @@ }; pcie-controller at 80003000 { + avdd-pex-supply = <&pci_vdd_reg>; + vdd-pex-supply = <&pci_vdd_reg>; + avdd-pex-pll-supply = <&pci_vdd_reg>; + avdd-plle-supply = <&pci_vdd_reg>; + vddio-pex-clk-supply = <&pci_clk_reg>; + + /* deprecated */ pex-clk-supply = <&pci_clk_reg>; vdd-supply = <&pci_vdd_reg>; };
arch/arm/boot/dts/tegra20-trimslice.dts +8 -0
@@ -318,6 +318,14 @@ pcie-controller at 80003000 { status = "okay"; + + avdd-pex-supply = <&pci_vdd_reg>; + vdd-pex-supply = <&pci_vdd_reg>; + avdd-pex-pll-supply = <&pci_vdd_reg>; + avdd-plle-supply = <&pci_vdd_reg>; + vddio-pex-clk-supply = <&pci_clk_reg>; + + /* deprecated */ pex-clk-supply = <&pci_clk_reg>; vdd-supply = <&pci_vdd_reg>;
arch/arm/boot/dts/tegra30-beaver.dts +11 -0
@@ -17,6 +17,17 @@ pcie-controller at 00003000 { status = "okay"; + + avdd-pexa-supply = <&ldo1_reg>; + vdd-pexa-supply = <&ldo1_reg>; + avdd-pexb-supply = <&ldo1_reg>; + vdd-pexb-supply = <&ldo1_reg>; + avdd-pex-pll-supply = <&ldo1_reg>; + avdd-plle-supply = <&ldo1_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + hvdd-pex-supply = <&sys_3v3_pexs_reg>; + + /* deprecated */ pex-clk-supply = <&sys_3v3_pexs_reg>; vdd-supply = <&ldo1_reg>; avdd-supply = <&ldo2_reg>;
arch/arm/boot/dts/tegra30-cardhu.dtsi +10 -0
@@ -38,6 +38,16 @@ pcie-controller at 00003000 { status = "okay"; + + /* AVDD_PEXA and VDD_PEXA are grounded on Cardhu. */ + avdd-pexb-supply = <&ldo1_reg>; + vdd-pexb-supply = <&ldo1_reg>; + avdd-pex-pll-supply = <&ldo1_reg>; + hvdd-pex-supply = <&pex_hvdd_3v3_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + avdd-plle-supply = <&ldo2_reg>; + + /* deprecated */ pex-clk-supply = <&pex_hvdd_3v3_reg>; vdd-supply = <&ldo1_reg>; avdd-supply = <&ldo2_reg>;
Signature · 1 line
1.9.1
RFC 2/5 ARM: tegra: Add new PCIe regulator properties
arch/arm/boot/dts/tegra30-cardhu.dtsi line 42
Quoted 9 lines · Thierry Reding
These new properties more accurately reflect the real connections of the boards and therefore make it easier to match them up with schematics.
arch/arm/boot/dts/tegra30-cardhu.dtsi +2
-0pcie-controller at 00003000 { status = "okay"; + + /* AVDD_PEXA and VDD_PEXA are grounded on Cardhu. */
Perhaps add the word "inputs" before "are"?
RFC 2/5 ARM: tegra: Add new PCIe regulator properties
Quoted 4 lines · Stephen Warren
Quoted 2 lines · Thierry Reding
These new properties more accurately reflect the real connections of the boards and therefore make it easier to match them up with schematics.
Quoted 8 lines
arch/arm/boot/dts/tegra30-cardhu.dtsi line 42
Quoted 6 lines
arch/arm/boot/dts/tegra30-cardhu.dtsi +2
-0pcie-controller at 00003000 { status = "okay"; + + /* AVDD_PEXA and VDD_PEXA are grounded on Cardhu. */Perhaps add the word "inputs" before "are"?
Done. Thanks,
Thierry
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RFC 3/5 PCI: tegra: Implement accurate power supply scheme
In reply to Thierry RedingThe current description of power supplies doesn't match the hardware. Instead it's designed to support the needs of current designs, which will break as soon as a new design appears that cannot be described using the current assumptions.
In order to fully support all possible future designs, all power supply inputs to the PCIe block need to be accurately described and separately configurable.
--- drivers/pci/host/pci-tegra.c | 146 ++++++++++++++++++++++++++----------------- 1 file changed, 87 insertions(+), 59 deletions(-)
drivers/pci/host/pci-tegra.c +87 -59
@@ -234,7 +234,6 @@ struct tegra_pcie_soc_data {bool has_pex_clkreq_en;bool has_pex_bias_ctrl;bool has_intr_prsnt_sense; -bool has_avdd_supply;bool has_cml_clk; };
@@ -275,9 +274,8 @@ struct tegra_pcie {unsigned int num_ports;u32 xbar_config; -struct regulator *pex_clk_supply; -struct regulator *vdd_supply; -struct regulator *avdd_supply; +struct regulator_bulk_data *supplies; +unsigned int num_supplies;const struct tegra_pcie_soc_data *soc_data;struct dentry *debugfs;
@@ -919,7 +917,6 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)static void tegra_pcie_power_off (struct tegra_pcie *pcie) { -const struct tegra_pcie_soc_data *soc = pcie->soc_data;int err;/* TODO: disable and unprepare clocks? */
@@ -930,23 +927,9 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)tegra_powergate_power_off (TEGRA_POWERGATE_PCIE ); -if (soc->has_avdd_supply) { - err =regulator_disable (pcie->avdd_supply); -if (err <0 ) -dev_warn (pcie->dev, -"failed to disable AVDD regulator: %d\n" , - err); - } - - err =regulator_disable (pcie->pex_clk_supply); + err =regulator_bulk_disable (pcie->num_supplies, pcie->supplies);if (err <0 ) -dev_warn (pcie->dev,"failed to disable pex-clk regulator: %d\n" , - err); - - err =regulator_disable (pcie->vdd_supply); -if (err <0 ) -dev_warn (pcie->dev,"failed to disable VDD regulator: %d\n" , - err); +dev_warn (pcie->dev,"failed to enable regulators: %d\n" , err); }static int tegra_pcie_power_on (struct tegra_pcie *pcie)
@@ -961,28 +944,9 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)tegra_powergate_power_off (TEGRA_POWERGATE_PCIE );/* enable regulators */ - err =regulator_enable (pcie->vdd_supply); -if (err <0 ) { -dev_err (pcie->dev,"failed to enable VDD regulator: %d\n" , err); -return err; - } - - err =regulator_enable (pcie->pex_clk_supply); -if (err <0 ) { -dev_err (pcie->dev,"failed to enable pex-clk regulator: %d\n" , - err); -return err; - } - -if (soc->has_avdd_supply) { - err =regulator_enable (pcie->avdd_supply); -if (err <0 ) { -dev_err (pcie->dev, -"failed to enable AVDD regulator: %d\n" , - err); -return err; - } - } + err =regulator_bulk_enable (pcie->num_supplies, pcie->supplies); +if (err <0 ) +dev_err (pcie->dev,"failed to enable regulators: %d\n" , err); err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, pcie->pex_clk,
@@ -1419,6 +1383,82 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,return -EINVAL ; } +/* +* Obtains the list of regulators required for a particular generation of the +* IP block. +* +* This would've been nice to do simply by providing static tables for use +* with the regulator_bulk_*() API, but unfortunately Tegra30 is a bit quirky +* in that it has two pairs or AVDD_PEX and VDD_PEX supplies (PEXA and PEXB) +* and either seems to be optional depending on which ports are being used. +*/ +static int tegra_pcie_get_regulators (struct tegra_pcie *pcie) +{ +struct device_node *np = pcie->dev->of_node; +unsigned int i =0 ; + +if (of_device_is_compatible (np,"nvidia,tegra30-pcie" )) { +bool need_pexa = false, need_pexb = false; +struct tegra_pcie_port *port; + +list_for_each_entry (port, &pcie->ports, list) { +dev_info (pcie->dev,"port %u enabled\n" , port->index); + +switch (port->index) { +case 0 : + need_pexa = true; +break ; + +case 1 : +case 2 : + need_pexb = true; +break ; + } + } + + pcie->num_supplies =4 + (need_pexa ?2 :0 ) + + (need_pexb ?2 :0 ); + + pcie->supplies =devm_kcalloc (pcie->dev, pcie->num_supplies, +sizeof (*pcie->supplies), +GFP_KERNEL ); +if (!pcie->supplies) +return -ENOMEM ; + + pcie->supplies[i++].supply ="avdd-pex-pll" ; + pcie->supplies[i++].supply ="hvdd-pex" ; + pcie->supplies[i++].supply ="vddio-pex-ctl" ; + pcie->supplies[i++].supply ="avdd-plle" ; + +if (need_pexa) { + pcie->supplies[i++].supply ="avdd-pexa" ; + pcie->supplies[i++].supply ="vdd-pexa" ; + } + +if (need_pexb) { + pcie->supplies[i++].supply ="avdd-pexb" ; + pcie->supplies[i++].supply ="vdd-pexb" ; + } + }else if (of_device_is_compatible (np,"nvidia,tegra20-pcie" )) { + pcie->num_supplies =5 ; + + pcie->supplies =devm_kcalloc (pcie->dev, pcie->num_supplies, +sizeof (*pcie->supplies), +GFP_KERNEL ); +if (!pcie->supplies) +return -ENOMEM ; + + pcie->supplies[0 ].supply ="avdd-pex" ; + pcie->supplies[1 ].supply ="vdd-pex" ; + pcie->supplies[2 ].supply ="avdd-pex-pll" ; + pcie->supplies[3 ].supply ="avdd-plle" ; + pcie->supplies[4 ].supply ="vddio-pex-clk" ; + } + +return devm_regulator_bulk_get (pcie->dev, pcie->num_supplies, + pcie->supplies); +} +static int tegra_pcie_parse_dt (struct tegra_pcie *pcie) {const struct tegra_pcie_soc_data *soc = pcie->soc_data;
@@ -1440,20 +1480,6 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)return -EINVAL ; } - pcie->vdd_supply =devm_regulator_get (pcie->dev,"vdd" ); -if (IS_ERR (pcie->vdd_supply)) -return PTR_ERR (pcie->vdd_supply); - - pcie->pex_clk_supply =devm_regulator_get (pcie->dev,"pex-clk" ); -if (IS_ERR (pcie->pex_clk_supply)) -return PTR_ERR (pcie->pex_clk_supply); - -if (soc->has_avdd_supply) { - pcie->avdd_supply =devm_regulator_get (pcie->dev,"avdd" ); -if (IS_ERR (pcie->avdd_supply)) -return PTR_ERR (pcie->avdd_supply); - } -for_each_of_pci_range (&parser, &range) {of_pci_range_to_resource (&range, np, &res);
@@ -1563,6 +1589,10 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)return err; } + err =tegra_pcie_get_regulators (pcie); +if (err <0 ) +return err; +return 0 ; }
@@ -1658,7 +1688,6 @@ static const struct tegra_pcie_soc_data tegra20_pcie_data = { .has_pex_clkreq_en = false, .has_pex_bias_ctrl = false, .has_intr_prsnt_sense = false, - .has_avdd_supply = false, .has_cml_clk = false, };
@@ -1670,7 +1699,6 @@ static const struct tegra_pcie_soc_data tegra30_pcie_data = { .has_pex_clkreq_en = true, .has_pex_bias_ctrl = true, .has_intr_prsnt_sense = true, - .has_avdd_supply = true, .has_cml_clk = true, };
Signature · 1 line
1.9.1
RFC 3/5 PCI: tegra: Implement accurate power supply scheme
Quoted 14 lines · Thierry Reding
The current description of power supplies doesn't match the hardware. Instead it's designed to support the needs of current designs, which will break as soon as a new design appears that cannot be described using the current assumptions.
In order to fully support all possible future designs, all power supply inputs to the PCIe block need to be accurately described and separately configurable.
drivers/pci/host/pci-tegra.c +0
-1@@ -930,23 +927,9 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie) - err =regulator_disable (pcie->pex_clk_supply);
drivers/pci/host/pci-tegra.c static void tegra_pcie_power_off(struct tegra_pcie *pcie) · line 930
Quoted 10 lines
drivers/pci/host/pci-tegra.c +2
-7+ err =regulator_bulk_disable (pcie->num_supplies, pcie->supplies);if (err <0 ) -dev_warn (pcie->dev,"failed to disable pex-clk regulator: %d\n" , - err); - - err =regulator_disable (pcie->vdd_supply); -if (err <0 ) -dev_warn (pcie->dev,"failed to disable VDD regulator: %d\n" , - err); +dev_warn (pcie->dev,"failed to enable regulators: %d\n" , err);
s/enable/disable/
RFC 3/5 PCI: tegra: Implement accurate power supply scheme
Quoted 14 lines · Stephen Warren
Quoted 12 lines · Thierry Reding
The current description of power supplies doesn't match the hardware. Instead it's designed to support the needs of current designs, which will break as soon as a new design appears that cannot be described using the current assumptions.
In order to fully support all possible future designs, all power supply inputs to the PCIe block need to be accurately described and separately configurable.
drivers/pci/host/pci-tegra.c +0
-0@@ -930,23 +927,9 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
Quoted 13 lines
drivers/pci/host/pci-tegra.c static void tegra_pcie_power_off(struct tegra_pcie *pcie) · line 932
Quoted 11 lines
drivers/pci/host/pci-tegra.c +2
-8- err =regulator_disable (pcie->pex_clk_supply); + err =regulator_bulk_disable (pcie->num_supplies, pcie->supplies);if (err <0 ) -dev_warn (pcie->dev,"failed to disable pex-clk regulator: %d\n" , - err); - - err =regulator_disable (pcie->vdd_supply); -if (err <0 ) -dev_warn (pcie->dev,"failed to disable VDD regulator: %d\n" , - err); +dev_warn (pcie->dev,"failed to enable regulators: %d\n" , err);s/enable/disable/
Good catch. Fixed, thanks,
Thierry
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RFC 4/5 PCI: tegra: Remove deprecated power supply properties
In reply to Thierry RedingThese power supply properties are no longer needed since the binding now contains the full set properties to accurately describe the power supply inputs of the Tegra PCIe block.
--- Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt | 5 ----- 1 file changed, 5 deletions(-)
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +0 -5
@@ -84,11 +84,6 @@ Power supplies for Tegra30: - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V. - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. -Deprecated supplies: -- pex-clk-supply: Supply voltage for internal reference clock -- vdd-supply: Power supply for controller (1.05V) -- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20) - Root ports are defined as subnodes of the PCIe controller node. Required properties:
Signature · 1 line
1.9.1
RFC 5/5 ARM: tegra: Remove legacy PCIe power supply properties
In reply to Thierry RedingThese properties are deprecated and no longer of any use.
--- arch/arm/boot/dts/tegra20-harmony.dts | 4 ---- arch/arm/boot/dts/tegra20-tamonten.dtsi | 4 ---- arch/arm/boot/dts/tegra20-trimslice.dts | 4 ---- arch/arm/boot/dts/tegra30-beaver.dts | 5 ----- arch/arm/boot/dts/tegra30-cardhu.dtsi | 5 ----- 5 files changed, 22 deletions(-)
arch/arm/boot/dts/tegra20-harmony.dts +0 -4
@@ -569,10 +569,6 @@ avdd-plle-supply = <&pci_vdd_reg>; vddio-pex-clk-supply = <&pci_clk_reg>; - /* deprecated */ - pex-clk-supply = <&pci_clk_reg>; - vdd-supply = <&pci_vdd_reg>; - pci at 1,0 { status = "okay"; };
arch/arm/boot/dts/tegra20-tamonten.dtsi +0 -4
@@ -478,10 +478,6 @@ avdd-pex-pll-supply = <&pci_vdd_reg>; avdd-plle-supply = <&pci_vdd_reg>; vddio-pex-clk-supply = <&pci_clk_reg>; - - /* deprecated */ - pex-clk-supply = <&pci_clk_reg>; - vdd-supply = <&pci_vdd_reg>; }; usb at c5008000 {
arch/arm/boot/dts/tegra20-trimslice.dts +0 -4
@@ -325,10 +325,6 @@ avdd-plle-supply = <&pci_vdd_reg>; vddio-pex-clk-supply = <&pci_clk_reg>; - /* deprecated */ - pex-clk-supply = <&pci_clk_reg>; - vdd-supply = <&pci_vdd_reg>; - pci at 1,0 { status = "okay"; };
arch/arm/boot/dts/tegra30-beaver.dts +0 -5
@@ -27,11 +27,6 @@ vddio-pex-ctl-supply = <&sys_3v3_reg>; hvdd-pex-supply = <&sys_3v3_pexs_reg>; - /* deprecated */ - pex-clk-supply = <&sys_3v3_pexs_reg>; - vdd-supply = <&ldo1_reg>; - avdd-supply = <&ldo2_reg>; - pci at 1,0 { status = "okay"; nvidia,num-lanes = <2>;
arch/arm/boot/dts/tegra30-cardhu.dtsi +0 -5
@@ -47,11 +47,6 @@ vddio-pex-ctl-supply = <&sys_3v3_reg>; avdd-plle-supply = <&ldo2_reg>; - /* deprecated */ - pex-clk-supply = <&pex_hvdd_3v3_reg>; - vdd-supply = <&ldo1_reg>; - avdd-supply = <&ldo2_reg>; - pci at 1,0 { nvidia,num-lanes = <4>; };
Signature · 1 line
1.9.1
cover PCI: tegra: Overhaul regulator usage
In reply to Thierry RedingQuoted 12 lines · Thierry Reding
The current device tree binding for the regulator setup on Tegra PCIe is not accurate. While it does work for current use-cases, that's likely by accident rather than design. This series replaces the existing set of power-supply properties with a new set that accurately describes the inputs of the IP block (depending on SoC generation).
As a heads-up, this breaks backwards compatibility with prior versions of the device tree bindings, but I don't see a reason why that should keep us from fixing this properly. Not many people are currently using these bindings and those who are are most likely tracking upstream development closely enough not to be impacted by this.
Quoted 6 lines
I've aimed to keep the series bisectible, which has the downside of interleaving patches to unrelated trees (ARM and PCI). I'm hoping that perhaps we can find a way to merge this as a whole to keep it possible to bisect across the series. Although again, I guess it wouldn't be all that bad if that wasn't the case, given how little PCIe is actually being used.
I'd be happy to put this series into a branch in the Tegra tree, given suitable acks from Bjorn on the PCI changes.
Bjorn Helgaas
maintainercover PCI: tegra: Overhaul regulator usage
Quoted 20 lines · Stephen Warren
Quoted 12 lines · Thierry Reding
The current device tree binding for the regulator setup on Tegra PCIe is not accurate. While it does work for current use-cases, that's likely by accident rather than design. This series replaces the existing set of power-supply properties with a new set that accurately describes the inputs of the IP block (depending on SoC generation).
As a heads-up, this breaks backwards compatibility with prior versions of the device tree bindings, but I don't see a reason why that should keep us from fixing this properly. Not many people are currently using these bindings and those who are are most likely tracking upstream development closely enough not to be impacted by this.
Quoted 6 lines
I've aimed to keep the series bisectible, which has the downside of interleaving patches to unrelated trees (ARM and PCI). I'm hoping that perhaps we can find a way to merge this as a whole to keep it possible to bisect across the series. Although again, I guess it wouldn't be all that bad if that wasn't the case, given how little PCIe is actually being used.
Quoted 2 lines
I'd be happy to put this series into a branch in the Tegra tree, given suitable acks from Bjorn on the PCI changes.
For 3/5 ("PCI: tegra: Implement accurate power supply scheme"),
I do have the "PCI: tegra: Use new OF interrupt mapping when possible" change from Lucas on my pci/host-tegra branch, but it shouldn't conflict with this.
Bjorn