ARM: qcom: Add initial IPQ8064 SoC and AP148 device trees
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Device tree bindings Arm (32-bit) Arm sub-architectures Arm Qualcomm mailing list +2 more subsystems
PATCH 1/1 ARM: qcom: Add initial IPQ8064 SoC and AP148 device trees
Add basic IPQ8064 SoC include device tree and support for basic booting on the AP148 Reference board. Also, keep dtb build list and qcom_dt_match in sorted order.
Signed-off-by Kumar Gala <[email protected]>
--- arch/arm/boot/dts/Makefile | 8 +- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 12 +++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 122 +++++++++++++++++++++++++++++++ arch/arm/mach-qcom/board.c | 4 +- 4 files changed, 142 insertions(+), 4 deletions(-) create mode 100644 arch/arm/boot/dts/qcom-ipq8064-ap148.dts create mode 100644 arch/arm/boot/dts/qcom-ipq8064.dtsi
arch/arm/boot/dts/Makefile +5 -3
@@ -231,9 +231,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ dra7-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb -dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ - qcom-msm8960-cdp.dtb \ - qcom-apq8074-dragonboard.dtb +dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8074-dragonboard.dtb \ + qcom-ipq8064-ap148.dtb \ + qcom-msm8660-surf.dtb \ + qcom-msm8960-cdp.dtb dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ ste-hrefprev60-stuib.dtb \ ste-hrefprev60-tvk.dtb \
arch/arm/boot/dts/qcom-ipq8064-ap148.dts new file +12 -0
@@ -0,0 +1,12 @@ +#include "qcom-ipq8064.dtsi" + +/ { + model = "Qualcomm IPQ8064/DB149"; + compatible = "qcom,ipq8064-db149", "qcom,ipq8064"; + + soc { + serial at 16340000 { + status = "ok"; + }; + }; +};
arch/arm/boot/dts/qcom-ipq8064.dtsi new file +122 -0
122 lines not on this page · raw message
arch/arm/mach-qcom/board.c +3 -1
@@ -15,9 +15,11 @@#include <asm/mach/arch.h> static const char *const qcom_dt_match[]__initconst = { +"qcom,apq8074-dragonboard" , +"qcom,ipq8062" , +"qcom,ipq8064" ,"qcom,msm8660-surf" ,"qcom,msm8960-cdp" , -"qcom,apq8074-dragonboard" ,NULL };
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arch/arm/boot/dts/qcom-ipq8064.dtsi line 3
Quoted 9 lines · Kumar Gala
arch/arm/boot/dts/qcom-ipq8064.dtsi new file +3
-0@@ -0,0 +1,122 @@ +/dts-v1/; + +/include/ "skeleton.dtsi"
#include?
arch/arm/boot/dts/qcom-ipq8064.dtsi line 15
Quoted 12 lines
arch/arm/boot/dts/qcom-ipq8064.dtsi new file +12
-0+ +#include <dt-bindings/clock/qcom,gcc-ipq806x.h> + +/ { + model = "Qualcomm IPQ8064"; + compatible = "qcom,ipq8064"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <1 14 0x304>;
It may be better to leave this out for now as the binding was never accepted. Which reminds me, I need to send a patch to fix up the interrupts we currently have queued for 3.15.
Quoted 15 lines
arch/arm/boot/dts/qcom-ipq8064.dtsi new file +15
-0+ compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + + cpu at 0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu at 1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>;
arch/arm/boot/dts/qcom-ipq8064.dtsi line 40
Quoted 10 lines
arch/arm/boot/dts/qcom-ipq8064.dtsi new file +10
-0+ qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + interrupts = <0 2 0x4>; + }; + };
Can you also throw in the pmu here please?
Quoted 12 lines
arch/arm/boot/dts/qcom-ipq8064.dtsi new file +12
-0+ + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller at 2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02000000 0x1000 >,
arch/arm/boot/dts/qcom-ipq8064.dtsi line 62
Quoted 10 lines
arch/arm/boot/dts/qcom-ipq8064.dtsi new file +10
-0+ < 0x02002000 0x1000 >; + }; + + timer at 200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, + <1 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>,
If PXO is actually 25Mhz this is wrong. How long does 'sleep 10' take?
Quoted 5 lines
arch/arm/boot/dts/qcom-ipq8064.dtsi new file +4
-0+ <32768>; + cpu-offset = <0x80000>; + }; +
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