clk: tegra20: convert to dt-binding defines

PATCH Applied Lucas Stach 2 participants 6 messages Apr 5, 2014 – Apr 7, 2014

Subsystems (6)

Device tree bindings Arm (32-bit) Common clk Tegra architecture support +2 more subsystems

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Lucas Stach

author

2014-04-05 11:50 UTC #0 lore raw

PATCH 1/5 clk: tegra20: convert to dt-binding defines

Allows to make relationship between DT and driver
more explicit and avoids duplication.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/clk/tegra/clk-tegra20.c | 168 +++++++++++++++++++---------------------
 1 file changed, 80 insertions(+), 88 deletions(-)

drivers/clk/tegra/clk-tegra20.c +80 ~~-88~~

index cfb719f..ea39f46 100644
@@ -19,6 +19,7 @@
 #include <common.h>
 #include <init.h>
 #include <io.h>
+#include <dt-bindings/clock/tegra20-car.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/err.h>

@@ -29,23 +30,7 @@
 
 static void __iomem *car_base;
 
-enum tegra20_clks {
-	cpu, ac97 = 3, rtc, timer, uarta, uartb, gpio, sdmmc2, i2s1 = 11, i2c1,
-	ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
-	gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
-	kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
-	dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
-	usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
-	pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
-	iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
-	vfir = 96, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
-	osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
-	pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
-	pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
-	pll_x, audio, pll_ref, twd, clk_max,
-};
-
-static struct clk *clks[clk_max];
+static struct clk *clks[TEGRA20_CLK_CLK_MAX];
 static struct clk_onecell_data clk_data;
 
 static unsigned int get_pll_ref_div(void)

@@ -58,11 +43,11 @@ static unsigned int get_pll_ref_div(void)
 
 static void tegra20_osc_clk_init(void)
 {
-	clks[clk_m] = clk_fixed("clk_m", tegra_get_osc_clock());
-	clks[clk_32k] = clk_fixed("clk_32k", 32768);
+	clks[TEGRA20_CLK_CLK_M] = clk_fixed("clk_m", tegra_get_osc_clock());
+	clks[TEGRA20_CLK_CLK_32K] = clk_fixed("clk_32k", 32768);
 
-	clks[pll_ref] = clk_fixed_factor("pll_ref", "clk_m", 1,
-					 get_pll_ref_div(), 0);
+	clks[TEGRA20_CLK_PLL_REF] = clk_fixed_factor("pll_ref", "clk_m", 1,
+						     get_pll_ref_div(), 0);
 }
 
 /* PLL frequency tables */

@@ -228,50 +213,52 @@ static struct tegra_clk_pll_params pll_u_params = {
 static void tegra20_pll_init(void)
 {
 	/* PLLC */
-	clks[pll_c] = tegra_clk_register_pll("pll_c", "pll_ref", car_base,
-			0, 0, &pll_c_params, TEGRA_PLL_HAS_CPCON,
+	clks[TEGRA20_CLK_PLL_C] = tegra_clk_register_pll("pll_c", "pll_ref",
+			car_base, 0, 0, &pll_c_params, TEGRA_PLL_HAS_CPCON,
 			pll_c_freq_table);
 
-	clks[pll_c_out1] = tegra_clk_register_pll_out("pll_c_out1", "pll_c",
-			car_base + CRC_PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP);
+	clks[TEGRA20_CLK_PLL_C_OUT1] = tegra_clk_register_pll_out("pll_c_out1",
+			"pll_c", car_base + CRC_PLLC_OUT, 0,
+			TEGRA_DIVIDER_ROUND_UP);
 
 	/* PLLP */
-	clks[pll_p] = tegra_clk_register_pll("pll_p", "pll_ref", car_base,
-			0, 216000000, &pll_p_params, TEGRA_PLL_FIXED |
+	clks[TEGRA20_CLK_PLL_P] = tegra_clk_register_pll("pll_p", "pll_ref",
+			car_base, 0, 216000000, &pll_p_params, TEGRA_PLL_FIXED |
 			TEGRA_PLL_HAS_CPCON, pll_p_freq_table);
 
-	clks[pll_p_out1] = tegra_clk_register_pll_out("pll_p_out1", "pll_p",
-			car_base + CRC_PLLP_OUTA, 0,
+	clks[TEGRA20_CLK_PLL_P_OUT1] = tegra_clk_register_pll_out("pll_p_out1",
+			"pll_p", car_base + CRC_PLLP_OUTA, 0,
 			TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
 
-	clks[pll_p_out2] = tegra_clk_register_pll_out("pll_p_out2", "pll_p",
-			car_base + CRC_PLLP_OUTA, 16,
+	clks[TEGRA20_CLK_PLL_P_OUT2] = tegra_clk_register_pll_out("pll_p_out2",
+			"pll_p", car_base + CRC_PLLP_OUTA, 16,
 			TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
 
-	clks[pll_p_out3] = tegra_clk_register_pll_out("pll_p_out3", "pll_p",
-			car_base + CRC_PLLP_OUTB, 0,
+	clks[TEGRA20_CLK_PLL_P_OUT3] = tegra_clk_register_pll_out("pll_p_out3",
+			"pll_p", car_base + CRC_PLLP_OUTB, 0,
 			TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
 
-	clks[pll_p_out4] = tegra_clk_register_pll_out("pll_p_out4", "pll_p",
-			car_base + CRC_PLLP_OUTB, 16,
+	clks[TEGRA20_CLK_PLL_P_OUT4] = tegra_clk_register_pll_out("pll_p_out4",
+			"pll_p", car_base + CRC_PLLP_OUTB, 16,
 			TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
 
 	/* PLLM */
-	clks[pll_m] = tegra_clk_register_pll("pll_m", "pll_ref", car_base,
-			0, 0, &pll_m_params, TEGRA_PLL_HAS_CPCON,
+	clks[TEGRA20_CLK_PLL_M] = tegra_clk_register_pll("pll_m", "pll_ref",
+			car_base, 0, 0, &pll_m_params, TEGRA_PLL_HAS_CPCON,
 			pll_m_freq_table);
 
-	clks[pll_m_out1] = tegra_clk_register_pll_out("pll_m_out1", "pll_m",
-			car_base + CRC_PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP);
+	clks[TEGRA20_CLK_PLL_M_OUT1] = tegra_clk_register_pll_out("pll_m_out1",
+			"pll_m", car_base + CRC_PLLM_OUT, 0,
+			TEGRA_DIVIDER_ROUND_UP);
 
 	/* PLLX */
-	clks[pll_x] = tegra_clk_register_pll("pll_x", "pll_ref", car_base,
-			0, 0, &pll_x_params, TEGRA_PLL_HAS_CPCON,
+	clks[TEGRA20_CLK_PLL_X] = tegra_clk_register_pll("pll_x", "pll_ref",
+			car_base, 0, 0, &pll_x_params, TEGRA_PLL_HAS_CPCON,
 			pll_x_freq_table);
 
 	/* PLLU */
-	clks[pll_u] = tegra_clk_register_pll("pll_u", "pll_ref", car_base,
-			0, 0, &pll_u_params, TEGRA_PLLU |
+	clks[TEGRA20_CLK_PLL_U] = tegra_clk_register_pll("pll_u", "pll_ref",
+			car_base, 0, 0, &pll_u_params, TEGRA_PLLU |
 			TEGRA_PLL_HAS_CPCON, pll_u_freq_table);
 }

@@ -280,55 +267,60 @@ static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
 static void tegra20_periph_init(void)
 {
 	/* peripheral clocks without a divider */
-	clks[uarta] = tegra_clk_register_periph_nodiv("uarta", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_UARTA, uarta, TEGRA_PERIPH_ON_APB);
-	clks[uartb] = tegra_clk_register_periph_nodiv("uartb", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_UARTB, uartb, TEGRA_PERIPH_ON_APB);
-	clks[uartc] = tegra_clk_register_periph_nodiv("uartc", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_UARTC, uartc, TEGRA_PERIPH_ON_APB);
-	clks[uartd] = tegra_clk_register_periph_nodiv("uartd", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_UARTD, uartd, TEGRA_PERIPH_ON_APB);
-	clks[uarte] = tegra_clk_register_periph_nodiv("uarte", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_UARTE, uarte, TEGRA_PERIPH_ON_APB);
+	clks[TEGRA20_CLK_UARTA] = tegra_clk_register_periph_nodiv("uarta",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTA, TEGRA20_CLK_UARTA,
+			TEGRA_PERIPH_ON_APB);
+	clks[TEGRA20_CLK_UARTB] = tegra_clk_register_periph_nodiv("uartb",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTB, 7,
+			TEGRA_PERIPH_ON_APB);
+	clks[TEGRA20_CLK_UARTC] = tegra_clk_register_periph_nodiv("uartc",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTC, TEGRA20_CLK_UARTC,
+			TEGRA_PERIPH_ON_APB);
+	clks[TEGRA20_CLK_UARTD] = tegra_clk_register_periph_nodiv("uartd",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTD, TEGRA20_CLK_UARTD,
+			TEGRA_PERIPH_ON_APB);
+	clks[TEGRA20_CLK_UARTE] = tegra_clk_register_periph_nodiv("uarte",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTE, TEGRA20_CLK_UARTE,
+			TEGRA_PERIPH_ON_APB);
 
 	/* peripheral clocks with a divider */
-	clks[sdmmc1] = tegra_clk_register_periph("sdmmc1", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_SDMMC1, sdmmc1, 1);
-	clks[sdmmc2] = tegra_clk_register_periph("sdmmc2", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_SDMMC2, sdmmc2, 1);
-	clks[sdmmc3] = tegra_clk_register_periph("sdmmc3", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_SDMMC3, sdmmc3, 1);
-	clks[sdmmc4] = tegra_clk_register_periph("sdmmc4", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_SDMMC4, sdmmc4, 1);
+	clks[TEGRA20_CLK_SDMMC1] = tegra_clk_register_periph("sdmmc1",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_SDMMC1, TEGRA20_CLK_SDMMC1, 1);
+	clks[TEGRA20_CLK_SDMMC2] = tegra_clk_register_periph("sdmmc2",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_SDMMC2, TEGRA20_CLK_SDMMC2, 1);
+	clks[TEGRA20_CLK_SDMMC3] = tegra_clk_register_periph("sdmmc3",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_SDMMC3, TEGRA20_CLK_SDMMC3, 1);
+	clks[TEGRA20_CLK_SDMMC4] = tegra_clk_register_periph("sdmmc4",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_SDMMC4, TEGRA20_CLK_SDMMC4, 1);
 }
 
 static struct tegra_clk_init_table init_table[] = {
-	{pll_p,		clk_max,	216000000,	1},
-	{pll_p_out1,	clk_max,	28800000,	1},
-	{pll_p_out2,	clk_max,	48000000,	1},
-	{pll_p_out3,	clk_max,	72000000,	1},
-	{pll_p_out4,	clk_max,	24000000,	1},
-	{pll_c,		clk_max,	600000000,	1},
-	{pll_c_out1,	clk_max,	120000000,	1},
-	{uarta,		pll_p,		0,		1},
-	{uartb,		pll_p,		0,		1},
-	{uartc,		pll_p,		0,		1},
-	{uartd,		pll_p,		0,		1},
-	{uarte,		pll_p,		0,		1},
-	{sdmmc1,	pll_p,		48000000,	0},
-	{sdmmc2,	pll_p,		48000000,	0},
-	{sdmmc3,	pll_p,		48000000,	0},
-	{sdmmc4,	pll_p,		48000000,	0},
-	{clk_max,	clk_max,	0,		0}, /* sentinel */
+	{TEGRA20_CLK_PLL_P,		TEGRA20_CLK_CLK_MAX,	216000000,	1},
+	{TEGRA20_CLK_PLL_P_OUT1,	TEGRA20_CLK_CLK_MAX,	28800000,	1},
+	{TEGRA20_CLK_PLL_P_OUT2,	TEGRA20_CLK_CLK_MAX,	48000000,	1},
+	{TEGRA20_CLK_PLL_P_OUT3,	TEGRA20_CLK_CLK_MAX,	72000000,	1},
+	{TEGRA20_CLK_PLL_P_OUT4,	TEGRA20_CLK_CLK_MAX,	24000000,	1},
+	{TEGRA20_CLK_PLL_C,		TEGRA20_CLK_CLK_MAX,	600000000,	1},
+	{TEGRA20_CLK_PLL_C_OUT1,	TEGRA20_CLK_CLK_MAX,	120000000,	1},
+	{TEGRA20_CLK_UARTA,		TEGRA20_CLK_PLL_P,	0,		1},
+	{TEGRA20_CLK_UARTB,		TEGRA20_CLK_PLL_P,	0,		1},
+	{TEGRA20_CLK_UARTC,		TEGRA20_CLK_PLL_P,	0,		1},
+	{TEGRA20_CLK_UARTD,		TEGRA20_CLK_PLL_P,	0,		1},
+	{TEGRA20_CLK_UARTE,		TEGRA20_CLK_PLL_P,	0,		1},
+	{TEGRA20_CLK_SDMMC1,		TEGRA20_CLK_PLL_P,	48000000,	0},
+	{TEGRA20_CLK_SDMMC2,		TEGRA20_CLK_PLL_P,	48000000,	0},
+	{TEGRA20_CLK_SDMMC3,		TEGRA20_CLK_PLL_P,	48000000,	0},
+	{TEGRA20_CLK_SDMMC4,		TEGRA20_CLK_PLL_P,	48000000,	0},
+	{TEGRA20_CLK_CLK_MAX,		TEGRA20_CLK_CLK_MAX,	0,	0}, /* sentinel */
 };
 
 static int tegra20_car_probe(struct device_d *dev)

@@ -341,7 +333,7 @@ static int tegra20_car_probe(struct device_d *dev)
 	tegra20_pll_init();
 	tegra20_periph_init();
 
-	tegra_init_from_table(init_table, clks, clk_max);
+	tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
 
 	/* speed up system bus */
 	writel(CRC_SCLK_BURST_POLICY_SYS_STATE_RUN <<

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Lucas Stach

author

2014-04-05 11:50 UTC #1 lore raw

PATCH 2/5 dt-bindings: add pinctrl-tegra.h

Signed-off-by Lucas Stach <[email protected]>

---
 include/dt-bindings/pinctrl/pinctrl-tegra.h | 45 +++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h

include/dt-bindings/pinctrl/pinctrl-tegra.h new file +45 -0

new file mode 100644
index 0000000..ebafa49
@@ -0,0 +1,45 @@
+/*
+ * This header provides constants for Tegra pinctrl bindings.
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author: Laxman Dewangan <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
+#define _DT_BINDINGS_PINCTRL_TEGRA_H
+
+/*
+ * Enable/disable for diffeent dt properties. This is applicable for
+ * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
+ * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
+ */
+#define TEGRA_PIN_DISABLE				0
+#define TEGRA_PIN_ENABLE				1
+
+#define TEGRA_PIN_PULL_NONE				0
+#define TEGRA_PIN_PULL_DOWN				1
+#define TEGRA_PIN_PULL_UP				2
+
+/* Low power mode driver */
+#define TEGRA_PIN_LP_DRIVE_DIV_8			0
+#define TEGRA_PIN_LP_DRIVE_DIV_4			1
+#define TEGRA_PIN_LP_DRIVE_DIV_2			2
+#define TEGRA_PIN_LP_DRIVE_DIV_1			3
+
+/* Rising/Falling slew rate */
+#define TEGRA_PIN_SLEW_RATE_FASTEST			0
+#define TEGRA_PIN_SLEW_RATE_FAST			1
+#define TEGRA_PIN_SLEW_RATE_SLOW			2
+#define TEGRA_PIN_SLEW_RATE_SLOWEST			3
+
+#endif

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Lucas Stach

author

2014-04-05 11:50 UTC #2 lore raw

PATCH 3/5 ARM: dts: update Tegra20 base dtsi to Linux 3.14

In reply to Lucas Stach

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/dts/tegra20.dtsi | 195 +++++++++++++++++++++++++++++++++++-----------
 1 file changed, 151 insertions(+), 44 deletions(-)

arch/arm/dts/tegra20.dtsi +151 ~~-44~~

index df40b54..48d2a7f 100644
@@ -1,5 +1,6 @@
 #include <dt-bindings/clock/tegra20-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"

@@ -16,57 +17,71 @@
 		serial4 = &uarte;
 	};
 
-	host1x {
+	host1x@50000000 {
 		compatible = "nvidia,tegra20-host1x", "simple-bus";
 		reg = <0x50000000 0x00024000>;
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+		resets = <&tegra_car 28>;
+		reset-names = "host1x";
 
 		#address-cells = <1>;
 		#size-cells = <1>;
 
 		ranges = <0x54000000 0x54000000 0x04000000>;
 
-		mpe {
+		mpe@54040000 {
 			compatible = "nvidia,tegra20-mpe";
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_MPE>;
+			resets = <&tegra_car 60>;
+			reset-names = "mpe";
 		};
 
-		vi {
+		vi@54080000 {
 			compatible = "nvidia,tegra20-vi";
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_VI>;
+			resets = <&tegra_car 20>;
+			reset-names = "vi";
 		};
 
-		epp {
+		epp@540c0000 {
 			compatible = "nvidia,tegra20-epp";
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_EPP>;
+			resets = <&tegra_car 19>;
+			reset-names = "epp";
 		};
 
-		isp {
+		isp@54100000 {
 			compatible = "nvidia,tegra20-isp";
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_ISP>;
+			resets = <&tegra_car 23>;
+			reset-names = "isp";
 		};
 
-		gr2d {
+		gr2d@54140000 {
 			compatible = "nvidia,tegra20-gr2d";
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+			resets = <&tegra_car 21>;
+			reset-names = "2d";
 		};
 
-		gr3d {
+		gr3d@54140000 {
 			compatible = "nvidia,tegra20-gr3d";
-			reg = <0x54180000 0x00040000>;
+			reg = <0x54140000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+			resets = <&tegra_car 24>;
+			reset-names = "3d";
 		};
 
 		dc@54200000 {

@@ -75,7 +90,11 @@
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
-			clock-names = "disp1", "parent";
+			clock-names = "dc", "parent";
+			resets = <&tegra_car 27>;
+			reset-names = "dc";
+
+			nvidia,head = <0>;
 
 			rgb {
 				status = "disabled";

@@ -88,24 +107,30 @@
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 				 <&tegra_car TEGRA20_CLK_PLL_P>;
-			clock-names = "disp2", "parent";
+			clock-names = "dc", "parent";
+			resets = <&tegra_car 26>;
+			reset-names = "dc";
+
+			nvidia,head = <1>;
 
 			rgb {
 				status = "disabled";
 			};
 		};
 
-		hdmi {
+		hdmi@54280000 {
 			compatible = "nvidia,tegra20-hdmi";
 			reg = <0x54280000 0x00040000>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 			clock-names = "hdmi", "parent";
+			resets = <&tegra_car 51>;
+			reset-names = "hdmi";
 			status = "disabled";
 		};
 
-		tvo {
+		tvo@542c0000 {
 			compatible = "nvidia,tegra20-tvo";
 			reg = <0x542c0000 0x00040000>;
 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;

@@ -113,10 +138,12 @@
 			status = "disabled";
 		};
 
-		dsi {
+		dsi@542c0000 {
 			compatible = "nvidia,tegra20-dsi";
-			reg = <0x54300000 0x00040000>;
+			reg = <0x542c0000 0x00040000>;
 			clocks = <&tegra_car TEGRA20_CLK_DSI>;
+			resets = <&tegra_car 48>;
+			reset-names = "dsi";
 			status = "disabled";
 		};
 	};

@@ -129,7 +156,7 @@
 		clocks = <&tegra_car TEGRA20_CLK_TWD>;
 	};
 
-	intc: interrupt-controller {
+	intc: interrupt-controller@50041000 {
 		compatible = "arm,cortex-a9-gic";
 		reg = <0x50041000 0x1000
 		       0x50040100 0x0100>;

@@ -137,7 +164,7 @@
 		#interrupt-cells = <3>;
 	};
 
-	cache-controller {
+	cache-controller@50043000 {
 		compatible = "arm,pl310-cache";
 		reg = <0x50043000 0x1000>;
 		arm,data-latency = <5 5 2>;

@@ -156,13 +183,14 @@
 		clocks = <&tegra_car TEGRA20_CLK_TIMER>;
 	};
 
-	tegra_car: clock {
+	tegra_car: clock@60006000 {
 		compatible = "nvidia,tegra20-car";
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
-	apbdma: dma {
+	apbdma: dma@6000a000 {
 		compatible = "nvidia,tegra20-apbdma";
 		reg = <0x6000a000 0x1200>;
 		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

@@ -182,14 +210,17 @@
 			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
+		resets = <&tegra_car 34>;
+		reset-names = "dma";
+		#dma-cells = <1>;
 	};
 
-	ahb {
+	ahb@6000c004 {
 		compatible = "nvidia,tegra20-ahb";
 		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
 	};
 
-	gpio: gpio {
+	gpio: gpio@6000d000 {
 		compatible = "nvidia,tegra20-gpio";
 		reg = <0x6000d000 0x1000>;
 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

@@ -205,7 +236,7 @@
 		interrupt-controller;
 	};
 
-	pinmux: pinmux {
+	pinmux: pinmux@70000014 {
 		compatible = "nvidia,tegra20-pinmux";
 		reg = <0x70000014 0x10   /* Tri-state registers */
 		       0x70000080 0x20   /* Mux registers */

@@ -213,17 +244,20 @@
 		       0x70000868 0xa8>; /* Pad control registers */
 	};
 
-	das {
+	das@70000c00 {
 		compatible = "nvidia,tegra20-das";
 		reg = <0x70000c00 0x80>;
 	};
 
-	tegra_ac97: ac97 {
+	tegra_ac97: ac97@70002000 {
 		compatible = "nvidia,tegra20-ac97";
 		reg = <0x70002000 0x200>;
 		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 12>;
 		clocks = <&tegra_car TEGRA20_CLK_AC97>;
+		resets = <&tegra_car 3>;
+		reset-names = "ac97";
+		dmas = <&apbdma 12>, <&apbdma 12>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -231,8 +265,11 @@
 		compatible = "nvidia,tegra20-i2s";
 		reg = <0x70002800 0x200>;
 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 2>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S1>;
+		resets = <&tegra_car 11>;
+		reset-names = "i2s";
+		dmas = <&apbdma 2>, <&apbdma 2>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -240,8 +277,11 @@
 		compatible = "nvidia,tegra20-i2s";
 		reg = <0x70002a00 0x200>;
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 1>;
 		clocks = <&tegra_car TEGRA20_CLK_I2S2>;
+		resets = <&tegra_car 18>;
+		reset-names = "i2s";
+		dmas = <&apbdma 1>, <&apbdma 1>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -257,8 +297,11 @@
 		reg = <0x70006000 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTA>;
+		resets = <&tegra_car 6>;
+		reset-names = "serial";
+		dmas = <&apbdma 8>, <&apbdma 8>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -267,8 +310,11 @@
 		reg = <0x70006040 0x40>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTB>;
+		resets = <&tegra_car 7>;
+		reset-names = "serial";
+		dmas = <&apbdma 9>, <&apbdma 9>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -277,8 +323,11 @@
 		reg = <0x70006200 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTC>;
+		resets = <&tegra_car 55>;
+		reset-names = "serial";
+		dmas = <&apbdma 10>, <&apbdma 10>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -287,8 +336,11 @@
 		reg = <0x70006300 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTD>;
+		resets = <&tegra_car 65>;
+		reset-names = "serial";
+		dmas = <&apbdma 19>, <&apbdma 19>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -297,20 +349,25 @@
 		reg = <0x70006400 0x100>;
 		reg-shift = <2>;
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA20_CLK_UARTE>;
+		resets = <&tegra_car 66>;
+		reset-names = "serial";
+		dmas = <&apbdma 20>, <&apbdma 20>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
-	pwm: pwm {
+	pwm: pwm@7000a000 {
 		compatible = "nvidia,tegra20-pwm";
 		reg = <0x7000a000 0x100>;
 		#pwm-cells = <2>;
 		clocks = <&tegra_car TEGRA20_CLK_PWM>;
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
 		status = "disabled";
 	};
 
-	rtc {
+	rtc@7000e000 {
 		compatible = "nvidia,tegra20-rtc";
 		reg = <0x7000e000 0x100>;
 		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

@@ -326,6 +383,10 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
+		dmas = <&apbdma 21>, <&apbdma 21>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -333,10 +394,13 @@
 		compatible = "nvidia,tegra20-sflash";
 		reg = <0x7000c380 0x80>;
 		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 11>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SPI>;
+		resets = <&tegra_car 43>;
+		reset-names = "spi";
+		dmas = <&apbdma 11>, <&apbdma 11>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -349,6 +413,10 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 54>;
+		reset-names = "i2c";
+		dmas = <&apbdma 22>, <&apbdma 22>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -361,6 +429,10 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
+		dmas = <&apbdma 23>, <&apbdma 23>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -373,6 +445,10 @@
 		clocks = <&tegra_car TEGRA20_CLK_DVC>,
 			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 47>;
+		reset-names = "i2c";
+		dmas = <&apbdma 24>, <&apbdma 24>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -380,10 +456,13 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d400 0x200>;
 		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 15>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC1>;
+		resets = <&tegra_car 41>;
+		reset-names = "spi";
+		dmas = <&apbdma 15>, <&apbdma 15>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -391,10 +470,13 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d600 0x200>;
 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC2>;
+		resets = <&tegra_car 44>;
+		reset-names = "spi";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -402,10 +484,13 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000d800 0x200>;
 		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 17>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC3>;
+		resets = <&tegra_car 46>;
+		reset-names = "spi";
+		dmas = <&apbdma 17>, <&apbdma 17>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};

@@ -413,22 +498,27 @@
 		compatible = "nvidia,tegra20-slink";
 		reg = <0x7000da00 0x200>;
 		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-		nvidia,dma-request-selector = <&apbdma 18>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&tegra_car TEGRA20_CLK_SBC4>;
+		resets = <&tegra_car 68>;
+		reset-names = "spi";
+		dmas = <&apbdma 18>, <&apbdma 18>;
+		dma-names = "rx", "tx";
 		status = "disabled";
 	};
 
-	kbc {
+	kbc@7000e200 {
 		compatible = "nvidia,tegra20-kbc";
 		reg = <0x7000e200 0x100>;
 		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_KBC>;
+		resets = <&tegra_car 36>;
+		reset-names = "kbc";
 		status = "disabled";
 	};
 
-	pmc {
+	pmc@7000e400 {
 		compatible = "nvidia,tegra20-pmc";
 		reg = <0x7000e400 0x400>;
 		clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;

@@ -442,7 +532,7 @@
 		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
-	iommu {
+	iommu@7000f024 {
 		compatible = "nvidia,tegra20-gart";
 		reg = <0x7000f024 0x00000018	/* controller registers */
 		       0x58000000 0x02000000>;	/* GART aperture */

@@ -455,7 +545,7 @@
 		#size-cells = <0>;
 	};
 
-	pcie-controller {
+	pcie-controller@80003000 {
 		compatible = "nvidia,tegra20-pcie";
 		device_type = "pci";
 		reg = <0x80003000 0x00000800   /* PADS registers */

@@ -478,9 +568,12 @@
 
 		clocks = <&tegra_car TEGRA20_CLK_PEX>,
 			 <&tegra_car TEGRA20_CLK_AFI>,
-			 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
 			 <&tegra_car TEGRA20_CLK_PLL_E>;
-		clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+		clock-names = "pex", "afi", "pll_e";
+		resets = <&tegra_car 70>,
+		         <&tegra_car 72>,
+		         <&tegra_car 74>;
+		reset-names = "pex", "afi", "pcie_x";
 		status = "disabled";
 
 		pci@1,0 {

@@ -517,6 +610,8 @@
 		phy_type = "utmi";
 		nvidia,has-legacy-mode;
 		clocks = <&tegra_car TEGRA20_CLK_USBD>;
+		resets = <&tegra_car 22>;
+		reset-names = "usb";
 		nvidia,needs-double-reset;
 		nvidia,phy = <&phy1>;
 		status = "disabled";

@@ -548,6 +643,8 @@
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "ulpi";
 		clocks = <&tegra_car TEGRA20_CLK_USB2>;
+		resets = <&tegra_car 58>;
+		reset-names = "usb";
 		nvidia,phy = <&phy2>;
 		status = "disabled";
 	};

@@ -569,6 +666,8 @@
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		phy_type = "utmi";
 		clocks = <&tegra_car TEGRA20_CLK_USB3>;
+		resets = <&tegra_car 59>;
+		reset-names = "usb";
 		nvidia,phy = <&phy3>;
 		status = "disabled";
 	};

@@ -597,6 +696,8 @@
 		reg = <0xc8000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+		resets = <&tegra_car 14>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};

@@ -605,6 +706,8 @@
 		reg = <0xc8000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
+		resets = <&tegra_car 9>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};

@@ -613,6 +716,8 @@
 		reg = <0xc8000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
+		resets = <&tegra_car 69>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};

@@ -621,6 +726,8 @@
 		reg = <0xc8000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
+		resets = <&tegra_car 15>;
+		reset-names = "sdhci";
 		status = "disabled";
 	};

Signature · 7 lines

1.9.0


_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox

Lucas Stach

author

2014-04-05 11:50 UTC #3 lore raw

PATCH 4/5 ARM: dts: update paz00 DT to Linux 3.14

In reply to Lucas Stach

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/dts/tegra20-paz00.dts | 56 +++++++++++++++++++++++++-----------------
 1 file changed, 34 insertions(+), 22 deletions(-)

arch/arm/dts/tegra20-paz00.dts +34 ~~-22~~

index d82d406..c7cd8e6 100644
@@ -1,13 +1,23 @@
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
 
 / {
 	model = "Toshiba AC100 / Dynabook AZ";
 	compatible = "compal,paz00", "nvidia,tegra20";
 
-	host1x {
-		hdmi {
+	aliases {
+		rtc0 = "/i2c@7000d000/tps6586x@34";
+		rtc1 = "/rtc@7000e000";
+	};
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	host1x@50000000 {
+		hdmi@54280000 {
 			status = "okay";
 
 			vdd-supply = <&hdmi_vdd_reg>;

@@ -19,7 +29,7 @@
 		};
 	};
 
-	pinmux {
+	pinmux@70000014 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&state_default>;

@@ -173,39 +183,39 @@
 					"gpu", "gpu7", "gpv", "i2cp", "pta",
 					"rm", "sdio1", "slxk", "spdo", "uac",
 					"uda";
-				nvidia,pull = <0>;
-				nvidia,tristate = <0>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 			};
 			conf_ck32 {
 				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
 					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-				nvidia,pull = <0>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 			};
 			conf_crtp {
 				nvidia,pins = "crtp", "dap3", "dap4", "dtb",
 					"dtc", "dte", "slxa", "slxc", "slxd",
 					"spdi";
-				nvidia,pull = <0>;
-				nvidia,tristate = <1>;
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 			};
 			conf_csus {
 				nvidia,pins = "csus", "spia", "spib", "spid",
 					"spif";
-				nvidia,pull = <1>;
-				nvidia,tristate = <1>;
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 			};
 			conf_ddc {
 				nvidia,pins = "ddc", "irrx", "irtx", "kbca",
 					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
 					"spic", "spig", "uaa", "uab";
-				nvidia,pull = <2>;
-				nvidia,tristate = <0>;
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 			};
 			conf_dta {
 				nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
 					"spie", "spih", "uad", "uca", "ucb";
-				nvidia,pull = <2>;
-				nvidia,tristate = <1>;
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 			};
 			conf_hdint {
 				nvidia,pins = "hdint", "ld0", "ld1", "ld2",

@@ -214,23 +224,23 @@
 					"ld13", "ld14", "ld15", "ld16", "ld17",
 					"ldc", "ldi", "lhs", "lsc0", "lspi",
 					"lvs", "pmc";
-				nvidia,tristate = <0>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 			};
 			conf_lc {
 				nvidia,pins = "lc", "ls";
-				nvidia,pull = <2>;
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 			};
 			conf_lcsn {
 				nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
 					"lm0", "lm1", "lpp", "lpw0", "lpw1",
 					"lpw2", "lsc1", "lsck", "lsda", "lsdi",
 					"lvp0", "lvp1", "sdb";
-				nvidia,tristate = <1>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 			};
 			conf_ld17_0 {
 				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
 					"ld23_22";
-				nvidia,pull = <1>;
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 			};
 		};
 	};

@@ -264,7 +274,7 @@
 		clock-frequency = <100000>;
 	};
 
-	nvec {
+	nvec@7000c500 {
 		compatible = "nvidia,nvec";
 		reg = <0x7000c500 0x100>;
 		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;

@@ -276,6 +286,8 @@
 		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 		       	 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
 	};
 
 	i2c@7000d000 {

@@ -411,7 +423,7 @@
 		};
 	};
 
-	pmc {
+	pmc@7000e400 {
 		nvidia,invert-interrupt;
 		nvidia,suspend-mode = <1>;
 		nvidia,cpu-pwr-good-time = <2000>;

@@ -468,7 +480,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		clk32k_in: clock {
+		clk32k_in: clock@0 {
 			compatible = "fixed-clock";
 			reg=<0>;
 			#clock-cells = <0>;

@@ -482,7 +494,7 @@
 		power {
 			label = "Power";
 			gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
-			linux,code = <116>; /* KEY_POWER */
+			linux,code = <KEY_POWER>;
 			gpio-key,wakeup;
 		};
 	};

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Lucas Stach

author

2014-04-05 11:50 UTC #4 lore raw

PATCH 5/5 ARM: dts: update colibri + iris DTs to Linux 3.14

In reply to Lucas Stach

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/dts/tegra20-colibri-iris.dts |  30 ++---
 arch/arm/dts/tegra20-colibri.dtsi     | 213 ++++++++++++++++++----------------
 2 files changed, 126 insertions(+), 117 deletions(-)

arch/arm/dts/tegra20-colibri-iris.dts +15 ~~-15~~

index 31b0f59..adfa917 100644
@@ -6,61 +6,61 @@
 	model = "Toradex Colibri T20 on Iris";
 	compatible = "toradex,iris", "toradex,colibri_t20", "nvidia,tegra20";
 
-	host1x {
-		hdmi {
+	host1x@50000000 {
+		hdmi@54280000 {
 			status = "okay";
 		};
 	};
 
-	pinmux {
+	pinmux@70000014 {
 		state_default: pinmux {
 			hdint {
-				nvidia,tristate = <0>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 			};
 
 			i2cddc {
-				nvidia,tristate = <0>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 			};
 
 			sdio4 {
-				nvidia,tristate = <0>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 			};
 
 			uarta {
-				nvidia,tristate = <0>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 			};
 
 			uartd {
-				nvidia,tristate = <0>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 			};
 		};
 	};
 
-	usb@c5000000 {
+	serial@70006000 {
 		status = "okay";
 	};
 
-	usb-phy@c5000000 {
+	serial@70006300 {
 		status = "okay";
 	};
 
-	usb@c5008000 {
+	i2c_ddc: i2c@7000c400 {
 		status = "okay";
 	};
 
-	usb-phy@c5008000 {
+	usb@c5000000 {
 		status = "okay";
 	};
 
-	serial@70006000 {
+	usb-phy@c5000000 {
 		status = "okay";
 	};
 
-	serial@70006300 {
+	usb@c5008000 {
 		status = "okay";
 	};
 
-	i2c_ddc: i2c@7000c400 {
+	usb-phy@c5008000 {
 		status = "okay";
 	};

arch/arm/dts/tegra20-colibri.dtsi +111 ~~-102~~

417 lines not on this page · raw message

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Sascha Hauer

Applied

2014-04-07 06:36 UTC #5 lore raw

In reply to Lucas Stach

Quoted 4 lines · Lucas Stach

Allows to make relationship between DT and driver
more explicit and avoids duplication.
Signed-off-by Lucas Stach <[email protected]>

Applied, thanks

Sascha

Quoted 255 lines

---
 drivers/clk/tegra/clk-tegra20.c | 168 +++++++++++++++++++---------------------
 1 file changed, 80 insertions(+), 88 deletions(-)

drivers/clk/tegra/clk-tegra20.c +80 ~~-88~~

index cfb719f..ea39f46 100644
@@ -19,6 +19,7 @@
 #include <common.h>
 #include <init.h>
 #include <io.h>
+#include <dt-bindings/clock/tegra20-car.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/err.h>

@@ -29,23 +30,7 @@
 
 static void __iomem *car_base;
 
-enum tegra20_clks {
-	cpu, ac97 = 3, rtc, timer, uarta, uartb, gpio, sdmmc2, i2s1 = 11, i2c1,
-	ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
-	gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
-	kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
-	dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
-	usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
-	pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
-	iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
-	vfir = 96, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
-	osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
-	pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
-	pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
-	pll_x, audio, pll_ref, twd, clk_max,
-};
-
-static struct clk *clks[clk_max];
+static struct clk *clks[TEGRA20_CLK_CLK_MAX];
 static struct clk_onecell_data clk_data;
 
 static unsigned int get_pll_ref_div(void)

@@ -58,11 +43,11 @@ static unsigned int get_pll_ref_div(void)
 
 static void tegra20_osc_clk_init(void)
 {
-	clks[clk_m] = clk_fixed("clk_m", tegra_get_osc_clock());
-	clks[clk_32k] = clk_fixed("clk_32k", 32768);
+	clks[TEGRA20_CLK_CLK_M] = clk_fixed("clk_m", tegra_get_osc_clock());
+	clks[TEGRA20_CLK_CLK_32K] = clk_fixed("clk_32k", 32768);
 
-	clks[pll_ref] = clk_fixed_factor("pll_ref", "clk_m", 1,
-					 get_pll_ref_div(), 0);
+	clks[TEGRA20_CLK_PLL_REF] = clk_fixed_factor("pll_ref", "clk_m", 1,
+						     get_pll_ref_div(), 0);
 }
 
 /* PLL frequency tables */

@@ -228,50 +213,52 @@ static struct tegra_clk_pll_params pll_u_params = {
 static void tegra20_pll_init(void)
 {
 	/* PLLC */
-	clks[pll_c] = tegra_clk_register_pll("pll_c", "pll_ref", car_base,
-			0, 0, &pll_c_params, TEGRA_PLL_HAS_CPCON,
+	clks[TEGRA20_CLK_PLL_C] = tegra_clk_register_pll("pll_c", "pll_ref",
+			car_base, 0, 0, &pll_c_params, TEGRA_PLL_HAS_CPCON,
 			pll_c_freq_table);
 
-	clks[pll_c_out1] = tegra_clk_register_pll_out("pll_c_out1", "pll_c",
-			car_base + CRC_PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP);
+	clks[TEGRA20_CLK_PLL_C_OUT1] = tegra_clk_register_pll_out("pll_c_out1",
+			"pll_c", car_base + CRC_PLLC_OUT, 0,
+			TEGRA_DIVIDER_ROUND_UP);
 
 	/* PLLP */
-	clks[pll_p] = tegra_clk_register_pll("pll_p", "pll_ref", car_base,
-			0, 216000000, &pll_p_params, TEGRA_PLL_FIXED |
+	clks[TEGRA20_CLK_PLL_P] = tegra_clk_register_pll("pll_p", "pll_ref",
+			car_base, 0, 216000000, &pll_p_params, TEGRA_PLL_FIXED |
 			TEGRA_PLL_HAS_CPCON, pll_p_freq_table);
 
-	clks[pll_p_out1] = tegra_clk_register_pll_out("pll_p_out1", "pll_p",
-			car_base + CRC_PLLP_OUTA, 0,
+	clks[TEGRA20_CLK_PLL_P_OUT1] = tegra_clk_register_pll_out("pll_p_out1",
+			"pll_p", car_base + CRC_PLLP_OUTA, 0,
 			TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
 
-	clks[pll_p_out2] = tegra_clk_register_pll_out("pll_p_out2", "pll_p",
-			car_base + CRC_PLLP_OUTA, 16,
+	clks[TEGRA20_CLK_PLL_P_OUT2] = tegra_clk_register_pll_out("pll_p_out2",
+			"pll_p", car_base + CRC_PLLP_OUTA, 16,
 			TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
 
-	clks[pll_p_out3] = tegra_clk_register_pll_out("pll_p_out3", "pll_p",
-			car_base + CRC_PLLP_OUTB, 0,
+	clks[TEGRA20_CLK_PLL_P_OUT3] = tegra_clk_register_pll_out("pll_p_out3",
+			"pll_p", car_base + CRC_PLLP_OUTB, 0,
 			TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
 
-	clks[pll_p_out4] = tegra_clk_register_pll_out("pll_p_out4", "pll_p",
-			car_base + CRC_PLLP_OUTB, 16,
+	clks[TEGRA20_CLK_PLL_P_OUT4] = tegra_clk_register_pll_out("pll_p_out4",
+			"pll_p", car_base + CRC_PLLP_OUTB, 16,
 			TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
 
 	/* PLLM */
-	clks[pll_m] = tegra_clk_register_pll("pll_m", "pll_ref", car_base,
-			0, 0, &pll_m_params, TEGRA_PLL_HAS_CPCON,
+	clks[TEGRA20_CLK_PLL_M] = tegra_clk_register_pll("pll_m", "pll_ref",
+			car_base, 0, 0, &pll_m_params, TEGRA_PLL_HAS_CPCON,
 			pll_m_freq_table);
 
-	clks[pll_m_out1] = tegra_clk_register_pll_out("pll_m_out1", "pll_m",
-			car_base + CRC_PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP);
+	clks[TEGRA20_CLK_PLL_M_OUT1] = tegra_clk_register_pll_out("pll_m_out1",
+			"pll_m", car_base + CRC_PLLM_OUT, 0,
+			TEGRA_DIVIDER_ROUND_UP);
 
 	/* PLLX */
-	clks[pll_x] = tegra_clk_register_pll("pll_x", "pll_ref", car_base,
-			0, 0, &pll_x_params, TEGRA_PLL_HAS_CPCON,
+	clks[TEGRA20_CLK_PLL_X] = tegra_clk_register_pll("pll_x", "pll_ref",
+			car_base, 0, 0, &pll_x_params, TEGRA_PLL_HAS_CPCON,
 			pll_x_freq_table);
 
 	/* PLLU */
-	clks[pll_u] = tegra_clk_register_pll("pll_u", "pll_ref", car_base,
-			0, 0, &pll_u_params, TEGRA_PLLU |
+	clks[TEGRA20_CLK_PLL_U] = tegra_clk_register_pll("pll_u", "pll_ref",
+			car_base, 0, 0, &pll_u_params, TEGRA_PLLU |
 			TEGRA_PLL_HAS_CPCON, pll_u_freq_table);
 }

@@ -280,55 +267,60 @@ static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
 static void tegra20_periph_init(void)
 {
 	/* peripheral clocks without a divider */
-	clks[uarta] = tegra_clk_register_periph_nodiv("uarta", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_UARTA, uarta, TEGRA_PERIPH_ON_APB);
-	clks[uartb] = tegra_clk_register_periph_nodiv("uartb", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_UARTB, uartb, TEGRA_PERIPH_ON_APB);
-	clks[uartc] = tegra_clk_register_periph_nodiv("uartc", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_UARTC, uartc, TEGRA_PERIPH_ON_APB);
-	clks[uartd] = tegra_clk_register_periph_nodiv("uartd", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_UARTD, uartd, TEGRA_PERIPH_ON_APB);
-	clks[uarte] = tegra_clk_register_periph_nodiv("uarte", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_UARTE, uarte, TEGRA_PERIPH_ON_APB);
+	clks[TEGRA20_CLK_UARTA] = tegra_clk_register_periph_nodiv("uarta",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTA, TEGRA20_CLK_UARTA,
+			TEGRA_PERIPH_ON_APB);
+	clks[TEGRA20_CLK_UARTB] = tegra_clk_register_periph_nodiv("uartb",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTB, 7,
+			TEGRA_PERIPH_ON_APB);
+	clks[TEGRA20_CLK_UARTC] = tegra_clk_register_periph_nodiv("uartc",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTC, TEGRA20_CLK_UARTC,
+			TEGRA_PERIPH_ON_APB);
+	clks[TEGRA20_CLK_UARTD] = tegra_clk_register_periph_nodiv("uartd",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTD, TEGRA20_CLK_UARTD,
+			TEGRA_PERIPH_ON_APB);
+	clks[TEGRA20_CLK_UARTE] = tegra_clk_register_periph_nodiv("uarte",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_UARTE, TEGRA20_CLK_UARTE,
+			TEGRA_PERIPH_ON_APB);
 
 	/* peripheral clocks with a divider */
-	clks[sdmmc1] = tegra_clk_register_periph("sdmmc1", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_SDMMC1, sdmmc1, 1);
-	clks[sdmmc2] = tegra_clk_register_periph("sdmmc2", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_SDMMC2, sdmmc2, 1);
-	clks[sdmmc3] = tegra_clk_register_periph("sdmmc3", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_SDMMC3, sdmmc3, 1);
-	clks[sdmmc4] = tegra_clk_register_periph("sdmmc4", mux_pllpcm_clkm,
-			ARRAY_SIZE(mux_pllpcm_clkm), car_base,
-			CRC_CLK_SOURCE_SDMMC4, sdmmc4, 1);
+	clks[TEGRA20_CLK_SDMMC1] = tegra_clk_register_periph("sdmmc1",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_SDMMC1, TEGRA20_CLK_SDMMC1, 1);
+	clks[TEGRA20_CLK_SDMMC2] = tegra_clk_register_periph("sdmmc2",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_SDMMC2, TEGRA20_CLK_SDMMC2, 1);
+	clks[TEGRA20_CLK_SDMMC3] = tegra_clk_register_periph("sdmmc3",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_SDMMC3, TEGRA20_CLK_SDMMC3, 1);
+	clks[TEGRA20_CLK_SDMMC4] = tegra_clk_register_periph("sdmmc4",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_SDMMC4, TEGRA20_CLK_SDMMC4, 1);
 }
 
 static struct tegra_clk_init_table init_table[] = {
-	{pll_p,		clk_max,	216000000,	1},
-	{pll_p_out1,	clk_max,	28800000,	1},
-	{pll_p_out2,	clk_max,	48000000,	1},
-	{pll_p_out3,	clk_max,	72000000,	1},
-	{pll_p_out4,	clk_max,	24000000,	1},
-	{pll_c,		clk_max,	600000000,	1},
-	{pll_c_out1,	clk_max,	120000000,	1},
-	{uarta,		pll_p,		0,		1},
-	{uartb,		pll_p,		0,		1},
-	{uartc,		pll_p,		0,		1},
-	{uartd,		pll_p,		0,		1},
-	{uarte,		pll_p,		0,		1},
-	{sdmmc1,	pll_p,		48000000,	0},
-	{sdmmc2,	pll_p,		48000000,	0},
-	{sdmmc3,	pll_p,		48000000,	0},
-	{sdmmc4,	pll_p,		48000000,	0},
-	{clk_max,	clk_max,	0,		0}, /* sentinel */
+	{TEGRA20_CLK_PLL_P,		TEGRA20_CLK_CLK_MAX,	216000000,	1},
+	{TEGRA20_CLK_PLL_P_OUT1,	TEGRA20_CLK_CLK_MAX,	28800000,	1},
+	{TEGRA20_CLK_PLL_P_OUT2,	TEGRA20_CLK_CLK_MAX,	48000000,	1},
+	{TEGRA20_CLK_PLL_P_OUT3,	TEGRA20_CLK_CLK_MAX,	72000000,	1},
+	{TEGRA20_CLK_PLL_P_OUT4,	TEGRA20_CLK_CLK_MAX,	24000000,	1},
+	{TEGRA20_CLK_PLL_C,		TEGRA20_CLK_CLK_MAX,	600000000,	1},
+	{TEGRA20_CLK_PLL_C_OUT1,	TEGRA20_CLK_CLK_MAX,	120000000,	1},
+	{TEGRA20_CLK_UARTA,		TEGRA20_CLK_PLL_P,	0,		1},
+	{TEGRA20_CLK_UARTB,		TEGRA20_CLK_PLL_P,	0,		1},
+	{TEGRA20_CLK_UARTC,		TEGRA20_CLK_PLL_P,	0,		1},
+	{TEGRA20_CLK_UARTD,		TEGRA20_CLK_PLL_P,	0,		1},
+	{TEGRA20_CLK_UARTE,		TEGRA20_CLK_PLL_P,	0,		1},
+	{TEGRA20_CLK_SDMMC1,		TEGRA20_CLK_PLL_P,	48000000,	0},
+	{TEGRA20_CLK_SDMMC2,		TEGRA20_CLK_PLL_P,	48000000,	0},
+	{TEGRA20_CLK_SDMMC3,		TEGRA20_CLK_PLL_P,	48000000,	0},
+	{TEGRA20_CLK_SDMMC4,		TEGRA20_CLK_PLL_P,	48000000,	0},
+	{TEGRA20_CLK_CLK_MAX,		TEGRA20_CLK_CLK_MAX,	0,	0}, /* sentinel */
 };
 
 static int tegra20_car_probe(struct device_d *dev)

@@ -341,7 +333,7 @@ static int tegra20_car_probe(struct device_d *dev)
 	tegra20_pll_init();
 	tegra20_periph_init();
 
-	tegra_init_from_table(init_table, clks, clk_max);
+	tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
 
 	/* speed up system bus */
 	writel(CRC_SCLK_BURST_POLICY_SYS_STATE_RUN <<

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Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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