ARM: qcom: Add initial APQ8064 SoC and IFC6410 board device trees
Subsystems (6)
PATCH v2 1/1 ARM: qcom: Add initial APQ8064 SoC and IFC6410 board device trees
Add basic APQ8064 SoC include device tree and support for basic booting on the IFC6410 board.
---
v2:
* created a v2.0 apq8064.dtsi to handle differences in Si rev in future
* changed /include/ to #include
* added PMU node
* dropped interrupts from cpus node, not currently part of binding
arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 12 +++ arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 + arch/arm/boot/dts/qcom-apq8064.dtsi | 154 +++++++++++++++++++++++++++++ arch/arm/mach-qcom/board.c | 1 + 5 files changed, 169 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts create mode 100644 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi create mode 100644 arch/arm/boot/dts/qcom-apq8064.dtsi
arch/arm/boot/dts/Makefile +1 -0
@@ -232,6 +232,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8064-ifc6410.dtb \ qcom-apq8074-dragonboard.dtb \ qcom-ipq8064-ap148.dtb \ qcom-msm8660-surf.dtb \
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts new file +12 -0
@@ -0,0 +1,12 @@ +#include "qcom-apq8064-v2.0.dtsi" + +/ { + model = "Qualcomm APQ8064/IFC6410"; + compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; + + soc { + serial at 16640000 { + status = "ok"; + }; + }; +};
arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi new file +1 -0
@@ -0,0 +1 @@ +#include "qcom-apq8064.dtsi"
arch/arm/boot/dts/qcom-apq8064.dtsi new file +154 -0
154 lines not on this page · raw message
arch/arm/mach-qcom/board.c +1 -0
@@ -15,6 +15,7 @@#include <asm/mach/arch.h> static const char *const qcom_dt_match[]__initconst = { +"qcom,apq8064" ,"qcom,apq8074-dragonboard" ,"qcom,ipq8062" ,"qcom,ipq8064" ,
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
Hi Kumar,
<snip>
arch/arm/boot/dts/qcom-apq8064.dtsi line 73
Quoted 6 lines
arch/arm/boot/dts/qcom-apq8064.dtsi new file +6
-0+ intc: interrupt-controller at 2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02000000 0x1000 >, + < 0x02002000 0x1000 >;
extra space around numbers.
I wonder what is the preferred way of describing the properties:
reg = <0x02000000 0x1000>,
<0x02002000 0x1000>;
or
reg = <0x02000000 0x1000>, <0x02002000 0x1000>;
This file mixes the above two ways of describing.
Quoted 8 lines
arch/arm/boot/dts/qcom-apq8064.dtsi new file +8
-0+ }; + + timer at 200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, + <1 3 0x301>; + reg = <0x0200a000 0x100>;
arch/arm/boot/dts/qcom-apq8064.dtsi line 91
Quoted 10 lines
arch/arm/boot/dts/qcom-apq8064.dtsi new file +10
-0+ clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x80000>; + }; + + acc0: clock-controller at 2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + }; +
regards,
Stan
Quoted 12 lines · Kumar Gala
Add basic APQ8064 SoC include device tree and support for basic booting on the IFC6410 board.
Signed-off-by Kumar Gala <[email protected]>---
v2:
* created a v2.0apq8064.dtsito handle differences in Si rev in future
* changed /include/ to #include
* added PMU node
* dropped interrupts from cpus node, not currently part of binding
Quoted 5 lines
arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 12 +++ arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 + arch/arm/boot/dts/qcom-apq8064.dtsi | 154 +++++++++++++++++++++++++++++ arch/arm/mach-qcom/board.c | 1 +
I suspect the arm-soc folks would like us to split the mach-qcom changes from the dts changes.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Quoted 10 lines · Kumar Gala
arch/arm/boot/dts/qcom-apq8064.dtsi new file +4
-0@@ -0,0 +1,154 @@ +/dts-v1/; + +#include "skeleton.dtsi" +#include <dt-bindings/clock/qcom,gcc-msm8960.h>
arch/arm/boot/dts/qcom-apq8064.dtsi line 14
Quoted 10 lines
arch/arm/boot/dts/qcom-apq8064.dtsi new file +10
-0+ +/ { + model = "Qualcomm APQ8064"; + compatible = "qcom,apq8064"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,krait";
This doesn't follow the binding. We're supposed to put the compatible in each cpu node even though it's always the same.
Quoted 26 lines
arch/arm/boot/dts/qcom-apq8064.dtsi new file +26
-0+ enable-method = "qcom,kpss-acc-v1"; + + cpu at 0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu at 1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + cpu at 2 { + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + }; +
arch/arm/boot/dts/qcom-apq8064.dtsi line 50
Quoted 10 lines
arch/arm/boot/dts/qcom-apq8064.dtsi new file +10
-0+ cpu at 3 { + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + }; + + L2: l2-cache { + compatible = "cache";
This would be "qcom,arch-cache" if the binding is accepted.
arch/arm/boot/dts/qcom-apq8064.dtsi line 52
Quoted 2 lines
arch/arm/boot/dts/qcom-apq8064.dtsi new file +2
-0+ cache-level = <2>; + interrupts = <0 2 0x4>;
These interrupts here are also not accepted as a binding yet.
Quoted 5 lines
arch/arm/boot/dts/qcom-apq8064.dtsi new file +5
-0+ }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu";
arch/arm/boot/dts/qcom-apq8064.dtsi line 67
Quoted 10 lines
arch/arm/boot/dts/qcom-apq8064.dtsi new file +10
-0+ interrupts = <1 10 0x304>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + +
Nit: Weird two newlines here
Quoted 8 lines
arch/arm/boot/dts/qcom-apq8064.dtsi new file +8
-0+ intc: interrupt-controller at 2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02000000 0x1000 >, + < 0x02002000 0x1000 >; + }; +
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation