PPC 85xx: Add support for QEMU's ppce500 PV machine

index f9f358e..cc0bf76 100644
@@ -50,6 +50,37 @@ static void write_cell(u8 *addr, u64 val, int size)
 }
 
 /**
+ * fdt_getprop_u32_default_node - Return a node's property or a default
+ *
+ * @fdt: ptr to device tree
+ * @off: offset of node
+ * @cell: cell offset in property
+ * @prop: property name
+ * @dflt: default value if the property isn't found
+ *
+ * Convenience function to return a node's property or a default value if
+ * the property doesn't exist.
+ */
+u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
+				const char *prop, const u32 dflt)
+{
+	const fdt32_t *val;
+	int len;
+
+	val = fdt_getprop(fdt, off, prop, &len);
+
+	/* Check if property exists */
+	if (!val)
+		return dflt;
+
+	/* Check if property is long enough */
+	if (len < ((cell + 1) * sizeof(uint32_t)))
+		return dflt;
+
+	return fdt32_to_cpu(*val);
+}
+
+/**
  * fdt_getprop_u32_default - Find a node and return it's property or a default
  *
  * @fdt: ptr to device tree

@@ -63,18 +94,13 @@ static void write_cell(u8 *addr, u64 val, int size)
 u32 fdt_getprop_u32_default(const void *fdt, const char *path,
 				const char *prop, const u32 dflt)
 {
-	const fdt32_t *val;
 	int off;
 
 	off = fdt_path_offset(fdt, path);
 	if (off < 0)
 		return dflt;
 
-	val = fdt_getprop(fdt, off, prop, NULL);
-	if (val)
-		return fdt32_to_cpu(*val);
-	else
-		return dflt;
+	return fdt_getprop_u32_default_node(fdt, off, 0, prop, dflt);
 }
 
 /**

index 9871e2f..3e1be57 100644
@@ -12,6 +12,8 @@
 
 #include <libfdt.h>
 
+u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
+				const char *prop, const u32 dflt);
 u32 fdt_getprop_u32_default(const void *fdt, const char *path,
 				const char *prop, const u32 dflt);
 int fdt_chosen(void *fdt, int force);

index cc0bf76..fcd2523 100644
@@ -1435,3 +1435,97 @@ u64 fdt_get_base_address(void *fdt, int node)
 
 	return prop ? fdt_translate_address(fdt, node, prop + naddr) : 0;
 }
+
+/*
+ * Read a property of size <prop_len>. Currently only supports 1 or 2 cells.
+ */
+static int fdt_read_prop(const fdt32_t *prop, int prop_len, int cell_off,
+			 uint64_t *val, int cells)
+{
+	const fdt32_t *prop32 = &prop[cell_off];
+	const fdt64_t *prop64 = (const fdt64_t *)&prop[cell_off];
+
+	if ((cell_off + cells) > prop_len)
+		return -FDT_ERR_NOSPACE;
+
+	switch (cells) {
+	case 1:
+		*val = fdt32_to_cpu(*prop32);
+		break;
+	case 2:
+		*val = fdt64_to_cpu(*prop64);
+		break;
+	default:
+		return -FDT_ERR_NOSPACE;
+	}
+
+	return 0;
+}
+
+/**
+ * fdt_read_range - Read a node's n'th range property
+ *
+ * @fdt: ptr to device tree
+ * @node: offset of node
+ * @n: range index
+ * @child_addr: pointer to storage for the "child address" field
+ * @addr: pointer to storage for the CPU view translated physical start
+ * @len: pointer to storage for the range length
+ *
+ * Convenience function that reads and interprets a specific range out of
+ * a number of the "ranges" property array.
+ */
+int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr,
+		   uint64_t *addr, uint64_t *len)
+{
+	int pnode = fdt_parent_offset(fdt, node);
+	const fdt32_t *ranges;
+	int pacells;
+	int acells;
+	int scells;
+	int ranges_len;
+	int cell = 0;
+	int r = 0;
+
+	/*
+	 * The "ranges" property is an array of
+	 * { <child address> <parent address> <size in child address space> }
+	 *
+	 * All 3 elements can span a diffent number of cells. Fetch their size.
+	 */
+	pacells = fdt_getprop_u32_default_node(fdt, pnode, 0, "#address-cells", 1);
+	acells = fdt_getprop_u32_default_node(fdt, node, 0, "#address-cells", 1);
+	scells = fdt_getprop_u32_default_node(fdt, node, 0, "#size-cells", 1);
+
+	/* Now try to get the ranges property */
+	ranges = fdt_getprop(fdt, node, "ranges", &ranges_len);
+	if (!ranges)
+		return -FDT_ERR_NOTFOUND;
+	ranges_len /= sizeof(uint32_t);
+
+	/* Jump to the n'th entry */
+	cell = n * (pacells + acells + scells);
+
+	/* Read <child address> */
+	if (child_addr) {
+		r = fdt_read_prop(ranges, ranges_len, cell, child_addr,
+				  acells);
+		if (r)
+			return r;
+	}
+	cell += acells;
+
+	/* Read <parent address> */
+	if (addr)
+		*addr = fdt_translate_address(fdt, node, ranges + cell);
+	cell += pacells;
+
+	/* Read <size in child address space> */
+	if (len) {
+		r = fdt_read_prop(ranges, ranges_len, cell, len, scells);
+		if (r)
+			return r;
+	}
+
+	return 0;
+}

index 3e1be57..b28fae6 100644
@@ -87,6 +87,8 @@ int fdt_add_edid(void *blob, const char *compat, unsigned char *buf);
 int fdt_verify_alias_address(void *fdt, int anode, const char *alias,
 			      u64 addr);
 u64 fdt_get_base_address(void *fdt, int node);
+int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr,
+		   uint64_t *addr, uint64_t *len);
 
 enum fdt_status {
 	FDT_STATUS_OKAY,

index 81aeadd..18366a7 100644
@@ -767,8 +767,6 @@ skip_l2:
 	return 0;
 }
 
-extern void setup_ivors(void);
-
 void arch_preboot_os(void)
 {
 	u32 msr;

@@ -781,8 +779,6 @@ void arch_preboot_os(void)
 	msr = mfmsr();
 	msr &= ~(MSR_ME|MSR_CE);
 	mtmsr(msr);
-
-	setup_ivors();
 }
 
 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)

index 8748ecd..fed8df9 100644
@@ -236,20 +236,26 @@ void init_addr_map(void)
 }
 #endif
 
-unsigned int
-setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
+uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
+		       enum tlb_map_type map_type)
 {
 	int i;
 	unsigned int tlb_size;
-	unsigned int wimge = MAS2_M;
-	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+	unsigned int wimge;
+	unsigned int perm;
 	unsigned int max_cam, tsize_mask;
-	u64 size, memsize = (u64)memsize_in_meg << 20;
 
+	if (map_type == TLB_MAP_RAM) {
+		perm = MAS3_SX|MAS3_SW|MAS3_SR;
+		wimge = MAS2_M;
 #ifdef CONFIG_SYS_PPC_DDR_WIMGE
-	wimge = CONFIG_SYS_PPC_DDR_WIMGE;
+		wimge = CONFIG_SYS_PPC_DDR_WIMGE;
 #endif
-	size = min(memsize, CONFIG_MAX_MEM_MAPPED);
+	} else {
+		perm = MAS3_SW|MAS3_SR;
+		wimge = MAS2_I|MAS2_G;
+	}
+
 	if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
 		/* Convert (4^max) kB to (2^max) bytes */
 		max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;

@@ -261,11 +267,11 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 	}
 
 	for (i = 0; size && i < 8; i++) {
-		int ram_tlb_index = find_free_tlbcam();
+		int tlb_index = find_free_tlbcam();
 		u32 camsize = __ilog2_u64(size) & tsize_mask;
-		u32 align = __ilog2(ram_tlb_address) & tsize_mask;
+		u32 align = __ilog2(v_addr) & tsize_mask;
 
-		if (ram_tlb_index == -1)
+		if (tlb_index == -1)
 			break;
 
 		if (align == -2) align = max_cam;

@@ -277,18 +283,29 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 
 		tlb_size = camsize - 10;
 
-		set_tlb(1, ram_tlb_address, p_addr,
-			MAS3_SX|MAS3_SW|MAS3_SR, wimge,
-			0, ram_tlb_index, tlb_size, 1);
+		set_tlb(1, v_addr, p_addr, perm, wimge,
+			0, tlb_index, tlb_size, 1);
 
 		size -= 1ULL << camsize;
-		memsize -= 1ULL << camsize;
-		ram_tlb_address += 1UL << camsize;
+		v_addr += 1UL << camsize;
 		p_addr += 1UL << camsize;
 	}
 
+	return size;
+}
+
+unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
+				 unsigned int memsize_in_meg)
+{
+	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+	u64 memsize = (u64)memsize_in_meg << 20;
+
+	memsize = min(memsize, CONFIG_MAX_MEM_MAPPED);
+	memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
+
 	if (memsize)
 		print_size(memsize, " left unmapped\n");
+
 	return memsize_in_meg;
 }
 

index cadaeef..5aa916f 100644
@@ -509,6 +509,14 @@ extern void print_tlbcam(void);
 extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
 extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
 
+enum tlb_map_type {
+	TLB_MAP_RAM,
+	TLB_MAP_IO,
+};
+
+extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
+			      enum tlb_map_type map_type);
+
 extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
 
 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \

index 3e99b07..2c8126c 100644
@@ -272,7 +272,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
 #define CONFIG_SYS_FSL_TBCLK_DIV 8
 #endif
-unsigned long get_tbclk (void)
+__weak unsigned long get_tbclk (void)
 {
 	unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
 

@@ -338,7 +338,8 @@ void mpc85xx_reginfo(void)
 	!defined(CONFIG_SYS_INIT_L2_ADDR)
 phys_size_t initdram(int board_type)
 {
-#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
+	defined(CONFIG_QEMU_E500)
 	return fsl_ddr_sdram_size();
 #else
 	return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;

index 993b8b8..998781b 100644
@@ -79,7 +79,7 @@ void setup_ifc(void)
 #endif
 
 /* We run cpu_init_early_f in AS = 1 */
-void cpu_init_early_f(void)
+void cpu_init_early_f(void *fdt)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
 	int i;

@@ -102,6 +102,12 @@ void cpu_init_early_f(void)
 	for (i = 0; i < sizeof(gd_t); i++)
 		((char *)gd)[i] = 0;
 
+	/*
+	 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
+	 * so we need to populate it before it accesses it.
+	 */
+	gd->fdt_blob = fdt;
+
 	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
 	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
 	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);

index fed8df9..129ec66 100644
@@ -24,7 +24,7 @@ void invalidate_tlb(u8 tlb)
 		mtspr(MMUCSR0, 0x2);
 }
 
-void init_tlbs(void)
+__weak void init_tlbs(void)
 {
 	int i;
 

index df44451..e376783 100644
@@ -797,6 +797,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
+#elif defined(CONFIG_QEMU_E500)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xe0000000
+
 #else
 #error Processor type not defined for this platform
 #endif

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