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ARM: dts: imx27-pdk: Keep the dt nodes sorted

PATCH New Fabio Estevam 2 participants 4 messages Apr 13, 2014 – Apr 14, 2014

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Fabio Estevam

author reviewer
#0 lore raw

PATCH v4 1/3 ARM: dts: imx27-pdk: Keep the dt nodes sorted

From: Fabio Estevam <[email protected]>

For better readability keep the dt nodes sorted.

---
Changes since v3:
- None
Changes since v2:
- None
Changes since v1:
- Newly introduced

 arch/arm/boot/dts/imx27-pdk.dts | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
arch/arm/boot/dts/imx27-pdk.dts +4 -3
index 28c83bc..bd95265 100644
@@ -21,11 +21,12 @@
 	};
 };
 
-&uart1 {
-	fsl,uart-has-rtscts;
+
+&fec {
 	status = "okay";
 };
 
-&fec {
+&uart1 {
+	fsl,uart-has-rtscts;
 	status = "okay";
 };
Signature · 1 line
1.8.3.2
author reviewer
#1 lore raw

PATCH v4 2/3 ARM: dts: imx27-pdk: Pass the UART1 pin configuration

From: Fabio Estevam <[email protected]>

Provide an entry for the UART1 pin muxing.

---
Changes since v3:
- None
Changes since v2:
- None
Changes since v1:
- Keep the iomuxc node at the bottom

 arch/arm/boot/dts/imx27-pdk.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
arch/arm/boot/dts/imx27-pdk.dts +15 -0
index bd95265..e0f4213 100644
@@ -28,5 +28,20 @@
 
 &uart1 {
 	fsl,uart-has-rtscts;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
 	status = "okay";
 };
+
+&iomuxc {
+	imx27-pdk {
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX27_PAD_UART1_TXD__UART1_TXD 0x0
+				MX27_PAD_UART1_RXD__UART1_RXD 0x0
+				MX27_PAD_UART1_CTS__UART1_CTS 0x0
+				MX27_PAD_UART1_RTS__UART1_RTS 0x0
+			>;
+		};
+	};
+};
Signature · 1 line
1.8.3.2
author reviewer
#2 lore raw

PATCH v4 3/3 ARM: dts: imx27-pdk: Pass the FEC pin configuration

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

Provide an entry for the FEC pin muxing.

---
Changes since v3:
- Fix closing } in the pinctrl_fec node
Changes since v2:
- Keep iomux node sorted
Changes since v1:
- Keep the iomuxc node at the bottom

 arch/arm/boot/dts/imx27-pdk.dts | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
arch/arm/boot/dts/imx27-pdk.dts +26 -0
index e0f4213..430b72b 100644
@@ -23,6 +23,9 @@
 
 
 &fec {
+	phy-mode = "mii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec>;
 	status = "okay";
 };
 
@@ -35,6 +38,29 @@
 
 &iomuxc {
 	imx27-pdk {
+		pinctrl_fec: fecgrp {
+			fsl,pins = <
+				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+				MX27_PAD_ATA_DATA13__FEC_COL 0x0
+				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+			>;
+		};
+
 		pinctrl_uart1: uart1grp {
 			fsl,pins = <
 				MX27_PAD_UART1_TXD__UART1_TXD 0x0
Signature · 1 line
1.8.3.2